JP2009277004A - Data transfer device and data transfer system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data transfer device for efficiently transferring data by preventing a malfunction. <P>SOLUTION: This data transfer device for transferring data through a bus 14 is provided with: a device controller 12 for writing data in a target device 13; an initiator core 11 for DMA-transferring the data through the bus to the device controller, and for outputting a transfer completion notification request signal S11 to the device controller. When receiving the transfer completion notification request signal, the device controller outputs a transfer completion notification signal S12 when all the data are written in the target device. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a data transfer device and a data transfer system.

  In recent years, in a system LSI, an initiator core directly transfers data (DMA transfer) to a target device such as a memory without going through a processor, and then the data stored in the target device is used by other initiators and processors. Such processing is performed.

  In such processing, the initiator core notifies the system by interruption that the data transfer has been completed. The system detects that the data stored in the target device is valid by processing the interrupt (see, for example, Patent Document 1).

  In general, data transfer from an initiator core to a target device is performed via an on-chip bus and a device controller. First, the initiator core executes a write transaction on the on-chip bus and starts outputting transfer data. The device controller receives the transfer data via the on-chip bus and stores it in the target device.

  Then, the initiator core outputs the last transfer data on the on-chip bus, and ends the data transfer when receiving the receipt response from the device controller. Depending on the protocol of the on-chip bus, there may be a case where a receipt response from the device controller does not occur. In such a case, the data transfer is terminated by outputting the last transfer data on the on-chip bus.

  Then, when the data transfer is completed, the initiator core notifies the system (processor) of the completion of the data transfer by generating an interrupt. When the interrupt becomes valid, the processor confirms the cause of the interrupt and detects completion of data transfer by the initiator core. Thereafter, the system can begin processing using the transferred data.

  Here, the data transfer from the initiator core to the device controller executed on the on-chip bus and the data transfer from the device controller to the target device are executed as independent transfers based on different transfer protocols. Therefore, it is difficult for the initiator core to detect that the transfer data is stored (written) in the target device.

  Also, the transfer path from the initiator core to the device controller is often a more complicated path such as via a plurality of on-chip buses via a bus bridge. In that case, it becomes even more difficult for the initiator core to confirm the data transfer status between the device controller and the target device.

  As a result, depending on the structure and function of the on-chip bus or device controller, the start of processing using transfer data by the system may overtake transfer data storage (writing) to the target device and cause malfunction.

  In order to prevent such overtaking, a read transaction (dummy read) is issued to the target device after the initiator core performs a write transaction of the last transfer data. At this time, the read address issued by the initiator core is in an area including the address where the last transfer data is stored.

  The initiator core confirms that writing of transfer data to the target device is completed by receiving read data or a response from the target device. Then, a data transfer completion interrupt is generated.

However, such a method generates a (redundant) read transaction that is originally unnecessary. In general, the latency (data waiting time from the memory) of the read transaction is larger than that of the write transaction, which has a problem that the throughput of the system is lowered.
Japanese Patent Laid-Open No. 10-293741

  It is an object of the present invention to provide a data transfer apparatus and a data transfer system that can prevent malfunctions and efficiently transfer data.

  A data transfer apparatus according to an aspect of the present invention is a data transfer apparatus that performs data transfer via a bus, and a DMA controller that writes data to a target device and DMA transfers the data to the device controller via the bus And an initiator core that outputs a transfer completion notification request signal to the device controller. When the device controller receives the transfer completion notification request signal, the device controller accompanies all writing of the data to the target device. A transfer completion notification signal is output.

  A data transfer system according to an aspect of the present invention is a data transfer system that performs DMA transfer of data to a storage device via a bus, a processor connected to the bus, and a device controller that writes the data to the storage device. And an initiator core that has a register and DMA transfers the data to the device controller via the bus and outputs a transfer completion notification request signal to the device controller. The device controller notifies the transfer completion notification When a request signal is received, a transfer completion notification signal is output as all the data is written to the storage device, and the initiator core generates an interrupt signal based on the transfer completion notification signal and interrupts the register. Cause information is set, and the processor It is characterized in detecting the interrupt cause information set in the register on the basis of the signal.

  A data transfer system according to an aspect of the present invention is a data transfer system that DMA-transfers data to a storage device via a bus, and includes a processor connected to the bus and a register that stores interrupt factor information. A device controller that writes the data to the storage device; and an initiator core that DMA-transfers the data to the device controller via the bus and outputs a transfer completion notification request signal to the device controller. When the controller receives the transfer completion notification request signal, the controller generates an interrupt signal when all the data is written to the storage device, and the processor generates the interrupt factor stored in the register based on the interrupt signal. It is characterized by detecting information.

  According to the present invention, it is possible to prevent malfunctions and efficiently transfer data.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  (First Embodiment) FIG. 1 shows a schematic configuration of a data transfer system according to a first embodiment of the present invention. The data transfer system includes an initiator core 11, a device controller 12, a target device 13, an on-chip bus 14, and a processor 15. For example, the initiator core 11 is a network controller, the device controller 12 is a DRAM controller, and the target device 13 is a DRAM.

  The initiator core 11 is connected to the on-chip bus 14 and performs DMA (Direct Memory Access) transfer of data. In addition, the initiator core 11 outputs a transfer completion notification request signal S11, and issues an interrupt when receiving the transfer completion notification signal S12.

  The device controller 12 controls the target device 13. The device controller 12 is given the data output from the initiator core 11 via the on-chip bus 14 and writes this data to the target device 13. Further, upon receiving the transfer completion notification request signal S11 from the initiator core 11, the device controller 12 outputs the transfer completion notification signal S12 when writing of all data (final data) to the target device 13 is completed.

  The transfer completion notification request signal S11 and the transfer completion notification signal S12 may be implemented by signals defined by the on-chip bus 14 standard, or may be implemented as independent signals different from the on-chip bus 14. .

  A data transfer method in such a data transfer system will be described with reference to a flowchart shown in FIG. 2 and a timing chart shown in FIG. First, the initiator core 11 issues a write command on the on-chip bus 14 and starts data transfer (DMA write transfer) to the device controller 12 (time T1). The initiator core 11 issues a transfer completion notification request (validate the transfer completion notification request signal S11) when a write command is issued.

  The DMA write transfer is executed by single transfer or burst transfer once or a plurality of times. For example, when the data width of the on-chip bus 14 is 64 bits (8 bytes) and the transfer data is 512 bytes, 64 single transfers (8 bytes transfer), 16 4 beats (8 bytes × 4) Times) burst transfer or one 64 beat (8 bytes × 64 times) burst transfer.

  In the example shown in FIG. 3, data transfer is executed by one burst transfer.

  When the initiator core 11 detects that the last data (data Dn) output on the on-chip bus 14 has been received by the device controller 12, the initiator core 11 ends the DMA transfer (time T2). If a buffer for temporarily storing data is provided between the initiator core 11 and the device controller 12, the DMA transfer is terminated when the last data is written in the buffer.

  When the writing of the last data to the target device 13 is completed, the device controller 12 issues a transfer completion notification (validate the transfer completion notification signal S12) (time T3).

  Upon receiving the transfer completion notification from the device controller 12, the initiator core 11 issues an interrupt to the processor 15 to notify the completion of data transfer. The initiator core 11 sets interrupt factor information in an internal register (not shown) of the initiator core 11 when issuing an interrupt.

  When the interrupt from the initiator core 11 becomes valid, the processor 15 refers to the information set in the internal register of the initiator core 11 to confirm the interrupt factor and detect that the data transfer by the initiator core 11 is completed. As a result, another initiator (not shown) can start processing using the data transferred by the initiator core 11.

  In the example illustrated in FIGS. 2 and 3, the device controller 12 has issued a transfer completion notification when the last data has been written to the target device 13, but access to the target device 13 from other initiators. However, if it is determined that write access from the initiator core 11 is not overtaken, a transfer completion notification can be issued even if data writing to the target device 13 is not completed.

  For example, when the device controller 12 has a scheduling function, a transfer completion notification is issued when the last data write is at the head of the queue waiting to be executed (executed after the access to the target device 13 being executed). it can.

  By receiving the transfer completion notification, the initiator core 11 can detect that the writing to the target device 13 has been completed or that the writing has been completed.

  In addition, since the initiator core 11 generates an interrupt to the processor 15 after receiving the transfer completion notification, the processing by the other initiator cores using the data transferred to the target device 13 is executed before the data transfer is completed. It is possible to prevent malfunction.

  Moreover, since a redundant waiting time is not required, a decrease in throughput can be suppressed.

  As described above, the data transfer system according to the present embodiment can prevent malfunction and perform data transfer efficiently.

  (Second Embodiment) FIG. 4 shows a schematic configuration of a data transfer system according to a second embodiment of the present invention. The data transfer system includes an initiator core 21, a device controller 22, a target device 23, an on-chip bus 24, a processor 25, and an interrupt signal timing control circuit 26.

  The initiator core 21 is connected to the on-chip bus 24 and performs DMA transfer of data. Further, the initiator core 21 outputs a transfer completion notification request signal S21 to the device controller 22 and outputs an interrupt signal S23 to the interrupt signal timing control circuit 26.

  The device controller 22 controls the target device 23. The device controller 22 receives data output from the initiator core 21 via the on-chip bus 24 and writes this data to the target device 23. Further, upon receiving the transfer completion notification request signal S21 from the initiator core 21, the device controller 22 notifies the interrupt signal timing control circuit 26 of the transfer completion when the writing of all data (final data) to the target device 23 is completed. The signal S22 is output.

  The transfer completion notification request signal S21 and the transfer completion notification signal S22 may be implemented by signals defined in the on-chip bus 24 standard, or may be implemented as independent signals different from the on-chip bus 24. .

  The interrupt signal timing control circuit 26 outputs an interrupt signal S24 to the processor 25 based on the interrupt signal S23 and the transfer completion notification signal S22. The interrupt signal S24 may be input directly to the processor 25, or may be input via an interrupt controller (not shown) or the like.

  A data transfer method in such a data transfer system will be described with reference to a flowchart shown in FIG. 5 and a timing chart shown in FIG. First, the initiator core 21 issues a write command on the on-chip bus 24 and starts data transfer (DMA write transfer) to the device controller 22 (time T1). The initiator core 21 issues a transfer completion notification request (validate the transfer completion notification request signal S21) when a write command is issued.

  When the initiator core 21 detects that the last data output on the on-chip bus 24 has been received by the device controller 22, the initiator core 21 ends the DMA transfer (time T2). When a buffer for temporarily storing data is provided between the initiator core 21 and the device controller 12, the DMA transfer ends when the last data is written in the buffer.

  When the initiator core 21 completes the DMA transfer, it enables the interrupt signal S23. At this time, the initiator core 21 sets interrupt factor information in an internal register (not shown).

  When the writing of the last data to the target device 23 is completed, the device controller 22 issues a transfer completion notification (enables the transfer completion notification signal S22) (time T3).

  When both the interrupt signal S23 from the initiator core 21 and the transfer completion notification signal S22 from the device controller 22 become valid, the interrupt signal timing control circuit 26 issues an interrupt to the processor 25 (enables the interrupt signal S24). The completion of data transfer is notified (time T4).

  When the interrupt from the interrupt signal timing control circuit 26 becomes valid, the processor 25 refers to the information set in the internal register of the initiator core 21 to check the cause of the interrupt and confirm that the data transfer by the initiator core 21 is completed. To detect. As a result, another initiator (not shown) can start processing using the data transferred by the initiator core 21.

  In the example shown in FIGS. 5 and 6, the device controller 22 has issued a transfer completion notification when the last data has been written to the target device 23, but access to the target device 23 from other initiators. However, if it is determined that write access from the initiator core 21 is not overtaken, a transfer completion notification can be issued even if data writing to the target device 23 is not completed.

  For example, when the device controller 22 has a scheduling function, a transfer completion notification is issued when the last data write is at the head of the queue waiting to be executed (executed next to the target device 23 being executed). it can.

  When the interrupt signal timing control circuit 26 receives the interrupt signal S23 from the initiator core 21 and the transfer completion notification from the device controller 22, the writing to the target device 23 is completed or the writing is completed. It can be detected that it has been confirmed.

  Then, the interrupt signal timing control circuit 26 generates an interrupt to the processor 25 after detecting that the writing to the target device 23 has been completed or the completion of the writing has been detected. Processing by another initiator core that uses the transferred data is executed before the completion of the data transfer, thereby preventing a malfunction.

  Moreover, since a redundant waiting time is not required, a decrease in throughput can be suppressed.

  As described above, the data transfer system according to the present embodiment can prevent malfunction and perform data transfer efficiently.

  (Third Embodiment) FIG. 7 shows a schematic configuration of a data transfer system according to a third embodiment of the present invention. The data transfer system includes an initiator core 31, a device controller 32, a target device 33, an on-chip bus 34, and a processor 35.

  The initiator core 31 is connected to the on-chip bus 34 and performs DMA transfer of data. Further, the initiator core 31 outputs a transfer completion notification request signal S31.

  The device controller 32 controls the target device 33. The device controller 32 is given the data output from the initiator core 31 via the on-chip bus 34 and writes this data to the target device 33. Further, upon receiving the transfer completion notification request signal S31 from the initiator core 31, the device controller 32 outputs an interrupt signal S32 to the processor 35 when writing of all data (final data) to the target device 13 is completed.

  The transfer completion notification request signal S31 may be implemented by a signal defined by the standard of the on-chip bus 34, or may be implemented as an independent signal different from the on-chip bus 34.

  A data transfer method in such a data transfer system will be described with reference to a flowchart shown in FIG. 8 and a timing chart shown in FIG. First, the initiator core 31 issues a write command on the on-chip bus 34, and starts data transfer (DMA write transfer) to the device controller 32 (time T1). The initiator core 31 issues a transfer completion notification request (validate the transfer completion notification request signal S31) when a write command is issued.

  When the initiator core 31 detects that the last data output on the on-chip bus 34 has been received by the device controller 32 (receives an acknowledge corresponding to the last data), the initiator core 31 ends the DMA transfer (time T2).

  When a buffer for temporarily storing data is provided in the path from the initiator core 11 to the device controller 12, the DMA transfer is terminated when the last data is written in the buffer.

  When the writing of the last data to the target device 33 is completed, the device controller 32 notifies the processor 35 of the completion of the transfer (interrupt signal S32 is valid) (time T3).

  When the interrupt from the device controller 32 becomes valid, the processor 35 confirms information stored in the internal register 321 of the device controller 32. When the identification information of the initiator core 31 is stored in the internal register 321, the processor 35 reads the interrupt factor information set in the internal register (not shown) of the initiator core 31 based on this identification information. Check the interrupt factor.

  When the register 321 stores (copy) information equivalent to the internal register of the initiator core 31, the processor 35 reads the interrupt factor information stored in the register 321 and confirms the interrupt factor.

  The register 321 may store information acquired from the initiator core identification information of the on-chip bus 34, or the initiator core 31 may write information on an interrupt factor. Further, the state of the register 321 at the completion of data transfer may be defined in advance.

  The processor 35 can detect that the data transfer by the initiator core 31 is completed by checking the interrupt factor. As a result, another initiator (not shown) can start processing using the data transferred by the initiator core 31.

  In the example shown in FIGS. 8 and 9, the device controller 32 issues a transfer completion notification (enables the interrupt signal S <b> 32) when the writing of the last data to the target device 33 is completed. When it is determined that access to the target device 33 from the host does not overtake write access from the initiator core 31, a transfer completion notification can be issued even if data writing to the target device 33 is not completed.

  For example, when the device controller 32 has a scheduling function, a transfer completion notification is issued when the last data write is at the head of the queue waiting to be executed (executed after access to the target device 33 being executed). it can.

  The device controller 32 detects that the writing to the target device 33 has been completed or that it has been determined that the writing has been completed, and then transfers the data transferred to the target device 33 in order to generate an interrupt to the processor 35. It is possible to prevent a malfunction from occurring due to the processing performed by the other initiator cores using the ID being executed before the completion of the data transfer.

  Moreover, since a redundant waiting time is not required, a decrease in throughput can be suppressed.

  As described above, the data transfer system according to the present embodiment can prevent malfunction and perform data transfer efficiently.

  Each of the above-described embodiments is an example and should be considered as not limiting. For example, in the above embodiment, the transfer completion notification request is issued when the write command is issued (time T1). However, from the time when the write command is issued until the last write data (data Dn) is output from the initiator core. If it is between (time T1-T2), a transfer completion notification request can be issued at an arbitrary timing.

  The technical scope of the present invention is defined by the terms of the claims, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 is a schematic configuration diagram of a data transfer system according to a first embodiment of the present invention. It is a data transfer flow using the data transfer system according to the first embodiment. 4 is a timing chart of data transfer using the data transfer system according to the first embodiment. It is a schematic block diagram of the data transfer system by the 2nd Embodiment of this invention. It is a data transfer flow using the data transfer system according to the second embodiment. 6 is a timing chart of data transfer using the data transfer system according to the second embodiment. It is a schematic block diagram of the data transfer system by the 3rd Embodiment of this invention. It is a data transfer flow using the data transfer system according to the third embodiment. 12 is a timing chart of data transfer using the data transfer system according to the third embodiment.

Explanation of symbols

11 Initiator Core 12 Device Controller 13 Target Device 14 On-Chip Bus 15 Processor

Claims (5)

A data transfer device for transferring data via a bus,
A device controller that writes data to the target device;
An initiator core that DMA-transfers the data to the device controller via the bus and outputs a transfer completion notification request signal to the device controller;
With
When the device controller receives the transfer completion notification request signal, the device controller outputs a transfer completion notification signal with every writing of the data to the target device.   The data transfer apparatus according to claim 1, wherein the initiator core generates an interrupt signal based on the transfer completion notification signal.   And an interrupt signal timing control circuit for generating a second interrupt signal based on the first interrupt signal generated from the initiator core and the transfer completion notification signal upon completion of the DMA transfer of the data. The data transfer device according to claim 1. A data transfer system that DMA transfers data to a storage device via a bus,
A processor connected to the bus;
A device controller for writing the data to the storage device;
An initiator core having a register, DMA-transferring the data to the device controller via the bus, and outputting a transfer completion notification request signal to the device controller;
With
When the device controller receives the transfer completion notification request signal, the device controller outputs a transfer completion notification signal with all writing of the data to the storage device, and the initiator core generates an interrupt signal based on the transfer completion notification signal. And the interrupt factor information is set in the register, and the processor detects the interrupt factor information set in the register based on the interrupt signal. A data transfer system that DMA transfers data to a storage device via a bus,
A processor connected to the bus;
A device controller for storing interrupt factor information, and writing the data into the storage device;
An initiator core that DMA-transfers the data to the device controller via the bus and outputs a transfer completion notification request signal to the device controller;
With
When the device controller receives the transfer completion notification request signal, the device controller generates an interrupt signal with every writing of the data to the storage device, and the processor stores the register stored in the register based on the interrupt signal A data transfer system characterized by detecting interrupt factor information.

Images