JP2011085989A - Memory arbitration circuit and memory arbitration method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory arbitration circuit and a memory arbitration method for further shortening the latency of one bus master. <P>SOLUTION: A system having a memory arbitration circuit is provided with: a priority order determination part 22 for determining the priority order of bus masters A11, B12 and 13; and a signal generation part 23 for receiving memory access requests from the bus masters A11, B12 and 13, and generating a control signal for memory access on the basis of the priority order. When receiving the memory access request of a bus master A11 during the memory access processing of the bus master B12, the signal generation part 23 temporarily stops the memory access processing of the bus master B12, and processes the memory access request of the bus master A11. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a memory arbitration circuit and a memory arbitration method that arbitrate access requests when accessing a memory from a plurality of bus masters.

  FIG. 5 is a diagram showing a system having a conventional memory arbitration circuit. In the conventional system, for example, a bus master A111 that wants to shorten memory access latency, such as a CPU (Central Processing Unit), and a bus master B112 that wants to improve bus bandwidth efficiency by increasing burst access, such as an image display circuit, for example. And other bus masters 113, memories (DDR (Double-Data-Rate) 1, DDR 2, etc.) 130 accessed from all bus masters, and access requests to the memories from the respective bus masters to arbitrate access to the memory And a memory arbitration circuit 120. The memory arbitration circuit 120 includes a priority determination unit 122 that determines the bus master priority, and a signal generation unit 121 that generates a control signal (including address and data) to the memory.

  A control signal for access from each bus master is input to the priority determination unit 122 of the memory arbitration circuit 120. The priority determination unit 122 has a specific priority algorithm. Then, when there are accesses from a plurality of bus masters at the same time, the priority determination unit 122 determines the access order according to this specific priority algorithm, and gives priority to the access from the bus master having the higher priority selected earlier. The signal generator 121 is notified. The signal generation unit 121 generates a signal for accessing the memory.

  The memory 130 such as DDR1 or DDR2 has a plurality of banks and can perform high-speed burst access to the banks. The signal generation unit 121 issues a bank active command for each burst access, selects a bank, and then performs burst access for each continuous clock. In a memory system that can use such burst access, memory access efficiency can be improved by reducing the number of bank active commands as much as possible and increasing the amount of data that can be burst-accessed by a continuous clock.

  The memory arbitration circuit 120 determines whether or not the data in the same bank is accessed every access, and if it is the same, performs the burst access as it is. If they are different, in order to change the bank, a new bank active command is issued to perform burst access.

  Further, Patent Document 1 discloses a resource management device for the purpose of reducing the worst latency by avoiding concentration of access permission for the same master and improving the access efficiency according to the type of shared resource. . In this resource management device, when two or more masters among a plurality of masters are requesting access simultaneously, the bus arbitration unit receives an access permission within a predetermined time among the two or more access request masters. An access permission is preferentially given to an access request master whose number of times is less than the first set value.

JP 2007-207024 A

  However, in such a normal system or the system described in Patent Document 1, the burst length of each burst access is performed with a predetermined length. Therefore, the bus master waiting for access has a waiting time T1 during which access cannot be started until the previous burst access by another bus master is completed. In addition, when a plurality of bus masters are accessed, it cannot be guaranteed that the same bank is always active, and a waiting time T2 for issuing a bank active command may occur.

  In the conventional system, the access of the bus master A111 that wants to shorten the access latency of the CPU or the like causes a waiting time T1 and a waiting time T2 in the worst case. This waiting time becomes an operation waiting time of the CPU, and causes a reduction in CPU operation efficiency.

  When the bus master A111 is a CPU and the bus master B112 is an image display circuit, the data access amount and frequency of the bus master B112 are much larger than those of the bus master A111, and the burst length is usually increased to improve the bus bandwidth efficiency. . For this reason, the probability of the worst case in which the waiting time T1 and the waiting time T2 occur is very high.

  The memory arbitration circuit according to the present invention is a memory arbitration circuit that arbitrates access to the memory from the first and second bus masters, and determines a priority order of the first and second bus masters. And a signal generation unit that receives a memory access request from the first and second bus masters and generates a control signal for memory access based on the priority, and the signal generation unit includes: When the memory access request of the first bus master is received during the memory access process of the second bus master, the memory access process of the second bus master is temporarily stopped and the memory access request of the first bus master is processed. Is.

  A memory arbitration method according to the present invention is a memory arbitration method for arbitrating access to a memory from a first bus master and a second bus master, wherein the memory access of the first bus master is performed during memory access processing of the second bus master. When the request is received, the memory access process of the second bus master is temporarily stopped, and the memory access request of the first bus master is processed.

  In the present invention, when the first bus master makes an access request to the memory, the access processing of the second bus master is temporarily interrupted, and the access request of the first bus master is preferentially processed. Latency can be shortened.

  According to the present invention, it is possible to provide a memory arbitration circuit and a memory arbitration method that can shorten the latency of one bus master.

It is a figure which shows the system which has a memory arbitration circuit concerning Embodiment 1 of this invention. 3 is a flowchart showing an operation of the memory arbitration circuit according to the first exemplary embodiment of the present invention; It is a figure which shows the system which has a memory arbitration circuit concerning Embodiment 3 of this invention. It is a flowchart which shows operation | movement of the memory arbitration circuit concerning Embodiment 3 of this invention. It is a figure which shows the system which has the conventional memory arbitration circuit.

  Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings. In this embodiment, the present invention is applied to a system used in, for example, a television set provided with a memory arbitration circuit that processes memory access requests from a plurality of bus masters. Here, the plurality of bus masters include a bus master A that wants to shorten memory access latency, such as a CPU, and a bus master B that wants to improve bus bandwidth efficiency by increasing burst access, such as an image display circuit. .

  That is, in a system in which these bus masters share one memory such as DDR1 and DDR2, the bandwidth efficiency of the bus master B is not reduced, and the latency of the bus master A is increased. For this reason, the memory arbitration circuit according to the present embodiment interrupts the bus master of the other bus master that is currently being executed when the access of the bus master A that wants to shorten the latency of memory access, such as a CPU, occurs. A function for interrupting access of A is provided. In addition, after the access of the bus master A is completed, the previous access is resumed.

  Furthermore, the other memory arbitration circuit according to the present embodiment has a function of occupying a memory bank only for the bus master A and not permitting the access even if an access from another bus master is performed. Furthermore, another memory arbitration circuit according to the present embodiment detects the increase or decrease in the access of the bus master A for the function of determining whether these functions are valid or invalid, and for determining the access interrupt condition. A function of detecting a decrease in access of other bus masters, and further detecting an excessive number of accesses of the bus master A is provided. Hereinafter, this embodiment will be described in detail with reference to the accompanying drawings.

[Embodiment 1 of the present invention] ]
FIG. 1 is a diagram showing a system having a memory arbitration circuit according to the first exemplary embodiment of the present invention. The system according to the present embodiment includes a memory arbitration circuit 20 that receives an access request to the memory from the first bus master and the second bus master and arbitrates access to the memory. The first bus master is a bus master A11 that wants to shorten the latency of memory access, such as a CPU, and the second bus master is a bus master that wants to improve bus bandwidth efficiency by lengthening burst access, such as an image display circuit. B12. Furthermore, it has another bus master 13. The system further includes a memory 30 that is accessed by all bus masters 11, 12, 13. The memory 30 can be, for example, an SDRAM (Synchronous Dynamic Random Access Memory) such as DDR1 or DDR2. Of course, a memory other than the SFRAM may be used.

  The memory arbitration circuit 20 receives a memory access request from the bus master A 11, the bus master B 12, and the other bus master 13, and a priority determination unit 22 that determines the priority of access to the memory of the bus master A 11, the bus master B 12, and the other bus master 13. And a signal generator 21 for generating a control signal for memory access based on the priority. When the signal generation unit 21 receives the memory access request of the bus master A11 during the memory access process of the bus master B112, the signal generation unit 21 temporarily stops the memory access process of the bus master B12 and processes the memory access request of the bus master A11.

  In this way, by interrupting the memory access request of the bus master A11, the waiting time of the bus master A11 can be shortened. On the other hand, the signal generation unit 21 temporarily stops the memory access request of the bus master B12, and when the processing of the memory access request of the bus master A11 is completed, the waiting time of the bus master B12 is minimized by restarting the memory access request of the bus master B12. It can be.

  FIG. 2 is a flow example showing the operation of the memory arbitration circuit according to the present exemplary embodiment. Here, a case where interrupt processing is performed during memory access request processing of the bus master B12 will be described.

  In response to a memory access request from the bus master B12, the processing is started (step S1). If a memory access request from the bus master A11 is generated during execution of the memory access process of the bus master B12 (step S2: Yes), the memory access process of the bus master B12 is interrupted (step S3). Then, the memory access process of the bus master A11 is preferentially performed (step S4). Thereafter, when the memory access process of the bus master A11 is completed, the memory access process of the bus master B12 is resumed (step S5). Thereafter, the interrupt processing of the bus master A11 is performed again until the memory access processing of the bus master B12 is completed.

  In this embodiment, when the bus master A12 such as a CPU is accessed during burst access by the bus master B12, the signal generator 21 interrupts the access of the other bus master B12 currently being executed, Interrupt access. Since the burst access of the other bus master is immediately interrupted, there is no waiting time until the burst access of the other bus master is completed.

[Embodiment 2 of the present invention] ]
Next, a second embodiment of the present invention will be described. The system configuration in the present embodiment is the same as that in the first embodiment. However, the function of the signal generation unit 21 is different. The memory 30 according to the present embodiment is an SDRAM, and includes a plurality of blocks called banks that can operate memory cells independently. The signal generation unit 21 sets a specific bank among the plurality of banks as a dedicated bank for the bus master A11.

  When reading data from the memory 30, it is necessary to activate the bank from which data is read and precharge the data lines. This is the waiting time when reading data. On the other hand, by setting a certain bank as a dedicated bank for the bus master A11, when the data to be read has continuous addresses, there is no waiting time for the bank active command. Accordingly, it is possible to further reduce the waiting time for reading data from the bus master A11.

  When there is an access request from the bus master A11 during the burst read of the bus master B12, a dedicated bank is used for the read from the bus master A11. Therefore, the bank used by the bus master B12 can be kept active. Therefore, after completion of the access request processing of the bus master A11, burst reading of the bus master B12 can be immediately restarted, and the waiting time when the access request of the bus master B12 is restarted can be shortened.

  In the present embodiment, when the bus master A12 such as a CPU is accessed during burst access in the bus master B12, the signal generator 21 interrupts burst reading of the bus master B12 currently being executed, and the bus master A11 It has a function of interrupting access and a function of occupying a memory bank for the bus master A11. As a result, there is no waiting time for the bank active command generated when the bus master A11 is accessed and no waiting time until the burst access of the bus master B12 is completed. Also, once the memory access request of the bus master B12 is temporarily stopped and the processing of the memory access request of the bus master A11 is completed, the memory master request of the bus master B12 is resumed, so that no waiting time occurs when the bus master B12 resumes burst reading. . As a result, the waiting time for access to the memory 30 of the bus masters A11 and B12 can be further reduced.

[Embodiment 3 of the present invention] ]
Next, an embodiment of the present invention will be described. FIG. 3 is a diagram illustrating a system having a memory arbitration circuit according to the present embodiment. In the present embodiment shown in FIG. 3, the same components as those in the first embodiment shown in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted.

  As shown in FIG. 3, the system according to the present embodiment is the same as the first embodiment in that it includes bus masters A11, B12, and 13, a memory arbitration circuit 20, and a memory 30. However, the configuration of the memory arbitration circuit 20 is different. That is, the memory arbitration circuit 20 includes an access profile unit 23 and an access interrupt condition determination unit 24 in addition to the signal generation unit 21 and the priority order determination unit 22.

  The access profile unit 23 is an access monitoring unit that monitors the memory access amount of each bus master, and measures at least the access amount to the memory 30 of the bus master A11. Note that the access period to the memory 30 may be measured.

  The access interrupt condition determination unit 24 determines whether or not to permit a memory access interrupt request from the bus master A11 based on the monitoring result of the access profile unit 23. When the memory access amount of the bus master A11 exceeds a predetermined threshold, the access interrupt condition determination unit 24 enables the interrupt function and enables the interrupt access function for the memory 30 from the bus master A11. Here, the access interrupt condition determination unit 24 may have a plurality of threshold values, change the threshold values according to the situation, and determine whether or not to permit the memory access interrupt request.

  That is, when there is a first period and a second period in which access from the second bus master to the memory 30 is required more frequently than the first period, the access interrupt condition determination unit 24 The threshold value for the period may be set higher than the threshold value for the first period. That is, when access to the memory 30 of the bus master B11 is more frequent than in the first period as in the second period, the access to the memory 30 of the bus master A11 is suppressed.

  This second period corresponds to, for example, while the bus master B12 requests acquisition of image data, and the first period is after the bus master B12 acquires image data until it requests acquisition of the next image data. Corresponding between. Specifically, the first period can correspond to a blanking period, and the second period can correspond to an effective display period. Normally, memory access of the bus master B12 does not occur during the blanking period, so that the interrupt processing of the bus master A11 is permitted. On the other hand, during the valid display period, the bus master B12 needs to acquire image data. The access request from the bus master A11 is rejected above a certain level so that the bus master B12 can acquire necessary image data.

  Various threshold values can be set according to the nature of processing. For example, when the access amount of the bus master A11 exceeds the threshold A (when it is detected that the access frequency has increased), the access interrupt is enabled (ON condition), and the access amounts of the other bus masters B12 and 13 are the threshold B. (When it is detected that the amount of access is below the minimum access amount), the access interrupt of the bus master A11 can be disabled (OFF condition). Further, when the access amount of the bus master A11 exceeds the threshold C (when it is detected that the access frequency is too high), it is possible to invalidate the access interrupt (OFF condition).

  FIG. 4 is a flowchart showing the operation of the present embodiment. The same steps as those in the first embodiment shown in FIG. 2 are the same steps. As shown in FIG. 4, when an access request from the bus master A11 is generated during the access request processing of the bus master B12 (step S2: Yes), the access interrupt condition determination unit 24 is counted by the access profile unit 23. It is determined whether the access amount of the bus master A11 is within a certain threshold. When this access amount exceeds a certain threshold, the access interrupt function of the bus master A11 is validated. Therefore, when the access amount is greater than or equal to a certain threshold value, the interrupt of the bus master A11 is permitted (step S11: Yes). Other steps are the same as those in the first embodiment.

  Here, it is also possible to disable the interrupt function when the access amount of the other bus masters B12, 13 falls below a certain threshold value during a certain unit time. Furthermore, the interrupt function can be disabled when the access amount by the access interrupt of the bus master A11 exceeds a certain threshold. One or more of these may be used in combination.

  When the bus master B11 is an image display circuit, memory access is concentrated during the valid display period, and no access occurs during the blanking period (invalid display period). Therefore, the threshold value during the effective display period may be different from the threshold value during the blanking period. As a result, during the effective period, the threshold for access interrupt is increased to make it difficult to meet the access interrupt condition, and priority is given to access by the bus master B12 as the image display unit. On the other hand, during the blanking period, the threshold value is decreased so that the access interrupt condition is easily met. Thus, two types of threshold values corresponding to two types of periods can be set.

  In the present embodiment, the same effect as in the first embodiment is obtained, the access amount of the bus master A11 is measured by the access profile unit 23, and the interrupt function of the bus master A11 is enabled or disabled based on the measured access amount. It will be disabled. As a result, excessive interrupts of the bus master A11 can be prohibited, and when the frequency of use of the memory 30 of the bus master B12 is low, the interrupt of the bus master A11 is permitted and the latency of the bus master A11 is minimized. At the same time, access of the bus master B12 can be secured.

  It should be noted that the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present invention.

  For example, in the above-described embodiment, the hardware configuration has been described. However, the present invention is not limited to this, and arbitrary processing may be realized by causing a CPU (Central Processing Unit) to execute a computer program. Is possible. In this case, the computer program can be provided by being recorded on a recording medium, or can be provided by being transmitted via the Internet or another transmission medium.

11,111 Bus master A
12,112 Bus master B
13, 113 Bus master 20, 120 Memory arbitration circuit 21, 121 Signal generation unit 22, 122 Priority determination unit 23 Access profile unit 24 Access interrupt condition determination unit 30, 130 Memory

Claims (17)

A memory arbitration circuit that arbitrates access to the memory from the first and second bus masters,
A priority determination unit for determining the priority of the first and second bus masters;
A signal generation unit that receives memory access requests from the first and second bus masters and generates a control signal for memory access based on the priority;
Have
When the signal generator receives a memory access request from the first bus master during the memory access process of the second bus master, the signal generator temporarily stops the memory access process of the second bus master, and the first bus master Memory arbitration circuit that processes memory access requests. The memory includes a plurality of banks,
The memory arbitration circuit according to claim 1, wherein the signal generation unit uses one or more of the plurality of banks as a bank dedicated to the first bus master. An access monitoring unit for monitoring the memory access amount of each bus master;
An access interrupt condition determination unit that determines permission / refusal of a memory access interrupt request from the first bus master based on a monitoring result of the access monitoring unit;
The memory arbitration circuit according to claim 1, wherein the access interrupt condition determination unit permits a memory access from the first bus master when a memory access amount of the first bus master exceeds a predetermined threshold. .   The memory arbitration circuit according to claim 3, wherein the access interrupt condition determination unit has a plurality of thresholds, changes the thresholds according to a situation, and determines whether or not to permit a memory access interrupt request. A first period and a second period in which the second bus master needs to access the memory more frequently than the first period;
5. The memory arbitration circuit according to claim 3, wherein the access interrupt condition determination unit sets a threshold value of the second period higher than a threshold value of the first period.   The second period corresponds to the time when the second bus master requests acquisition of image data, and the first period requests the acquisition of the next image data after the second bus master acquires image data. The memory arbitration circuit according to claim 5, which corresponds to the period until   The memory arbitration circuit according to claim 5 or 6, wherein the first period corresponds to a blanking period, and the second period corresponds to an effective display period.   The signal generation unit temporarily stops the memory access request of the second bus master, and resumes the memory access request of the second bus master when processing of the memory access request of the first bus master is completed. 8. The memory arbitration circuit according to any one of 1 to 7.   9. The memory arbitration circuit according to claim 1, wherein the first bus master is a bus master that needs to make a memory access latency as short as possible. 10.   The memory arbitration circuit according to any one of claims 1 to 9, wherein the second bus master is a bus master that needs to increase bus bandwidth efficiency by burst access.   The memory arbitration circuit according to claim 1, wherein the first bus master is a CPU (Central Processing Unit).   The memory arbitration circuit according to claim 1, wherein the second bus master is an image display circuit.   The memory arbitration circuit according to claim 1, wherein the memory is an SDRAM (Synchronous Dynamic Random Access Memory). A memory arbitration method for arbitrating access to memory from first and second bus masters,
When the memory access request of the first bus master is received during the memory access process of the second bus master, the memory access process of the second bus master is temporarily stopped and the memory access request of the first bus master is processed. Memory arbitration method. The memory includes a plurality of banks,
The memory arbitration method according to claim 14, wherein one or more banks among the plurality of banks are dedicated to the first bus master. Monitor the memory access amount of each bus master,
16. The memory arbitration method according to claim 14, wherein when the memory access amount of the first bus master exceeds a predetermined threshold based on the monitoring result, memory access from the first bus master is permitted.   17. The memory access request of the second bus master is temporarily stopped, and when the processing of the memory access request of the first bus master is finished, the memory access request of the second bus master is resumed. The memory arbitration method according to claim 1.

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