475118 經濟部智慧財產局員工消費合作社印製 A7 B7五、發明説明（1 ) 本發明係關於，個人電腦，工作站，辦公室處理器等 資訊處理裝置所使用之位址/資料分離型資訊處理裝置用 匯流排系統。 在資訊處理裝置所使用之資訊處理裝置用匯流排系統 ，爲了要獲得更高之傳送能力，一直在設法擴大資料匯流 排之寬度，但匯流排寬度之擴大必然地會增加匯流排之信 號線數。因此，由於連接在匯流排之匯流排控制器，匯流 排介面單元等之積體電路之信號針腳數有限，一條匯流排 之資料匯流排寬度之擴大自有一定之限度。因此，在高性 能之資訊處理裝置則在進行，例如日本國特開平6 -5 1 9 1 0號公報所記載之匯流排之多工化，亦即平行方 式設置多條匯流排之方法。 上述傳統技術係在多數之匯流排連接裝置各配設多數 之匯流排單元，而使用平行設置之多條匯流排之空間之一 條。這個時候會產生，對同一位址存取有多條極流排上同 時進行時之處理等，因平行設置多條匯流排而引起之特別 處理。因此會產生，控制邏輯變複雜，傳送能力不能達到 期待值，可靠度降低，消耗電力增加，開發工數增加，控 制電路之價格上昇等問題。 同時要平行設置多條廣泛採用在處理器（C P U )等 之外部匯流排等之位址，資料分離型匯流排時，雖然有能 以個別之積體電路控制位址·匯流排與資料匯流排之優點， 但因位址匯流排與資料匯流排一樣平行設置多條，匯流排 系統之信號針腳數會大幅度增加，系統之價格會昇高。 ^紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐1 一 4 - (請先閲讀背面之注意事項再填寫本頁) 衣·475118 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (1) The present invention relates to an address / data separation type information processing device used for information processing devices such as personal computers, workstations, and office processors. Bus system. In order to obtain a higher transmission capacity, the bus system for information processing devices used in information processing devices has been trying to increase the width of the data bus. However, the expansion of the bus width will inevitably increase the number of signal lines of the bus. . Therefore, due to the limited number of signal pins of the integrated circuit connected to the bus controller, bus interface unit, etc., the data bus width of a bus has its own limit. Therefore, high-performance information processing devices are being carried out, such as the multiplexing of the busbars described in Japanese Patent Application Laid-Open No. 6-5109, that is, a method of setting a plurality of busbars in a parallel manner. The above-mentioned conventional technology is to configure a plurality of busbar units in each of the plurality of busbar connection devices, and use one of a plurality of busbar spaces arranged in parallel. At this time, there will be special processing caused by multiple buses being accessed at the same address when they are processed at the same time, due to the parallel installation of multiple buses. As a result, the control logic becomes complicated, the transmission capacity cannot reach the expected value, the reliability decreases, the power consumption increases, the number of development workers increases, and the price of the control circuit rises. At the same time, multiple external buses that are widely used in processors (CPUs) and other addresses must be set up in parallel. In the case of data-separated buses, although individual integrated circuits can control the address, the bus and the data bus Advantage, but because the address bus is set in parallel with the data bus, the number of signal pins of the bus system will increase significantly, and the price of the system will increase. ^ The paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm 1 to 4-(Please read the precautions on the back before filling this page).
、1T 475118 經濟部智慧財產局員工消費合作社印製 A7 B7五、發明説明（2 ) 本發明之目的在提供，平行設置多條匯流排控制邏輯 也不會變複雜，具有更高之傳送能力之匯流排控制方法， 及使用該方法之匯流排控制L S I ，以及使用該方法之匯 流排系統。 本發明之具體目的在提供，匯流排系統整體之信號針 腳數不多，但能有很高傳送能力之匯流排系統。 本發明之具體目的在提供，一方面可抑制信號針腳數 之增加，但仍可獲得很高之傳送能力之匯流排控制L S I 〇 本發明之具體目的在提供，一面可抑制其價格，但仍 可獲得很高之傳送能力之匯流排系統，或匯流排控制 LSI。 本發明之具體目的在提供，一面可抑制其消耗電力， 但仍可獲得很高之傳送能力之匯流排系統，或匯流排控制 LSI。 本發明之具體目的在提供，一方面可確保很高之可靠 度，同時可獲得很高之傳送能力之匯流排系統，或匯流排 控制L· S I 〇 本發明之具體目的在提供，開發工數很短，且可以獲 得很高之傳送能力之匯流排系統，或匯流排控制L S I 。 本發明係爲了達成上述目的，在位址，資料分離型匯 流排，設置1個系統之位址匯流排，及與該系統連繋之多 系統資料匯流排。並爲了位址匯流排與資料匯流排之連繫 ，配設在向位址匯流排輸出位址時，指定應使用之資料匯 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁) 衣· _ 5 — 475118 A7 B7 五、發明説明（3 ) 流排之手段。 (請先閲讀背面之注意事項再填寫本頁) 同時，本發明配設有，要求匯流排使用權時，由匯流 排連接裝置向仲裁器通知傳送資料長度之手段。並爲了位 址匯流排與資料匯流排之連繫，配設仲裁器向匯流排連接 裝置授與匯流排使用權時，指定應使用之資料匯流排之手 段。 同時，本發明係與同一時脈信號同步，控制上述一個 系統之位址匯流排與上述多系統之資料匯流排。 依據本發明時，在位址，資料分離型匯流排系統，因 爲設有一個系統之位址匯流排，及與該位址匯流排連繫之 多系統之資料匯流排，因此，雖然位址匯流排並未與寳料 匯流排同樣設有很多系統，仍能獲得與平行設置多條位址 、資料分離型匯流排時同樣之傳送能力。藉此，匯流排系 統整體之信號針腳之增加不多。 經濟部智慧財產局員工消費合作社印製 而位址匯流排與多數之資料匯流排之連繫，可藉，在 位址、資料分離型匯流排採用與位址、資料多工型匯流排 同樣之以流水線（pipe-line)式輸出位址與資料之分割 傳送協定，同時在向位址匯流排輸出位址時，指定所使用 之資料匯流排，便可以實現。藉此，設置多系統資料匯流 排時，位址匯流排仍是一個系統，因此不需要有同時存取 同一位址時之處理等之特別處理。 同時，本發明係採用要求匯流排使用權時由匯流排連 接裝置向仲裁器通知傳送資料長度之方法，作爲匯流排之 裁決（arbitration)方法，並在仲裁器向匯流排連接裝 ^紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐1 — -6 — 475118 A7 ___B7 __ 五、發明説明（4 ) 置授與匯流排使用權時，指定所使用之資料匯流排。 (請先閲讀背面之注意事項再填寫本頁) 同時，藉此可由仲裁器一面管理傳送資料長度等多系 統之資料匯流排之使用程序，同時進行裁決，因此可以很 容易實現一個系統之位址匯流排與多系統之資料匯流排之 連繋。 同時，本發明係使位址匯流排與多數之資料匯流排與 同一之時脈脈衝信號同步而加以控制，因此，使用將閱讀 傳送分割成請求時及回應時之兩次進行之分割傳送協定， 或在分割傳送協定將閱讀傳送之請求之回應之間隔固定在 一定時間之時槽傳送協定，作爲閱讀傳送之協定，即可很 容易使位址匯流排與多數之資料匯流排連繫。 尤其是分割傳送協送，如果將仲裁器設在如主記憶控 制部之不含匯流排主控裝置之匯流排連接裝置內，則可將 回應時之裁決變成主記憶控制部之內部處理，而得削減信 號線數。 經濟部智慧財產局員工消費合作社印製 同時使位址匯流排與多數之資料匯流排與同一時脈信 號同步加以控制，藉此可在多數之資料匯流排中，檢出有 一部分故障時，不使用檢出故障之資料匯流排，僅使用正 常之資料匯流排而動作，而實現縮退機能。 依據本發明時，則不需要複雜之控制邏輯，而獲得具 有很高之傳送能力之匯流排系統。藉此，可一面保持很高 之傳送能力，同時可抑制匯流排系統整體及匯流排控制 L S I之信號針腳數之增加，並抑制消耗電力，價格，開 發工數。 一 7 - 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 475118 A7 _____ B7 ___ 五、發明説明（5 ) 茲參照第1圖至第8圖以及表1 ，說明本發明之實施 例如下。表1條第1圖之匯流排之信號架構之例子之信號 線一覽表。 (請先閲讀背面之注意事項再填寫本頁) 在第1圖所示實施例之系統匯流排設有一個系統之位 址/控制匯流排，及兩系統之資料匯流排。在第1圖， 1 0係本發明之系統匯流排，1 1係系統匯流排1 0中之 一個系統之位址/控制匯流排（A D R / C N T L )， 1 2及1 3係系統匯流排1 0中之兩系統之資料匯流排（ L — D A T A及R — D A T A ) ，1 4係連接在系統匯流 排10之多數之處理器元件（PE) ，15係連接在系統 匯流排1 0之主記憶控制部，1 6係主記憶器，1 7係連 接在系統匯流排1 0之I / 0匯流排控制部，1 8係 I / 0匯流排。P E 1 4，主記憶控制部1 5，I /〇匯 流排控制部1 7稱作匯流排連接裝置。9 1係從各匯流排 連接裝置個別連接到主記憶控制部內之仲裁器之匯流排請 求線（後述之表1之RQ (*)<3_0>) ，92係從 經濟部智慧財產局員工消費合作社印製 仲裁器個別連接到各匯流排連接裝置之匯流排權許可線（ 後述之表1之GRT(*)<3 — 0>) ，93係以匯流 排連接在各匯流排連接裝置，指示所使用之資料匯流排之 信號（後述之表1之LDSEL#)。 在此，P E 1 4與I / 0匯流排控制部1 7含有匯流 排主控裝置，但主記憶控制部1 5則不含匯流排主控裝置 〇 第1圖係PE14各含有多數之CPU之多處理器系 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 297公釐） -8 - 475118 A7 B7 五、發明説明（6 ) (請先閱讀背面之注意事項再填寫本頁) 統’系統架構則除了系統匯流排1 〇以外，可以與上述並 排設置多條匯流排之傳統技術一樣。採用具有多數之主記 憶控制部或I / ◦匯流排控制部之系統架構，或主記憶控 制部與I / 〇匯流排控制部一體化之系統架構時，也可以 應用本發明。本實施例之系統匯流排1 〇之仲裁器係設置 在主記憶控制部1 5內。 其次，第2圖表示P E 1 4之內部架構之一個例子。 在第2圖中，20係多數之CPU，21係CPU 20 之外部匯流排中之位址/控制匯流排（A / C ) ，2 2係 C Ρ ϋ 2 0之外部匯流排中之資料匯流排（D ) ，2 3係 經濟部智慧財產局員工消費合作社印製 連接在系統匯流排1 0之匯流排介面控制器中之位址/控 制匯流排連接用L S I ，2 4及2 5係連接在系統匯流排 介面控制器中之資料匯流排連接用LS I ，26及27係 連接在系統匯流排介面控制器中之L S I間控制信號。一 個位址/控制匯流排連接用L S I 2 3，與兩個資料匯 流排連接用LSI 24及25，係構成連接在PE14 中之系統匯流排1 0之匯流排介面控制器之L S I ，該等 總稱爲匯流排控制用L S I 。 第2圖係以位址、資料分離型之外部匯流排連接多數 之之CPU 20，CPU 20分別在內部設有高速緩 衝記憶體。位址/控制匯流排連接用L S I 2 3連接在 CPU 2 0之外部匯流排中之位址/控制匯流排2 1及 系統匯流排1 0中之ADR/CNTL 11 ，資料匯流 排連接用LSI 24及25則連接在CPU 20之外 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 297公釐） 475118 經濟部智慧財產局員工消費合作社印製 A7 _ B7五、發明説明（7 ) 部匯流排中之資料匯流排2 2，系統滙流排1 0中之兩系 統之資料匯流排L—DATA 12及R—DATA 13之一方。資料匯流排連接用LS I 24及2 5係由 位址/控制匯流排連接用L S I 2 3之控制信號2 6及 2 7加以控制。 連接在系統匯流排1 0之匯流排介面控制器在主記憶 控制部1 5及I / 〇匯流排控制部1 7，亦由同樣之 L S I架構實現之。 第3圖表示P E 1 4之內部結構之其他例子。第3 圖係在第2圖之架構追加處理器元件內共有高速緩衝記憶 體（PE cache) °PE cache 30 係定 位在C P U 2 0內所設之高速緩衝記億體與主記億器之 中間階層，而由位址/控制匯流排連接用L S I 2 3引 出之位址/控制線3 1，及從資料匯流排連接用L S I 2 4及2 5引出之資料線3 2及3 3，連接在匯流排介面 控制器。 本發明之匯流排1 0之信號架構之例子示於表1。表 1係從左往右分別表示，信號名稱，信號線數，信號之意 義。在表1內之信號名稱，其末尾之#記號表示負極性， 而（* )則表示係裁決用之個別連接控制線。以下就各信 號分別說明之。 (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 一 10 - 475118 A7 B7 五、發明説明（8 ) 表1 經濟部智慧財產局員工消費合作社印製1T 475118 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (2) The purpose of the present invention is to provide that multiple bus control logics installed in parallel will not become complicated and have higher transmission capabilities. Bus control method, bus control LSI using the method, and bus system using the method. A specific object of the present invention is to provide a bus system having a small number of signal pins as a whole but having a high transmission capacity. A specific object of the present invention is to provide a bus control LSI that can suppress an increase in the number of signal pins, but still obtain a high transmission capacity. The specific object of the present invention is to provide, while suppressing its price, it can still A bus system or a bus control LSI that achieves high transmission capabilities. A specific object of the present invention is to provide a bus system or a bus control LSI that can suppress its power consumption, but still obtain a high transmission capacity. The specific purpose of the present invention is to provide a bus system, or a bus control L · SI, which can ensure a high degree of reliability and obtain a high transmission capacity on the one hand. The specific purpose of the present invention is to provide, develop labor Very short and bus system or bus control LSI that can get very high transmission capacity. In order to achieve the above-mentioned object, the present invention provides an address bus with one system at the address and data separation type bus, and a plurality of system data buses connected to the system. In order to link the address bus with the data bus, the data size specified for the data collection to be used when outputting addresses to the address bus is specified by the Chinese National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before filling out this page) Clothing _ 5 — 475118 A7 B7 V. Description of Invention (3) Means of Streaming. (Please read the notes on the back before filling this page) At the same time, the present invention is equipped with a means for the bus connection device to notify the arbiter of the length of the data when the bus connection right is requested. In order to connect the address bus with the data bus, an arbiter is provided to assign the bus connection device to the bus connection device to specify the method of the data bus to be used. At the same time, the present invention synchronizes with the same clock signal to control the address bus of one system and the data bus of multiple systems. According to the present invention, the address and data separation type bus system is provided with a system address bus and data buses of multiple systems connected to the address bus. Therefore, although the address bus The bus does not have many systems like the treasure bus, and can still obtain the same transmission capacity as when multiple addresses and data-separated buses are set in parallel. As a result, the signal pins of the bus system as a whole have not increased much. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, the address bus and the majority of data buses can be borrowed. The address and data separation buses are the same as the address and data multiplex buses. A pipeline-line output address and data split transmission protocol, and at the same time when outputting an address to an address bus, specify the data bus to be used can be achieved. Therefore, when setting up a multi-system data bus, the address bus is still a system, so there is no need for special processing such as processing when accessing the same address at the same time. At the same time, the present invention adopts a method in which the bus connection device notifies the arbiter of the length of the data transmitted when the right to use the bus is required. China National Standard (CNS) A4 specification (210X297 mm 1 — -6 — 475118 A7 ___B7 __ 5. Explanation of the invention (4) When granting and using the right to use the bus, specify the data bus used. (Please read the back first Please also fill out this page) At the same time, the arbiter can manage the use of multi-system data buses such as data length and make decisions at the same time, so it is easy to implement one system's address bus and multi-system At the same time, the present invention synchronizes and controls the address bus and the majority of the data buses with the same clock pulse signal. Therefore, the reading transmission is divided into two parts: request time and response time. Split transmission protocol, or when the interval of the response to the request to read the transmission is fixed at the time of the split transmission protocol The time slot transmission protocol, as a protocol for reading transmission, can easily link the address bus with most data buses. Especially for the split transmission protocol, if the arbiter is set in the main memory control unit, In the bus connection device that does not include the bus master control device, the ruling at the time of response can be turned into the internal processing of the main memory control department, so that the number of signal lines can be reduced. The address bus and the majority of the data buses are controlled in synchronization with the same clock signal, so that when a part of the majority of the data buses is detected, the faulty data bus is not used, and only the normal data bus is used. The data bus operates and realizes the shrinking function. According to the present invention, a complex control logic is not required, and a bus system with a high transmission capacity is obtained. Thus, while maintaining a high transmission capacity, at the same time, It can suppress the increase of the number of signal pins of the bus system as a whole and the bus control LSI, and suppress the power consumption, price, and development work. 7-This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 475118 A7 _____ B7 ___ 5. Description of the invention (5) The following describes the implementation examples of the present invention with reference to Figures 1 to 8 and Table 1. Below. Table 1 The signal line list of the example of the signal structure of the bus in Figure 1. (Please read the precautions on the back before filling this page.) There is a system in the system bus of the embodiment shown in Figure 1. Address / control bus of the two systems. In FIG. 1, 10 is the system bus of the present invention, and 11 is the system address / control bus of one of the 10 systems. (ADR / CNTL), 1 2 and 1 3 are the data buses (L — DATA and R — DATA) of two of the 10 system buses, and 1 4 are the processor elements connected to the majority of the system bus 10 (PE), 15 series connected to the main memory control section of the system bus 10, 16 series main memory, 17 connected to the system bus 10 I / 0 bus control section, 18 series I / 0 bus. P E 1 4, the main memory control unit 15, and the I / 〇 bus control unit 17 are called bus connection devices. 9 1 is the bus request line (RQ (*) < 3_0 > in Table 1 described later) that is individually connected from each bus connection device to the arbiter in the main memory control department, 92 is consumed by employees of the Intellectual Property Bureau of the Ministry of Economic Affairs The cooperative prints the arbiter individually connected to the bus line permission line of each bus connection device (GRT (*) < 3 — 0 > in Table 1 described later), 93 is connected to each bus connection device by bus, Signal indicating the data bus used (LDSEL # in Table 1 described later). Here, the PE 14 and I / 0 bus control sections 17 contain the bus master control device, but the main memory control section 15 does not include the bus master control device. Figure 1 shows that each of PE14 contains a majority of CPUs. Multi-processor system This paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 mm) -8-475118 A7 B7 V. Description of invention (6) (Please read the precautions on the back before filling this page) 'In addition to the system bus 10, the system architecture can be the same as the above-mentioned traditional technology of setting multiple buses side by side. The present invention can also be applied when a system architecture having a majority of the main memory control unit or the I / o bus control unit or a system architecture in which the main memory control unit and the I / 0 bus control unit are integrated. The arbiter of the system bus 10 in this embodiment is provided in the main memory control section 15. Next, Figure 2 shows an example of the internal structure of P E 1 4. In Figure 2, 20 is the majority of the CPU, 21 is the address / control bus (A / C) in the external bus of CPU 20, and 2 is the data bus in the external bus of C PF 0 20 Row (D), 2 and 3 are printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, which are connected to the bus interface controller of the system bus 10, and the control bus is connected with LSI. The data bus connection in the system bus interface controller uses LS I, 26 and 27 are the inter-LSI control signals connected to the system bus interface controller. One address / control bus connection LSI 23, and two data bus connection LSIs 24 and 25 are LSIs constituting the bus interface controller of the system bus 10 connected to PE14. It is an LSI for bus control. Fig. 2 shows that most of the CPUs 20 are connected by external buses of address and data separation type. The CPUs 20 are respectively provided with high-speed buffer memory. Address / control bus connection LSI 2 3 Address / control bus 2 1 connected to external bus of CPU 2 0 and ADR / CNTL 11 of system bus 10 and data bus connection LSI 24 And 25 are connected outside the CPU 20. This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 475118 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 _ B7 V. Invention Description (7) Department One of the two data buses L-DATA 12 and R-DATA 13 of the two systems of the data bus 22 and the system bus 10. The data bus connection LS I 24 and 25 are controlled by the control signals 26 and 27 of the address / control bus connection L S I 2 3. The bus interface controller connected to the system bus 10 in the main memory control section 15 and the I / 〇 bus control section 17 are also implemented by the same L S I architecture. Fig. 3 shows another example of the internal structure of P E 1 4. Figure 3 shows the common cache memory (PE cache) in the additional processor elements in the architecture shown in Figure 2. ° PE cache 30 is positioned between the cache memory and the master memory in the CPU 20 Level, and the address / control line 3 1 from the address / control bus connection LSI 2 3 and the data lines 3 2 and 3 3 from the data bus connection LSI 2 4 and 25 are connected to Bus interface controller. An example of the signal architecture of the bus 10 of the present invention is shown in Table 1. Table 1 shows the signal names, signal line numbers, and signal meanings from left to right. For the signal names in Table 1, the # symbol at the end indicates negative polarity, and (*) indicates that it is an individual connection control line for adjudication. Each signal is explained below. (Please read the precautions on the back before filling this page) This paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm)-10-475118 A7 B7 V. Description of invention (8) Table 1 Intellectual Property Bureau, Ministry of Economic Affairs Printed by Employee Consumer Cooperative
信號名稱 信號線數 信號之意義 LD<6 3 — 00> 6 4 L-DATA資料 L D E <7 - 0 > 8 L-DATAECC RD<63-00> 6 4 R-DATA資料 RDE<7-0> 8 R-DATAECC AS# 1 位址選通脈衝 A < 3 1 - 0 3 > 2 9 位址 A P < 1 - 0 > 2 位址同位 C<28 — 00> 2 9 指令 C P < 1 - 0 > 2 指令同位 R S P < 7 - 0 > 8 回應碼 R Q (木）<3 -> 4 匯流排權請求 G R 丁（氺）# 1 匯流排權許可 L D S E T # 1 使用資料匯流排指示 C L K 1 匯流排時脈信號 P 0 N R S T # 1 接通電源重置 B U S R S T # 1 匯流排重置 1 d<2 — 0>(*) 3 模組ID (請先閲讀背面之注意事項再填寫本頁) 衣· 訂 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -11 - 475118 A7 B7 五、發明説明（9 ) (請先閲讀背面之注意事項再填寫本頁) 表1之系統匯流排1 0係時脈同步式，c L K係匯流 排時脈信號，供給連接在系統匯流排1 〇之所有L s 1 。 LD<6 3 — 0 0>及RD<6 3 — 0〇>係各系統匯流 排1 0中之兩系統之資料匯流排L — DATA 1 2及R — D A T A 1 3之資料，有8個位元組，即6 4個位元之寬 度。1/〇丑<7-0>及11〇^<7-0>係分別附加在 LD<6 3 — 0 0>及RD<6 3-0 〇>之錯誤檢查碼 (ECC)，分別含在資料匯流排L—DATA 12及 R - D A T A 1 3 0 RQ(*)<3-0>係各匯流排連接裝置個別對仲 裁器輸出之4位元之匯流排使用權請求信號。該4位元含 有當作資訊之傳送資料長度。G R T ( * )#係由各仲裁 器個別輸入各匯流排連接裝置之匯流排使用權許可信號’ L D S E L #係與匯流排使用權許可信號同時由仲裁器輸 出之使用資料匯流排指示信號。 經濟部智慧財產局員工消費合作社印製 其他信號則全部含在系統匯流排1 0中之A D R / CNTL 1 1。AS# 係位址選通脈衝（Adressstrobe )信號，表示在ADR/CNTL 1 1上輸出有位址及 指令。 八<3 1-03>及（：<28-00>分別係2 9位 元之位址信號及指令信號。指令信號中含有表示使用兩系 統之資料匯流排之任一方之信號。其他之指令信號及位址 信號與上述傳統技術之匯流排一樣。A P <1 - 0 >及 CP<1-0>係分別附加在A<31-03>及。< 本紙張尺度適用中國國家標準（CNS ) A4規格（210><297公釐） 一 12 _ 475118 A7 B7 五、發明説明（10 ) (請先閲讀背面之注意事項再填寫本頁) 2 8 _ 0 0 >之同位信號，分別含在位址信號及指令信號 。尺3卩<7-0>係8位元之回應碼信號，表示各匯流 排連接裝置對上述位址信號及指令信號之回應（正常受理 位址信號及指令信號，檢出錯誤，或再試請求等）之信號 。本實施例係由位址/匯流排控制用L S I 2 3輸出。 PONRST#及BUSRST#分別爲電源接通（ power on).重置信號及匯流排重置信號，與上述傳統技術 之匯流排之重置信號一樣。I D < 2 — 0 >( * )係對連 接到系統匯流排1 0之各模組給以個別之模組號碼之固定 值之I D信號。 同時，表1之P E最大數爲4個，將主記憶控制部 1 5與I / 〇控制部1 7 —體化成爲1個模組。 其次再使用這些圖與第4圖，說明本發明之匯流排控 制之例子。第4圖係說明分割傳送協定之例子。第4圖表 示有3個匯流排連接裝置（0)〜（2)之匯流排使用權 請求信號RQ (0)〜RQ (2)，與匯流排使用權許可 信號GRT(〇) #〜GRT(2) #。再者，（ ）內 經濟部智慧財產局員工消費合作社印製 係裝置號碼，但匯流排連接裝置（0 )〜（2 )爲第1圖 所示之PE 1 4，I/O匯流排控制部1 7之任一方均 可。再說明第4圖之定時圖之內容如下。 在循環T 1 ，係由P E 1 4或I / 〇匯流排控制部 17等之匯流排連接裝置（0)及（1)使用RQ (0) ，R Q ( 1 )輸出匯流排使用權請求信號（1 〇 1及 2 0 1 )。這是由該匯流排連接裝置中之位址/控制匯流 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -13 - 475118 A7 B7 五、發明説明（11 ) (請先閲讀背面之注意事項再填寫本頁) 排連接用LSI 23輸出。101係閱讀請求或 c a c h e無效化請求等之僅傳送位址之傳送請求，在此 係當作主記憶控制部1 5內之資料之閱讀請求。2 0 1係 伴隨著4循環之資料傳送之寫入傳送請求。主記憶控制部 1 5內之仲裁器在T 1取進這些資訊。仲裁器則進行裁決 ，使用GRT (〇) #在T3向匯流排連接裝置（0)授 與匯流排使用權，並使用GRT ( 1 ) #在T4向匯流排 連接裝置（1)授與匯流排使用權（10 2及202)。 在T 4，由仲裁器對匯流排連接裝置（1 )授與匯流 排使用權，同時藉輸出LDSEL#信號，指示（203 )使用L D當作資料匯流排。 在T 5，匯流排連接裝置（0 )中之位址/控制匯流 排連接用L S I 2 3則連同位址選通脈衝信號AS# — 併，輸出（104)對GRT (〇) # (102)之位址 及指令A，C 〇 經濟部智慧財產局員工消費合作社印製 在T7，由匯流排連接裝置（0 )指定之匯流排連接 裝置（在此爲主記億控制部15 )輸出（1 0 6 )對T5 之位址及指令A，C ( 1 04)之回應碼RSP。Signal name Signal line number Signal meaning LD < 6 3 — 00 > 6 4 L-DATA data LDE < 7-0 > 8 L-DATAECC RD < 63-00 > 6 4 R-DATA data RDE < 7-0 > 8 R-DATAECC AS # 1 address strobe A < 3 1-0 3 > 2 9 address AP < 1-0 > 2 address parity C < 28 — 00 > 2 9 instruction CP < 1-0 > 2 command parity RSP < 7-0 > 8 response code RQ (wood) < 3-> 4 bus flow request GR ding (氺) # 1 bus flow permission LDSET # 1 use Data bus indication CLK 1 Bus clock signal P 0 NRST # 1 Power on reset BUSRST # 1 Bus reset 1 d < 2 — 0 > (*) 3 Module ID (Please read the precautions on the back first (Fill in this page again.) The size of the clothes and the paper are in accordance with the Chinese National Standard (CNS) A4 (210X297 mm) -11-475118 A7 B7. 5. Description of the invention (9) (Please read the precautions on the back before filling this page. ) The system bus 10 of Table 1 is a clock synchronization type, and c LK is a clock signal of the bus, which supplies all L s 1 connected to the system bus 1 〇LD < 6 3 — 0 0 > and RD < 6 3 — 0〇 > are the data buses of two systems of each system bus 10, L — DATA 1 2 and R — DATA 1 3, there are 8 Bytes, which is a width of 64 bits. 1 / 〇ugly < 7-0 > and 11〇 ^ < 7-0 > are error check codes (ECC) appended to LD < 6 3-0 0 > and RD < 6 3-0 〇 >, respectively, The data bus L-DATA 12 and R-DATA 1 3 0 RQ (*) < 3-0 > are the 4-bit bus use right request signals output by the bus connection device to the arbiter. The 4 bits contain the length of the transmitted data as information. G R T (*) # is the bus usage right permission signal input by each arbiter to each bus connection device ′ L D S E L # is the usage data bus indication signal output by the arbiter at the same time as the bus usage right permission signal. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs and other signals are all included in the system bus 10 A D R / CNTL 1 1. AS # is an address strobe (Adressstrobe) signal, which indicates that an address and a command are output on ADR / CNTL 1 1. Eight < 3 1-03 > and (: < 28-00 > are respectively a 29-bit address signal and a command signal. The command signal includes a signal indicating the use of either of the two data buses. Others The command signal and address signal are the same as those of the conventional technology bus. AP < 1-0 > and CP < 1-0 > are attached to A < 31-03 > and respectively. ≪ This paper size is applicable to China National Standard (CNS) A4 Specification (210 > < 297 mm)-12 _ 475118 A7 B7 V. Description of Invention (10) (Please read the notes on the back before filling this page) 2 8 _ 0 0 > of The parity signals are included in the address signal and the command signal. Rule 3 尺 < 7-0 > is an 8-bit response code signal, which indicates that each bus connection device responds to the above address signal and command signal (normal acceptance Address signal and instruction signal, error detection, retry request, etc.). This embodiment is output by the address / bus control LSI 2 3. PONRST # and BUSRST # are power on respectively. .Reset signal and bus reset signal The reset signal is the same. ID < 2 — 0 > (*) is an ID signal with a fixed value for each module number for each module connected to the system bus 10. At the same time, the PE of Table 1 is the largest The number is four, and the main memory control unit 15 and the I / 〇 control unit 17 are integrated into one module. Next, these figures and FIG. 4 are used to explain an example of the bus control of the present invention. Fig. 4 illustrates an example of a split transmission protocol. Fig. 4 illustrates a bus use right request signal RQ (0) to RQ (2) with three bus connection devices (0) to (2), and a bus use right License signal GRT (〇) # ~ GRT (2) #. Furthermore, () The number of the printing device of the consumer cooperative of the employee of the Intellectual Property Bureau of the Ministry of Economic Affairs (), but the bus connection device (0) ~ (2) is shown in Figure 1. Either PE 1 4 or I / O bus control unit 17 shown is acceptable. The content of the timing diagram in Fig. 4 is as follows. In cycle T 1, it is PE 1 4 or I / 〇 bus. The bus connection devices (0) and (1) of the control unit 17 etc. use RQ (0), and RQ (1) outputs the bus use right request signals (101 and 2 0 1). This is The address / control bus in the bus connection device is based on the Chinese paper standard (CNS) A4 (210X297 mm) -13-475118 A7 B7 V. Description of the invention (11) (Please read the note on the back first Please fill in this page again.) LSI 23 output for connection. 101 is a read-only address transfer request such as a read request or a c a c h e invalidation request, and is here a read request for data in the main memory control section 15. 2 0 1 is a write transfer request accompanied by 4 cycles of data transfer. The arbiter in the main memory control section 15 fetches this information at T1. The arbiter makes a ruling, using GRT (〇) # to grant the bus connection right to the bus connection device (0) at T3, and GRT (1) # to the bus connection device (1) at T4. Right of use (10 2 and 202). At T4, the arbiter grants the bus connection device (1) the right to use the bus, and at the same time borrows the output LDSEL # signal to instruct (203) to use L D as the data bus. At T 5, the address / control bus connection LSI in the bus connection device (0) 2 3 together with the address strobe signal AS # — and outputs (104) to GRT (〇) # (102) The address and instructions A, C 〇 The employee's consumer cooperative of the Intellectual Property Bureau of the Ministry of Economy is printed on T7, and the bus connection device designated by the bus connection device (0) (here is the main record control unit 15) output (1 0 6) The response code RSP to the address of T5 and the instructions A and C (1 04).
接受 T4 之 GRT (1) # (202) ，LDSEL #( 2 0 3 )後，匯流排連接裝置（1 )中之位址/控制 匯流排連接用L S I 2 3，在T 6連同位址選通脈衝信 號AS# —併輸出（204)位址及指令A，C，而資料 匯流排連接用L S I 2 4則藉位址/控制匯流排連接用 LSI 23之控制，從T8在LD上輸出（2 05) 4 本紙張尺度適用中國國家標準（CNS ) A4規格（210父297公釐1 ' -14 - 475118 A7 B7 五、發明説明（12 ) 循環之資料。這時表示，以T 6之指令輸出（204)， 可使用LD作爲資料匯流排。 由匯流排連接裝置（1 )通知寫入資料之匯流排連接 裝置在T8輸出（206)，對T6之位址及指令A，C 輸出（204)之回應碼RSP。 其次在T3及T4，各個匯流排連接裝置（2)及（ 0)使用 GQ(2) ，RQ(〇)輸出（301 及 401 )輸出匯流排使用權請求信號。3 0 1條件隨有4循環之 資料傳送之寫入傳送請求，4 0 1係僅位址之傳送請求。 仲裁器便進行裁決，使用GRT (2) #，在T5向匯流 排連接裝置（2)授與匯流排使用權，並使用GRT (〇 )#，在T6向匯流排連接裝置（0)授與匯流排使用權 (3 0 2 及 4 0 2 )。 在T5，仲裁器對匯流排連接裝置（2)授與匯流排 使用權之同時，藉不輸出LD S E L #信號指示使用RD 當作資料匯流排。 在T 7，匯流排連接裝置（2 )中之位址/控制匯流 排連接用L S I 2 3與位址選通脈衝信號A S # —併， 輸出（304)對GRT (2) # (302 )之位址及指 令 A，C 〇 在T9，匯流排連接裝置（2 )中之資料匯流排連接 用L S I 2 5藉位址/控制匯流排連接用L S I 23 之控制，從T9在RD上輸出（305) 4循環之資料。 這時以T7之指令輸出（304)表示可使用RD作爲資 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁) 衣·After accepting the GRT (1) # (202) and LDSEL # (2 0 3) of T4, the address / control bus connection LSI 2 3 in the bus connection device (1) is gated at T 6 with the address Pulse signal AS # — and output (204) address and instructions A, C, and the data bus connection LSI 2 4 is controlled by the address / control bus connection LSI 23, and is output from T8 on the LD (2 05) 4 This paper size applies the Chinese National Standard (CNS) A4 specification (210 father 297 mm 1 '-14-475118 A7 B7 V. Description of the invention (12) Circulation data. At this time, it is indicated by the T 6 instruction output ( 204), LD can be used as the data bus. The bus connection device (1) informs the bus connection device that writes data to output at T8 (206), to the address of T6 and instructions A, C output (204). Response code RSP. Secondly at T3 and T4, each bus connection device (2) and (0) uses GQ (2), and RQ (〇) outputs (301 and 401) to output the bus use right request signal. 3 0 1 condition With 4 cycles of data transfer write transfer request, 401 is an address-only transfer request. The arbiter then decides and uses GRT (2 ) #, Grant bus usage rights to the bus connection device (2) at T5, and use GRT (〇) # to grant bus usage rights to the bus connection device (0) at T6 (3 0 2 and 4) 0 2). At T5, the arbiter grants the right to use the bus connection device (2), and does not output the LD SEL # signal to indicate the use of RD as the data bus. At T 7, the bus connection device (2) The LSI 23 for address / control bus connection is connected to the address strobe signal AS # and outputs the address (304) to the GRT (2) # (302) and the instructions A and C. In T9, the data bus connection device LSI 2 in the bus connection device (2) is controlled by the address / control bus connection LSI 23, and T305 outputs (305) 4 cycles of data on the RD. T7's instruction output (304) indicates that RD can be used as the capital paper size. Applicable to China National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before filling this page).
、1T 經濟部智慧財產局員工消費合作社印製 -15 - 475118 A7 ___ B7 _ 五、發明説明（13 ) 料匯流排。 (請先閱讀背面之注意事項再填寫本頁) 由匯流排連接裝置（2 )通知通入資料之匯流排連接 裝置在T9輸出（ 306)，對T7之位址及指令A，C 輸出（304)之回應碼RSP。 而匯流排連接裝置（0)則接受GRT (〇) # ( 402)，在T8連同位址選通脈衝信號AS#—起輸出 (4 0 4 )位址及指令A，C，而從匯流排連接裝置（〇 )傳送位址之匯流排連接裝置則在T 1 〇輸出（4 0 6 ) 對該位址及指令A，C之回應碼RSP。 經濟部智慧財產局員工消費合作社印製 本實施例因仲裁器含在主記憶控制部1 5內，因此， 主記憶控制部1 5雖是匯流排連接裝置，但不向外部輸出 匯流排權請求及許可信號，主記憶控制部1 5之傳送請求 係在仲裁器之內部處理。因此，雖未圖示，主記憶控制部 1 5將對T 5之位址及指令A，C與位址選通脈衝信號信 號AS# (1〇4)之閱讀請求回應，在T6請求4循環 之資料傳送。仲裁器則在內部處理之結果，於T 8對主記 憶控制部1 5授與匯流排使用權，與匯流排使用權一併輸 出LDSEL#信號，指示（5 0 3 )可使用LD當作資 料匯流排。這時仲裁器在進行兩系統之資料匯流排之程序 管理。在ΤΙ 1以前使用（205及305) LD，RD 之雙方之資料匯流排，因此在內部處理時原來在T 7時可 向主記憶控制部1 5授與使用權，但等候到T 8，而從 T 1 2起由主記憶控制部1 5進行資料傳送。 主記憶控制部1 5在控制已授與匯流排使用權後，在 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -16 - 475118 A7 B7 _ 五、發明説明（14 ) T 1 0與位址選通脈衝信號A s # —併輸出（5 0 4 )位 址及指令A，C，並從T12在LD上輸出（505) 4 循環之資料。但這時也可以沒有位址輸出。這個時候 T 1 0之指令輸出（5 0 4 )表示使用L D作爲資料匯流 排。對主記憶控制部1 5在T 5進行閱讀請求（1 0 4 ) 之匯流排連接裝置（〇)，在T12輸出（506)對指 令輸出（504)之回應碼RSP。 這時若是時槽傳送協定，使用之資料匯流排係由T 5 之閱讀請求（1 04)指定，因此位址及指令A，C與位 址選通脈衝信號AS# (504)均不需要。 再假設’在T 8，匯流排連接裝置（0 ) ，（ 1 )及 (2)在輸出（901 ，601及801)匯流排使用權 請求信號，回應T 8之位址及指令A，C與位址選通脈衝 信號A S # ( 4 0 4 )，在T 9，主記憶控制部1 5請求 4循環之資料傳送。9 0 1係僅位址之傳送請求，8 0 1 係4循環之資料傳送請求，6 0 1係1循環之資料傳送請 求。仲裁器則進行裁決，在T10使用GRT(1)#對 匯流排連接裝置（1) ( 602)，在T11對主記憶控 制部1 5 (未圖示）授與匯流排使用權，使用GRT ( 2 )#於T12向匯流排連接裝置（2) (802)授與匯 流排使用權，使用G R T ( 〇 ) #，於T 1 3向匯流排連 接裝置（0 ) ( 9 02)授與匯流排使用權。 在T 1 〇，由仲裁器向匯流排連接裝置（1 )指示匯 流排使用權，同時藉不輸出LDSEL#信號指示使用 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁) •靡衣·Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs -15-475118 A7 ___ B7 _ V. Description of the invention (13) Material bus. (Please read the precautions on the back before filling this page) The bus connection device (2) informs the bus connection device of the access data to output at T9 (306), the address of T7 and the instructions A and C output (304 ) Response code RSP. The bus connection device (0) accepts GRT (〇) # (402), and outputs (4 0 4) address and command A and C from T8 together with the address strobe signal AS #. The connecting device (0) transmits the bus of the address. The connecting device outputs (406) the response code RSP to the address and the instructions A and C at T 1 0. Printed in this embodiment by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. The arbiter is included in the main memory control unit 15. Therefore, although the main memory control unit 15 is a bus connection device, it does not output a bus request to the outside. And permission signals, the transfer requests of the main memory control unit 15 are processed internally by the arbiter. Therefore, although not shown, the main memory control unit 15 will respond to the reading request of the address and instruction A, C and address strobe signal signal AS # (104) of T 5 and request 4 cycles at T6. Data transfer. The arbiter internally processes the result and grants the bus memory use right to the main memory control unit 15 at T 8 and outputs the LDSEL # signal together with the bus use right to indicate (5 0 3) that LD can be used as data Bus. At this time, the arbiter is performing the process management of the data bus of the two systems. Before Ti 1 (205 and 305), the data buses of both LD and RD were used. Therefore, during the internal processing, the master memory control unit 15 could be granted the right to use at T 7 but waited until T 8 and From T 1 2, data is transferred by the main memory control unit 15. The master memory control unit 15 applies the Chinese National Standard (CNS) A4 specification (210X297 mm) to this paper standard after controlling the use of the bus. -16-475118 A7 B7 _ V. Description of the invention (14) T 1 0 and address strobe signal A s # — and output (5 0 4) address and instructions A, C, and output (505) 4 cycles of data on LD from T12. But there is no address output at this time. At this time, the command output (5 0 4) of T 1 0 indicates that L D is used as the data bus. The bus connection device (0) that makes a reading request (104) to the main memory control unit 15 at T5, and outputs a response code RSP to the command output (504) at T12 (506). At this time, if it is a time slot transmission protocol, the data bus used is specified by the read request (1 04) of T5, so the address and instructions A, C and address strobe signal AS # (504) are not required. Assume again that at T 8, the bus connection devices (0), (1), and (2) output (901, 601, and 801) bus usage request signals, and respond to the address of T 8 and the instructions A, C, and The address strobe signal AS # (4 0 4), at T 9, the main memory control unit 15 requests 4 cycles of data transmission. 9 0 1 is an address-only transmission request, 8 0 1 is a 4-cycle data transmission request, and 60 0 1 is a 1-cycle data transmission request. The arbiter made the ruling, using GRT (1) # to connect the bus connection device (1) (602) at T10, and granting the right to use the bus to the main memory control unit 15 (not shown) at T11, using GRT ( 2) # Grant bus usage right to the bus connection device (2) (802) at T12, use GRT (〇) # to grant bus to the bus connection device (0) (9 02) at T 1 3 Right of use. At T 1 〇, the arbiter instructs the bus connection device (1) to use the bus, and at the same time, it does not output the LDSEL # signal to indicate that the use of this paper size applies to the Chinese National Standard (CNS) A4 specification (210X297 mm) (please (Please read the notes on the back before filling in this page)
、1T 經濟部智慧財產局員工消費合作社印製 475118 A7 B7 五、發明説明（15 ) R D當作資料匯流排。 在T 1 2，匯流排連接裝置（1 )中之位址/控制匯 流排連接用L S I 2 3，與位址選通脈衝信號A S # — 併輸出位址及指令A，C，資料匯流排連接用L S I 2 5由上述位址/控制匯流排連接用L S I 2 3之控制 ’在T14於RD上輸出（6〇5) 1個循環之資料。這 時，以T1 2之指令輸出（6 04)表示使用RD作爲資 料匯流排。由匯流排連接裝置（1 )傳送資料之匯流排連 接裝置在T1 4輸出（60 6)對指令輸出（6 04)之 回應碼R S P。 在T 1 1仲裁器向主記憶控制部1 5授與匯流排使用 權，連同匯流排使用權，藉不輸出LDS E L #信號指示 使用R D當作資料匯流排。 在T 1 3，主記憶控制部1 5將連同位址選通脈衝信 號A S # —併輸出（7 0 4 )對匯流排使用權之位址及指 令A，C，並從T15起在RD上輸出（705 )資料。 這時，T1 3之指令輸出（7〇4)指示使用RD當作資 料匯流排。 從主記憶控制部1 5傳送資料之匯流排連接裝置（0 )，在T1 5輸出（706)對指令輸出（704 )之回 應碼R S P。 在τ 1 2，仲裁器將向匯流排連接裝置（2 )，連同 匯流排使用權一併藉輸出LDSEL#信號表示（803 )使用L D當作資料匯流排。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁) 衣· 訂 經濟部智慧財產局員工消費合作社印製 -18 - 475118 A7 B7 五、發明説明（16 ) (請先閲讀背面之注意事項再填寫本頁) 在T 1 4，匯流排連接裝置（2 )中之位址/控制匯 流排連接用L S I 2 3將連同位置選通脈衝信號A S # 一併輸出（804)，對 GRT (2) # (802)之位 址及指令A，C。這時，以T1 4之指令輸出（804 ) 表示使用L D當作資料匯流排。 在T1 5，匯流排連接裝置（0)連同位址選通脈衝 信號AS# —併輸出（904)對，GRT (〇) # ( 902)之位址及指令A，C。 從第4圖可以看出，本發明係在位址，資料分離型匯 流排，與位址，資料多工型匯流排一樣，以流水線方式輸 出位址與資料，而且指定向位址匯流排輸出位址時所使用 之資料匯流排。 而且，本實施例之從授與匯流排使用權至輸出相對應 之位址及指令之間隔爲一定（本實施例爲兩個循環），從 輸出位址及指令至輸出回應之間隔爲一定（本實施例爲兩 個循環）。前者與後者間隔不一樣（例如前者爲3個循環 而後者爲兩個循環）也無坊。 經濟部智慧財產局員工消費合作社印製 再使用第5圖說明表1之匯流排系統之協定之指令及 回應之格式之例子如下。 第5圖（1)係指令信號C<28 — 00>之格式。 最上位5位元之RQC係表示區別讀，寫存取，l/ο存 取等之請求指令，以下2位元之L係傳送資料長度，1位 元之D係所使用資料匯流排之指定，4位元之A T T R係 表 7K 統寫，回寫（wright-through, wright-back)之高 f紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐) ' 一 一 19 一 475118 A7 B7 五、發明説明（17) (請先閲讀背面之注意事項再填寫本頁) 速緩衝控制之類別等之層性，6位元之R Q I D係指令輸 出源之模組號碼及各模組附加之傳送號碼，8位元之BE 係位元組使能（byte enable)，最下位3位元之S P C 係表示診斷存取，異常處理存取等之特殊指令，D位元以 外均與上述傳統技術之匯流排一樣。在分割傳送協定之回 應（以下稱作分割回應）時，僅表示分割回應之R Q C及 表示傳送號碼之RQ I D有效，傳送號碼係與分割方式時 之傳送請求時所附之R Q I D相同之號碼。 經濟部智慧財產局員工消費合作社印製 第5圖（2 )係平常時（即，傳送請求時，寫入時等 分割回應時以外）及分割回應時之回應碼RSP<7—0 >之格式。平常時之RE 3至REO及REM係各4個之 P E 1 4及主記憶控制部1 5之錯誤檢測位元，T 1及 T 0係對閱讀請求之主記憶控制部1 5之回應時間預告， A C K係指定位址之模組之正常回應位元。分割回應時， 4個PE 1 4係分別以2位元（R00與R0 1 ，R1 〇 與R 1 1等）回應高速緩衝記憶器之狀態，控制動作及錯 誤檢測之有無。以上之回應碼R S P格式之內容全部與傳 統技術之分割傳送協定之匯流排一樣。在此，PE 1 4爲 4個只是一個例子，係對應設計時之P E 1 4之最大數。 其次參照第6圖說明第4圖之仲裁器之兩系統之資料 匯流排之程序管理之動作。在本發明，位址匯流排係與傳 統技術之匯流排一樣，可以進行裁決控制。而爲了兩系統 之資料匯流排之程序管理而在仲裁器重新配設8位元之內 部表格。內部表格係L D例及RD例各4位元，分別表示 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -20 - 475118 A7 B7 五、發明説明（18 ) (請先閲讀背面之注意事項再填寫本頁) 5循環至8循環前方之使用狀況。再者，在此之所謂5循 環係由，向下一循環授與匯流排權許可，至從請求匯流排 權之匯流排連接裝置輸出位址及指令爲止之循環數（本實 施例爲2)，加上從成爲上述匯流排連接裝置之對方之匯 流排連接裝置輸出回應之循環（本實施例爲2 )而定（1 +2+2)。同時，所謂從5循環至8循環之4循環（內 部表格之長度）係由一次進行之傳送循環數之最大值（本 實施例爲4 )而定。L與R之兩列係由資料匯流排之系統 數而定。這些值不限於本實施例，應依各回應循環，傳送 循環，資料匯流排系統數而定，而對應此內部表格之架構 也會變化。此內部表格可在仲裁器內部用習用之暫存器等 構件構成之。 第6圖係表示在第4圖之定時圖之仲裁器之內部處理 例之狀態圖。再者，圖中之（ ）內表示目前之循環數。 在T 2時，仲裁器未對任何匯流排連接裝置授與資料 匯流排之使用權，這時之內部表格與初期狀態相同，所有 位元爲0。 經濟部智慧財產局員工消費合作社印製 在T1之RQ ( 1 )，傳送資料長度爲4，因此仲裁 器則將匯流排使用權授與匯流排連接裝置（1 )，決定資 料匯流排係從T 8使用L 一 D A T A 1 2 4個循環。而仲 裁器則在T 3於內部表格之L側4位元寫入1 ，並在T 4 輸出 G R T ( 1 ) #。 在T3之RQ (2)，因傳送資料長度爲4，因此仲 裁器則對匯流排連接裝置（2 )授與匯流排使用權’決定 本紙張尺度適用中國國家標準（CNS ) A4規格（21〇><297公釐） 一 21 , 475118 A7 B7 五、發明説明（19 ) (請先閲讀背面之注意事項再填寫本頁) 從T 9起使用4循環之R — D ATA 13當作資料匯流排 。而仲裁器則在T4將1寫入內部表格之R側4位元。在 T 5輸出G R T ( 2 ) #。另一方面，L側由時間經過而 向左移位1個位元，而在空的位元寫入0。 在T 5及T 6兩側均只移位。因爲表示兩側之資料匯 流排均要被使用，仲裁器不能重新將資料匯流排之使用權 授與任何匯流排連接裝置。仲裁器在縱使有位址匯流排空 出來，仍令欲使用資料匯流排之匯流排連接裝置等候^ 在T 7 L側空出來時，仲裁器將對回應閱讀請求之主 記億控制部1 5授與匯流排使用權，而在內部表格之L側 4位元寫入1。 在T 8時，R側會空出來，但因無請求，因此R側全 成爲0… 在T9，仲裁器會對T8之RQ (1) (60 1)回 經濟部智慧財產局員工消費合作社印製 應而對匯流排連接裝置（1 )授與匯流排使用權，但資料 匯流排之使用爲1個循環，因此仲裁器僅在R側之最左端 之1位元寫入1。但此僅1位元之寫入在實際之動作時可 以省略。 如以上所述，仲裁器可使用內部表格進行兩系統之資 料匯流排之程序處理。資料匯流排爲兩系統以上時，亦可 如上述進行程序管理。同時，在傳送協定採用時槽傳送協 定時，仍可與上述一樣將一定間隔後之回應之資料匯流排 之使用寫入內部表格，以管理多系統之資料匯流排之程序 。時槽傳送協定時，內部表格之長度依上述一定間隔之長 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -22 - 475118 經濟部智慧財產局員工消費合作社印製 A7 B7五、發明説明（20) 度而定。 再參照第7圖說明本發明之其他實施例。 第7圖設有1個系統之位址/控制匯流排與4個系統 之資料匯流排。在本圖內，7 0係本發明之系統匯流排， 7 1係系統匯流排7 0中之1個系統之位址/控制匯流排 ，72 ，73 ，74及75係系統匯流排70中之4個系 統之資料匯流排（DATA — 〇〜DATA - 3)。第7 圖中除了系統匯流排7 0以外，其架構與第1圖相同， P E 1 4係例如在第2圖，可將匯流排介面控制器中之資 料匯流排連接用L S I 2 4及2 5，分別連接到系統匯流 排7 0之各兩系統之資料匯流排而實現之。 第8圖係表示第7圖之匯流排系統之協定之例子之定 時圖。D — 〇至〇 — 3係4系統之資料匯流排（DATA 一 0〜DATA— 3) ，DSEL係擴張成2位元之資料 匯流排指示信號，其他信號則與第4圖一樣。 第8圖所示之例子係以資料長度4循環進行所有之傳 送。這時，因位比匯流排爲1個系統而位址傳送爲1個循 環，資料匯流排有4個系統而資料傳送有4個循環，因此 可使位址匯流排及所有資料匯流排之使用效率最大。 在丁 2 1 ，匯流排連接裝置（0 )及（1 )使用R Q (0 ) ，R Q ( 1 )輸出（1 1 Ο 1 及 1 2 0 1 )匯流排 使用權請求信號。主記憶控制部1 5內之仲裁器進行裁決 ，在T2 3用GRT (0) #向匯流排連接裝置授與（ 1102)匯流排使用權，並在T24用GRT(1)# 本紙張尺度適用中國國家標準（CNS ) A4規格（210X：297公釐） ~ -23 - (請先閲讀背面之注意事項再填寫本頁) 475118 經濟部智慧財產局員工消費合作社印製 A7 B7五、發明説明（21 ) 向匯流排連接裝置（1 )授與（1 2 0 2 )匯流排使用權 〇 在T 2 3，仲裁器將向匯流排連接裝置（1)連同匯 流排使用權一併藉輸出D S E L信號指示使用D - 0作爲 資料匯流排，在T 2 4，仲裁器則向匯流排連接裝置（1 )指示（1 2 0 3 )使用D - 1作爲資料匯流排。 在T2 5，匯流排連接裝置（〇)在接受GRT (〇 )# ( 1 1 0 2 ) ，DSEL(ll〇3)後，連同位址 選通脈衝信號A S # —併輸出（1 1 〇 4 )位址及指令A ，C，並從T27起，匯流排連接裝置（0)則在D - 〇 上輸出（1 1 0 5) 4循環之資料。這時，T2 5之指令 輸出（1 1 04)指示使用D-Ο作爲資料匯流排。 在T26，匯流排連接裝置（1)連同位址選通脈衝 信號A S # —併輸出（1 2 0 4 )對G R T ( 1 ) # ( 1202) DSEL (1203)之位址及指令信號A， C，並從T28起，匯流排連接裝置（1)在D - 1上輸 出（1205) 4循環之資料。這時，T26之指令輸出 (1 2 0 4 )指示使用D — 1作爲資料匯流排。 其次在T2 3及T24，各匯流排連接裝置（2)及 (〇)使用 RQ(2) ，RQ(0)輸出（1301 及 1 4 0 1 )匯流排使用權請求信號。 仲裁器則進行裁決，在T25使用GRT(2)#向 匯流排連接裝置（2 )授與（1 3 0 2 )匯流排使用權， 並在T26使甩GRT (〇) #向匯流排連接裝置（0) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐) (請先閲讀背面之注意事項再填寫本頁) -24 - 475118 A7 B7 五、發明説明（22) 授與（1402)匯流排使用權。 (請先閱讀背面之注意事項再填寫本頁) 在丁 2 5，仲裁器向匯流排連接裝置（2)連同匯流 排使用權，一併藉輸出（1303) ，DSEL信號指示 使用D - 2作爲資料匯流排，在T 2 6，仲裁器向匯流排 連接裝置（0 )連同匯流排使用權，一併藉輸出D S E L 信號指示使用D - 3，作爲資料匯流排。 匯流排連接裝置（2)在接受GRT (2) # ( 1 3 0 2 ) ，DSEL(1303)後，在 T27 連同位 址選通脈衝信號A S # —併輸出（1 3 0 4 )位址及指令 A，C，並從T 29起在D - 2上輸出（1305) 4循 環之資料。這時，T27之指令輸出（1 304)指示使 用D — 2作爲資料匯流排。 經濟部智慧財產局員工消費合作社印製 而匯流排連接裝置（0)在接受GRT (〇) # ( 1402) ，DSEL(1403)後，在 T28 連同位 址選通脈衝信號A S # —併輸出（1 4 0 4 )位址及指令 A，C，並從T30起在D — 3上輸出（140 5 ) 4循 環之資料。這時，T2 8之指令輸出（1 404)指示使 用D — 3作爲資料匯流排。在T 3 0，匯流排連接裝置（ 〇)係使用兩系統之資料匯流排D — 〇及D — 3，同時傳 送依據兩個RQ(〇) (11 0 1及1401)之個別之 資料。 在本實施例，因仲裁器含在主記憶控制部1 5內，主 記憶控制部1 5雖是匯流排連接裝置，但不向外部輸出匯 流排權請求及許及信號，主記憶控制部i 5之傳送請求係 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -25 - 475118 A7 __ B7 __ 五、發明説明（23) 在仲裁器之內部處理。 (請先閲讀背面之注意事項再填寫本頁) 在本實施例，主記憶控制部1 5對未圖示之T 2 1以 前之其他匯流排連接裝置之請求閱讀回應，而在T 2 4請 求4循環之資料傳送。仲裁器在內部處理之結果，在 T 2 7向主記憶控制部1 5授與匯流排使用權，與匯流排 使用權一併輸出DSEL信號，指示（1 50 3)使用D - 0作爲資料匯流排。這時仲裁器在進行4系統之資料匯 流排之程序管理，到T 3 0時所有之資料匯流排在使用中 (1105 ，1205 ，1305 ，1405)，因此令 其等候到T 2 7始向主記憶控制部1 5授與匯流排使用權 ，而主記憶控制部1 5則從T 3 1起傳送資料。 在向主記憶控制部1 5授與匯流排使用權後，在 T 2 9連同位址選通脈衝信號信號a S # —併輸出（ 1 5 04)位址及指令a，C，並在T3 1於D — 0上輸 出（1505) 4循環之資料。這時，T29之指令輸出 (1 5 0 4 )指示使用D — 〇作爲資料匯流排。 經濟部智慧財產局員工消費合作社印製 對主記憶控制部1 5於T 2 0以前請求閱讀之匯流排 連接裝置，對指令輸出（1504)，於T31輸出未圖 示之回應碼RSP。 如_h述’本實施例係多系統之資料匯流排與1系統之 位址匯流排連繫動作。 上述兩個實施例，係就資料匯流排爲2及4系統之情 形進行說明，但除此以外之系統數亦可同樣實現。 再者’依據本發明時，位址匯流排爲丨個系統，因此 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -26 - 475118 A7 B7 五、發明説明（24) ，具有資料匯流排系統數之增加很容易之擴充容易性。 (請先閲讀背面之注意事項再填寫本頁) 再者，本發明之匯流排系統指的是，備有仲裁器，且 連接有一個以上之內含一個以上之匯流排主控裝置之匯流 排連接裝置，或可連接之母板（mother board)。而匯流 排連接裝置可以是實裝在可從母板分離之卡片，亦可聚積 在母板上。 而上述各實施例之各處理器元件進一步備有多數之處 理器，但不限定如此，任意之處理器元件備有單一之處理 器亦可。 同時如上述，依據本發明時，從一個匯流排連接裝置 輸出多數之匯流排權請求時，分開資料匯流排則可平行進 行傳送，因此，縱使備有多數之處理器之處理器元件另有 一個也可應用本發明。 而上述各實施例之含有匯流排主控裝置者係以處理器 元件，及I / 0控制部爲例子，但不限定如此，只要備有 多數之匯流排主控裝置者，均可應用本發明。 經濟部智慧財產局員工消費合作社印製 同時，上述各實施例係說明以同一時間脈衝信號來傳 送位址與資料，但亦可以由位址匯流排之時間脈衝之循環 數來決定資料匯流排之使用期間，在其範圍內，使用例如 用雙倍快速之時脈信號之源始同步傳送方式。 而當在上述多數之之資料匯流排內之任何處發生故障 時，仲裁器很容易禁止使用該資料匯流排，進行縮退控制 〇 如以上所述，依據本發明時，因爲位址匯流排只有一 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -27 - 475118 經濟部智慧財產局員工消費合作社印製 A7 _ B7五、發明説明（25 ) 個系統，因此平行設置多條資料匯流排，控制邏輯也不會 變複雜，可獲得有更高之傳送能力之匯流排控制方法，及 使用此之匯流排控制用L S I ，以及使用此之匯流排系統 〇 同時，依據本發明時，因位址匯流排只有一個系統， 因此可以獲得，一面可抑制匯流排系統整體之信號針腳數 之增加，同時可獲得有更高傳送能力之匯流排系統。 同時，依據本發明時，因位址匯流排只有一個系統， 因此可以獲得，一個可抑制信號針腳數之增加，同時有更 高傳送能力之匯流排控制用L S I 。 同時，依據本發明時，因位址匯流排只有一個系統， 因此可以獲得，可以抑制信號針腳數之增加，而一個抑制 其價格，同時有更高傳送能力之匯流排系統，或匯流排控 制用L· S I 〇 同時，依據本發明時，因位址匯流排只有一個系統， 因此可以獲得，控制邏輯不會複雜，信號針腳數之增加較 少’可一個抑制消耗電力，同時可以有更高傳送能力之匯 流排系統，或匯流排控制用L S I 。 同時，依據本發明時，因爲位址匯流排只有一個系統 ，因此可以獲得，控制邏輯不會複雜，一面確保高可靠度 ，同時有更高傳送能力之匯流排系統，或匯流排控制用 LSI。 同時’依據本發明時，因爲位址匯流排只有一個系統 ，因此可以獲得，控制邏輯不會複雜，開發過程短，且有 本紙張尺度適用中國國家標準（CNS ) A4規格（210父297公襲1 "" " -28 - (請先閲讀背面之注意事項再填寫本頁) 475118 A7 B7 五、發明説明（26) 更高傳送能力之匯流排系統，或匯流排控制用L S I 。 圖式之簡單說明 (請先閱讀背面之注意事項再填寫本頁) 第1圖係表示使用本發明之具有兩系統資料匯流排之 匯流排系統之資料處理裝置之硬體架構例子之方塊圖。 第2圖係表示第1圖之處理器元件14之內部架構之 一個例子之L S I架構圖。 第3圖係表示第1圖之處理器元件14之內部架構之 另一個例子之L S I架構圖。 第4圖係表示表1之匯流排系統之協定之例子之定時 圖。 第5圖係表示表1之匯流排系統之協定之指令及回應 格式之例子之圖。 第6圖係表示第4圖所示定時圖之仲裁器之內部表處 理之例子之狀態圖。 第7圖係表示使用本發明具有四系統資料匯流排之匯 流排系統之資料處理裝置之硬體架構例子之方塊圖。 經濟部智慧財產局員工消費合作社印製 第8圖係表示第7圖之匯流排系統之協定之例子之定 時圖。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -29 -Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs of the Ministry of Economic Affairs of the People's Republic of China. 475118 A7 B7 V. Invention Description (15) R D is used as the data bus. At T 1 2, the address / control bus connection LSI 2 3 in the bus connection device (1) is connected to the address strobe signal AS # — and outputs the address and command A, C, and data bus connection. Using the LSI 25, the above-mentioned address / control bus connection control LSI 23 is used to output (605) one cycle of data on the RD at T14. At this time, the command output of T1 2 (604) indicates that RD is used as the data bus. The bus connection device that transmits data from the bus connection device (1) sends a response code RSP at the T1 4 output (60 6) to the command output (6 04). At T 1 1 the arbiter grants the master memory control unit 15 the right to use the bus, together with the right to use the bus, by not outputting the LDS E L # signal instruction uses R D as the data bus. At T 1 3, the main memory control unit 15 together with the address strobe signal AS # — and outputs (7 0 4) the address and instructions A, C for the right to use the bus, and it will be on RD from T15. Output (705) the data. At this time, the command output (704) of T1 3 instructs to use RD as the data bus. The bus connection device (0) for transmitting data from the main memory control unit 15 outputs a response code R S P at T1 5 output (706) to the command output (704). At τ 1 2, the arbiter will connect the device to the bus (2), and use the output LDSEL # signal to indicate (803) to use the bus as the data bus along with the right to use the bus. This paper size applies to China National Standard (CNS) A4 (210X297 mm) (Please read the precautions on the back before filling out this page) Clothing · Order Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs Consumer Cooperatives -18-475118 A7 B7 5 、 Explanation of invention (16) (Please read the notes on the back before filling in this page) At T 1 4, the address / control bus connection LSI 2 in the bus connection device (2) will be accompanied by the position strobe pulse The signal AS # is also output (804), the address of the GRT (2) # (802) and the instructions A and C. At this time, the command output (804) of T1 4 indicates that L D is used as the data bus. At T1 5, the bus connection device (0) together with the address strobe signal AS # — and outputs (904) pairs, the address of the GRT (0) # (902) and the instructions A, C. It can be seen from FIG. 4 that the present invention is in the address, data separation type bus, which is the same as the address and data multiplex type bus, and outputs the address and data in a pipelined manner, and specifies the output to the address bus. The data bus used in the address. Moreover, in this embodiment, the interval from the grant of bus usage rights to the corresponding address and instruction corresponding to the output is constant (two cycles in this embodiment), and the interval from the output address and instruction to the output response is constant ( This embodiment is two cycles). The former is not the same as the latter (for example, the former has 3 cycles and the latter is two cycles). Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, and then using Figure 5 to illustrate the order and response format of the bus system agreement in Table 1 as an example. Fig. 5 (1) shows the format of the command signal C < 28 — 00 >. The top 5 digits of RQC are request instructions for distinguishing read, write access, l / ο access, etc., the following 2 digits L is the length of the transmitted data, and the 1 digit D is the designation of the data bus The 4-bit ATTR is written in Table 7K. The high-f paper size of wright-through (wright-back) is applicable to the Chinese National Standard (CNS) A4 (210X297 mm). 1-1 19 475118 A7 B7 V. Description of the invention (17) (Please read the precautions on the back before filling in this page) The hierarchy of the type of cache control, etc., 6-bit RQID is the module number of the command output source and the additional transmission of each module Number, 8-bit BE is byte enable, and the lowest 3 bits of SPC are special instructions for diagnostic access, exception handling access, etc. Other than D-bit are the same as the above-mentioned traditional technology. The bus is the same. When responding to a split transmission agreement (hereinafter referred to as a split response), only the R Q C indicating the split response and the RQ ID indicating the transmission number are valid. The transmission number is the same number as the R Q ID attached to the transmission request in the division mode. Figure 5 (2) printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs is the response code RSP < 7-0 > format. Normally RE 3 to REO and REM are error detection bits of 4 PE 1 4 and the main memory control unit 15 each, and T 1 and T 0 are advance notice of the response time to the main memory control unit 15 of the read request , ACK is the normal response bit of the module with the specified address. When splitting the response, the four PE 1 4 series responded to the status of the cache memory with 2 bits (R00 and R0 1, R1 〇 and R 1 1 etc.), the control action and the presence or absence of error detection. The content of the above response code RSP format is all the same as the bus of the split transmission protocol of the conventional technology. Here, PE 1 4 is only an example, which corresponds to the maximum number of P E 1 4 at the time of design. Secondly, referring to Fig. 6, the data management system of the arbiter in Fig. 4 will be described. In the present invention, the address bus is the same as the bus of the conventional technology, and it can carry out ruling control. For the management of the data bus of the two systems, an internal table of 8 bits is reconfigured in the arbiter. The internal form is 4 digits for LD and RD, respectively, indicating that the paper size is applicable to the Chinese National Standard (CNS) A4 (210X297 mm) -20-475118 A7 B7 V. Description of the invention (18) (Please read the back first (Notes on this page, please fill in this page) 5 cycles to 8 cycles in front of the use. Moreover, the so-called 5 cycles here are the number of cycles from granting the bus permission to the next cycle to the address and instruction output from the bus connection device requesting the bus right (this embodiment is 2) , Plus the cycle of response output from the bus connection device that becomes the counterpart of the above bus connection device (2 in this embodiment) (1 + 2 + 2). Meanwhile, the so-called 4 cycles (the length of the internal table) from 5 cycles to 8 cycles are determined by the maximum number of transmission cycles performed at one time (4 in this embodiment). The two columns L and R are determined by the number of systems in the data bus. These values are not limited to this embodiment, but should depend on the number of response cycles, transmission cycles, and data bus systems, and the structure corresponding to this internal table will also change. This internal form can be constructed inside the arbiter using conventional registers and other components. Fig. 6 is a state diagram showing an internal processing example of the arbiter in the timing diagram of Fig. 4; In addition, () in the figure indicates the current cycle number. At T 2, the arbiter did not grant the right to use the data to any bus connection device. At this time, the internal table is the same as the initial state, and all bits are 0. The Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs printed the RQ (1) on T1, and the length of the transmitted data is 4, so the arbiter will grant the right to use the bus to the bus connection device (1). 8 Use L-DATA 1 2 4 cycles. The arbiter writes 1 to the 4 bits on the L side of the internal table at T 3 and outputs G R T (1) # at T 4. In the RQ (2) of T3, because the length of the transmitted data is 4, the arbiter grants the bus connection device (2) the right to use the bus' to determine that this paper size applies the Chinese National Standard (CNS) A4 specification (21〇 > < 297 mm) 1 21, 475118 A7 B7 V. Description of the invention (19) (Please read the precautions on the back before filling out this page) From T 9 use 4 cycles of R — D ATA 13 as information Bus. The arbiter writes 1 to the 4 bits on the R side of the internal table at T4. G T (2) # is output at T 5. On the other hand, the L side is shifted to the left by 1 bit from the passage of time, and 0 is written to the empty bit. Only shift on both sides T 5 and T 6. Because the data buses on both sides are to be used, the arbiter cannot re-authorize the use of the data bus to any bus connection device. Even if the arbiter empties out the address bus, it still makes the bus connection device that wants to use the data bus wait ^ When the T 7 L side is vacated, the arbiter will respond to the read request of the master control unit 1 5 The right to use the bus is granted, and 1 is written in 4 bits on the L side of the internal form. At T 8, the R side will be vacated, but because there is no request, the R side will be all 0 ... At T9, the arbiter will return the RQ (1) (60 1) of T8 to the Intellectual Property Bureau employee consumer cooperative. In response, the bus connection device (1) is granted the right to use the bus, but the use of the data bus is 1 cycle, so the arbiter only writes 1 in the leftmost bit on the R side. However, this 1-bit write can be omitted during actual operation. As mentioned above, the arbiter can use the internal form to process the data buses of the two systems. When the data bus is more than two systems, the program management can also be performed as described above. At the same time, when the transmission protocol adopts the time slot transmission protocol, the use of the response data bus after a certain interval can still be written into the internal table, as described above, to manage the multi-system data bus process. In the time slot transmission agreement, the length of the internal form is based on the long paper at a certain interval as described above. The Chinese national standard (CNS) A4 specification (210X297 mm) is applicable. 、 Description of invention depends on (20) degree. Referring to Fig. 7, another embodiment of the present invention will be described. Figure 7 has an address / control bus for one system and a data bus for four systems. In the figure, 70 is the system bus of the present invention, 71 is the system address / control bus of one of the 70 buses, 72, 73, 74, and 75 are the system bus 70 Data bus for four systems (DATA — 〇 ~ DATA-3). Except for system bus 70 in Figure 7, its architecture is the same as that in Figure 1. PE 1 4 is shown in Figure 2. For example, the data bus in the bus interface controller can be connected to LSI 2 4 and 2 5 It is realized by connecting to the data buses of each of the two systems of the system bus 70 respectively. Fig. 8 is a timing chart showing an example of the agreement of the busbar system of Fig. 7. D — 0 to 0 — 3 is the data bus of the 4 system (DATA — 0 to DATA — 3), DSEL is expanded to a 2-bit data bus indicator signal, and other signals are the same as in Figure 4. The example shown in Fig. 8 performs all transmissions with a data length of 4 cycles. At this time, because the bit ratio bus is one system and the address transmission is one cycle, the data bus has four systems and the data transmission has four cycles, so the use efficiency of the address bus and all data buses can be achieved. maximum. In Ding 2 1, the bus connection devices (0) and (1) use R Q (0), and R Q (1) outputs (1 1 〇 1 and 1 2 0 1) the bus use right request signal. The arbiter in the main memory control section 15 makes a ruling, grants (1102) the bus connection right to the bus connection device with GRT (0) # at T2 3, and uses GRT (1) # at T24. This paper standard applies China National Standard (CNS) A4 Specification (210X: 297 mm) ~ -23-(Please read the notes on the back before filling this page) 475118 Printed by the Consumers ’Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 21) Grant the bus connection device (1) (1 2 0 2) the right to use the bus. At T 2 3, the arbiter will output the DSEL signal to the bus connection device (1) together with the bus use right. The instruction uses D-0 as the data bus. At T 2 4, the arbiter instructs the bus connection device (1) (1 2 0 3) to use D-1 as the data bus. At T2 5, the bus connection device (〇) accepts GRT (〇) # (1 1 0 2), DSEL (ll〇3), together with the address strobe signal AS # — and outputs (1 1 〇4 ) Address and instructions A, C, and from T27, the bus connection device (0) will output (1 1 0 5) 4 cycles of data on D-〇. At this time, the command output (1 1 04) of T2 5 instructs to use D-O as the data bus. At T26, the bus connection device (1) together with the address strobe signal AS # — and output (1 2 0 4) to the address and command signal A, C of GRT (1) # (1202) DSEL (1203) From T28, the bus connection device (1) outputs (1205) 4 cycles of data on D-1. At this time, the command output (1 2 0 4) of T26 instructs to use D — 1 as the data bus. Secondly, at T2 3 and T24, each of the bus connection devices (2) and (〇) uses RQ (2), and RQ (0) outputs (1301 and 1 4 0 1) bus usage request signals. The arbiter made a ruling, using GRT (2) # to grant (1 3 0 2) the right to use the bus to the bus connection device (2) at T25, and the GRT (〇) # to the bus connection device at T26 (0) This paper size applies Chinese National Standard (CNS) A4 specification (210X 297 mm) (Please read the notes on the back before filling this page) -24-475118 A7 B7 V. Description of Invention (22) Granted ( 1402) Bus usage rights. (Please read the precautions on the back before filling this page) In D25, the arbiter borrows the output (1303) with the bus connection device (2) and the right to use the bus, and the DSEL signal indicates that D-2 is used as Data bus. At T 2 6, the arbiter sends the DSEL signal to the bus connection device (0) together with the bus use right to indicate the use of D-3 as the data bus. After the bus connection device (2) accepts the GRT (2) # (1 3 0 2) and DSEL (1303), it sends the address strobe signal AS # at T27 and outputs (1 3 0 4) the address and Command A, C, and output (1305) 4 cycles of data on D-2 from T 29. At this time, the command output of T27 (1 304) instructs to use D-2 as the data bus. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs and the bus connection device (0) accepts GRT (〇) # (1402) and DSEL (1403), together with the address strobe pulse signal AS # at T28 and outputs ( 1 4 0 4) address and instructions A, C, and output (140 5) 4 cycles of data on D-3 from T30. At this time, the command output (1 404) of T2 8 instructs to use D-3 as the data bus. At T 3 0, the bus connection device (0) uses the data buses D — 0 and D — 3 of the two systems, and simultaneously transmits individual data according to the two RQ (0) (11 0 1 and 1401). In this embodiment, the arbiter is included in the main memory control unit 15. Although the main memory control unit 15 is a bus connection device, it does not output a bus right request and permission signal to the outside. The main memory control unit i The transmission request of 5 is based on the Chinese standard (CNS) A4 specification (210X297 mm) of this paper size. -25-475118 A7 __ B7 __ V. Description of the invention (23) It is processed inside the arbiter. (Please read the precautions on the back before filling this page) In this embodiment, the main memory control unit 15 responds to requests for other bus connection devices before T 2 1 (not shown), and requests at T 2 4 4 cycles of data transmission. As a result of the internal processing by the arbiter, the bus memory use right is granted to the main memory control unit 15 at T 2 7 and the DSEL signal is output together with the bus use right, instructing (1 50 3) the use of D-0 as the data bus row. At this time, the arbiter is managing the data bus of the 4 systems. By T 30, all data buses are in use (1105, 1205, 1305, 1405), so it waits until T 2 7 to start to the main memory. The control unit 15 grants the right to use the bus, while the main memory control unit 15 transmits data from T 31. After granting the bus memory use right to the main memory control unit 15, the address strobe signal signal a S # is output together with the address strobe signal at T 2 9 and the (1 5 04) address and instructions a and C are output, and at T3 1 outputs (1505) 4 cycles of data on D — 0. At this time, the command output (1 5 0 4) of T29 instructs to use D — 〇 as the data bus. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs The bus connection device requested by the main memory control unit 15 before T 2 0 to output a command (1504) to the command, and an unillustrated response code RSP at T31. As described in _h ', this embodiment is an action in which the data bus of multiple systems is linked to the address bus of system 1. The above two embodiments are described with respect to the case where the data buses are 2 and 4 systems, but the number of other systems can also be implemented in the same manner. Furthermore, according to the present invention, the address bus is a single system, so this paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) -26-475118 A7 B7 V. Description of the invention (24), with The increase in the number of data bus systems is easy to expand. (Please read the notes on the back before filling this page.) Furthermore, the bus system of the present invention refers to a bus with an arbiter and connected to more than one bus master device containing more than one bus Connect the device or connectable mother board. The bus connection device can be mounted on a card that can be separated from the motherboard, or it can be accumulated on the motherboard. Each processor element of each of the above embodiments further includes a plurality of processors, but it is not limited to this, and any processor element may be provided with a single processor. As mentioned above, according to the present invention, when a plurality of bus right requests are output from one bus connection device, the separate data buses can be transmitted in parallel. Therefore, even if there is another processor element with a plurality of processors, The invention can also be applied. The above embodiments include the bus master control device as the processor element and the I / 0 control unit as examples, but it is not limited to this. As long as a majority of the bus master control devices are provided, the present invention can be applied. . At the same time as printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, the above-mentioned embodiments explain that the address and data are transmitted with the same time pulse signal, but the data bus can also be determined by the number of cycles of the time pulse of the address bus. During use, within its range, a synchronous transmission method using, for example, a source of double fast clock signals is used. And when a failure occurs in any of the above-mentioned majority of the data buses, the arbiter can easily prohibit the use of the data bus and perform retraction control. As described above, according to the present invention, because the address bus has only one This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) -27-475118 printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 _ B7 V. Invention Description (25) systems, so multiple documents are set up in parallel The control logic of the bus will not become complicated, and a bus control method with higher transmission capacity, a LSI for controlling the bus, and a bus system using the same can be obtained. At the same time, according to the present invention, Because the address bus has only one system, it can be obtained. On the one hand, the increase of the number of signal pins of the bus system can be suppressed, and at the same time, a bus system with higher transmission capacity can be obtained. At the same time, according to the present invention, since there is only one system for the address bus, it is possible to obtain an L S I for bus control that can suppress an increase in the number of signal pins and also has a higher transmission capacity. At the same time, according to the present invention, since there is only one system for the address bus, it can be obtained, which can suppress the increase in the number of signal pins, and a bus system that suppresses its price and has higher transmission capacity, or for bus control. L · SI 〇 At the same time, according to the present invention, because there is only one system for the address bus, it can be obtained, the control logic will not be complicated, and the increase in the number of signal pins will be less. Capability bus system, or bus control LSI. At the same time, according to the present invention, because there is only one system for the address bus, it can be obtained that the control logic is not complicated, while ensuring a high reliability, while having a higher transmission capacity of the bus system, or bus control LSI. At the same time, according to the present invention, because the address bus has only one system, it can be obtained, the control logic is not complicated, the development process is short, and this paper standard is applicable to the Chinese National Standard (CNS) A4 specification (210 parent 297 public attack 1 " " " -28-(Please read the notes on the back before filling out this page) 475118 A7 B7 V. Description of the invention (26) Bus system with higher transmission capacity, or LSI for bus control. Figure A simple description of the formula (please read the precautions on the back before filling this page). Figure 1 is a block diagram showing an example of the hardware architecture of a data processing device using a bus system with two data buses of the present invention. FIG. 2 is an LSI architecture diagram showing an example of the internal architecture of the processor element 14 in FIG. 1. FIG. 3 is an LSI architecture diagram showing another example of the internal architecture of the processor element 14 in FIG. 1. FIG. 4 The diagram is a timing chart showing an example of the agreement of the bus system of Table 1. Fig. 5 is a diagram showing an example of the command and response format of the agreement of the bus system of Table 1. Fig. 6 is the fourth diagram. The state diagram of the example of the internal table processing of the arbiter in the timing diagram shown. Figure 7 is a block diagram showing an example of the hardware architecture of a data processing device using a bus system with four data buses according to the present invention. Ministry of Economic Affairs Figure 8 printed by the Intellectual Property Bureau's Consumer Cooperatives is a timing chart showing an example of the agreement of the bus system in Figure 7. This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) -29-