WO1997023833A1

WO1997023833A1 - Bus system for information processor

Info

Publication number: WO1997023833A1
Application number: PCT/JP1996/001311
Authority: WO
Inventors: Kouichi Okazawa; Masaya Umemura; Takashi Moriyama; Tatsuya Hirai
Original assignee: Hitachi, Ltd.
Priority date: 1995-12-21
Filing date: 1996-05-17
Publication date: 1997-07-03
Also published as: TW475118B

Abstract

A bus system for information processors which does not need to perform any special processing despite of parallel installation of a plurality of buses and has a high transfer ability while the increase of the number of signal pins in the whole bus system is small. A bus separated address-data system is provided with one address bus and a plurality of data buses which are used in relation to the address bus and a means which designates one data bus to be used when an address is outputted to the address bus. In a bus arbitration method, there is provided a means used when a device connected to the bus informs an arbiter of the length of transferred data when the device requests the right of using the bus. There is also provided a means which designates the data bus to be used when the arbiter gives the right of using the bus to the device connected to the bus.

Description

Description Bus system for information processing equipment Technical field

The present invention relates to an address data separation type bus system for an information processing device used in an information processing device such as a personal computer, a work station, and an office processor. Background art

In the information processing device bus system used for information processing devices, the data bus width has been expanded in order to obtain higher transfer capability, but the increase in the data bus width inevitably increases the bus signal. This causes an increase in the number of lines. For this reason, there is a limit to the increase in the data bus width of one bus due to the limit of the number of signal pins of an integrated circuit such as a bus controller and a bus interface unit connected to a node. For this reason, in a high-performance information processing apparatus, for example, multiplexing of buses, that is, a plurality of buses are installed in parallel, as described in Japanese Patent Application Laid-Open No. Hei 6-51910. ing.

In the above prior art, a plurality of bus interface units are provided for a plurality of bus connection devices, respectively, and one of a plurality of buses installed in parallel is used. In this case, special processing occurs by installing multiple buses in parallel, such as processing when access to the same address is performed simultaneously on multiple buses. As a result, the control logic becomes complicated, and the transfer capability does not reach the expected value, reliability decreases, power consumption increases, development man-hours increase, and control circuit prices increase. When multiple address / data separated buses, which are widely used as external buses of a processor (CPU), are installed in parallel, there is an advantage that the address bus and the data bus can be controlled by separate integrated circuits. However, since a plurality of address buses are installed in parallel as in the overnight bus, the number of signal pins in the entire bus system increases significantly, resulting in a problem that the system price increases.

An object of the present invention is to provide a bus control method having a higher transfer capability without complicating the control logic even when a plurality of buses are installed in parallel, and a bus control SI using the bus control method. The purpose of the present invention is to provide a bus system that uses a computer.

Further, a specific object of the present invention is to provide a bus system which can obtain a higher transfer capability while suppressing an increase in the number of signal pins of the entire bus system.

Further, a specific object of the present invention is to provide a bus control LSI capable of obtaining a higher transfer capability while keeping the increase in the number of signal pins small. Further, a specific object of the present invention is to provide a bus system or a bus control LSI that achieves higher transfer performance while suppressing the cost.

Further, a specific object of the present invention is to provide a bus system or a bus control LSI that achieves higher transfer capability while suppressing power consumption. To provide a bus system or bus control LSI that achieves higher transfer capability while ensuring reliability.

Another object of a specific invention, the number of development steps is short, and the disclosure of the _c invention is to provide a bus system, or bus control LSI to achieve higher transfer capacity

In the present invention, in order to achieve the above object, an address / data separation type bus In the system, one address bus and a plurality of data buses that cooperate with the address bus are provided. Also, in order to cooperate with the address bus and the data bus, a means for specifying the data bus to be used when outputting an address to the address bus is provided.

Further, in the present invention, means is provided for the bus connection device to notify the arbiter of the transfer data length when the bus use right is requested. To cooperate with the address bus and data bus, a method is provided to specify the data bus to be used when the arbiter gives the bus connection right to the bus connection device. In the present invention, the one address bus and the plurality of data buses are controlled in synchronization with the same clock.

According to the present invention, in the address / data separation type bus system, since one address bus and a plurality of data buses cooperating with the address bus are provided, a plurality of address / data separation type buses are installed in parallel. The same transfer capacity as described above can be obtained without installing multiple address buses in parallel like the overnight bus. As a result, the increase in the number of signal pins in the entire bus system can be kept small.

In addition, the link between the address bus and multiple data buses is based on a split transfer protocol that outputs the same address and data as the address / data multiplexed bus to the address / data segregation bus in a pipelined manner, as well as the address bus. This can be realized by specifying the data bus to be used when outputting the address to the device. As a result, even if multiple data buses are installed, only one address bus is used, so that special processing such as processing for simultaneous access to the same address is not required.

Further, in the present invention, as a bus arbitration method, a method is employed in which a bus connection device notifies a transfer data length to an arbiter when a bus use right is requested, and when the arbiter grants a bus use right to the bus connection device. To The data bus to be used is specified.

In addition, this makes it possible to perform arbitration while managing the use schedule of a plurality of data buses, such as the arbiter transfer data length, so that it is easy to link one address bus with a plurality of data buses. Can be realized.

In the present invention, since the address bus and a plurality of data buses are controlled in synchronization with the same clock, the read transfer is performed twice as a request transfer and a response as a protocol for read transfer. By using a split transfer protocol that divides data into multiple parts or a time slot transfer protocol that fixes the interval between read transfer requests and responses to a fixed time in the split transfer protocol, the address bus and multiple data Buses can be linked easily.

In the split transfer protocol, in particular, the arbiter is built into a bus connection device that does not include a bus master, such as the main memory control unit. Can be reduced.

By controlling the address bus and multiple data buses in synchronization with the same clock, if a failure is detected in some of the multiple data buses, the failed data bus is not used. A degeneration function that operates using only a normal data bus can be realized. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a block diagram showing an example of a hardware configuration of an information processing apparatus using a bus system having two data buses according to the present invention ₍ FIG. 2 shows a processor element 14 in FIG. 1). Fig. 3 is an LSI configuration diagram showing an example of the internal configuration of the processor. FIG. 8 is an LSI configuration diagram showing another example of the internal configuration of the ment 14. Fig. 4 is a timing chart showing an example of the protocol of the bus system shown in Table 1. FIG. 5 is a diagram showing an example of a command and response format in the protocol of the bus system shown in Table 1. FIG. 6 is a state diagram showing an example of arbiter internal table processing in the timing chart of FIG. FIG. 7 is a block diagram showing an example of a hardware configuration of an information processing apparatus using a bus system having four data buses according to the present invention. FIG. 8 is a timing chart showing an example of the protocol of the bus system in FIG. BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, an embodiment of the present invention will be described with reference to FIGS. 1 to 8 and Table 1. c Table 1 is a list of signal lines showing an example of the signal configuration of the bus in FIG.

In the system bus of the embodiment shown in FIG. 1, one address Z control bus and two data buses are provided. In FIG. 1, reference numeral 10 denotes a system bus according to the present invention, 11 denotes one system address control bus (ADR / CNTL) in the system bus 10, and 12 and 13 denote two systems data in the system bus 10. Buses (L-DATA and R-DAT A), 14 is a plurality of processor elements (PE) connected to the system bus 10, 15 is a main memory control unit connected to the system bus 10, 16 is main memory, and 17 is An IZO bus control unit connected to the system bus 10 is an IZO bus. The PE 14, main memory control unit 15, and IZO bus control unit 17 are called bus connection devices. Reference numeral 91 denotes a bus right request line (RQ (*) <3-0> in Table 1 described later) that is individually connected from each bus-connected device to each of the devices in the main memory control unit, and 92 denotes an arbiter to each bus-connected device. Bus right grant lines (GRT (*) # in Table 1 below) that are individually connected to Reference numeral 3 denotes a signal (LDSEL # in Table 1 described later) that is connected to each bus connection device and indicates a data bus to be used.

Here, the PE 14 and the I / 0 bus control unit 17 include a bus master, but the main memory control unit 15 does not include a bus master.

FIG. 1 shows a multiprocessor system in which the PEs 14 each include a plurality of CPUs. The system configuration is the same as that of the prior art in which the plurality of buses are installed in parallel, except for the system bus 10. Can be. Even when a system configuration having a plurality of main memory control units or an IZO bus control unit, or a system configuration in which the main memory control unit and the one-to-one bus control unit are integrated is used, the present invention Applicable. In the present embodiment, it is assumed that the arbiter of the system bus 10 is installed in the main memory control unit 15.

Next, an example of the internal configuration of the PE 14 is shown in FIG. In FIG. 2, reference numeral 20 denotes a plurality of CPUs, reference numeral 21 denotes an address Z control bus (AZC) in the external bus of the CPU 20, reference numeral 22 denotes a data bus (D) in the external bus of the CPU 20, and reference numeral 23 denotes a system bus 10. Address Z control bus connection LSI in the bus interface controller to be connected, 24 and 25 are data bus connection LSIs in the bus interface controller connected to the system bus 10, and 26 and 27 are bus interfaces connected to the system bus 10. This is the control signal between LSIs of the interface controller. One address Z control bus connection LSI 23 and two data bus connection LSIs 24 and 25 are LSIs constituting a bus interface controller connected to the system bus 10 in the PE 14, and Are collectively referred to as bus control LSIs.

In FIG. 2, a plurality of CPUs 20 are connected by an address / data separation type external bus, and each CPU 20 has a built-in cache memory. LSI 23 is connected to the CPU 20 external address bus. Data bus connection LSIs 24 and 25 are connected to the ADRZCNTL 11 of the system bus 10 and the system bus 10 and are connected to the external bus of the CPU 20. Data buses L-DATA 12 and R-DAT A 13 respectively. The data bus connection LSIs 24 and 25 are controlled by control signals 26 and 27 from the address / control bus connection LSI 23.

The bus interface controller connected to the system bus 10 is also realized in the main memory control unit 15 and the IZO bus control unit 17 with the same LSI configuration.

FIG. 3 shows another example of the internal configuration of the PE 14. In FIG. 3, a shared cache memory (PE cache) 30 in the processor element is added to the configuration of FIG. The PE cache 30 is positioned at an intermediate level between the cache memory and the main memory in which the CPU 20 is built, and the address control line 31 from the LSI control bus connection LSI 23 and the data bus connection LSI 24 And 25 are connected to the bus interface controller by data lines 32 and 33.

Next, an example of the signal configuration of the bus 10 according to the present invention is shown in Table 1 on the next page. Table 1 shows the signal names, the number of signal lines, and the meaning of the signals from the left. In the signal names in Table 1, the suffix # indicates negative polarity, and (*) indicates an individual connection control line for arbitration. Hereinafter, each signal will be described.

In Table 1, the system bus 10 is a clock synchronous system, and CLK is a bus clock, which is supplied to all LSIs connected to the system bus 10. LD <63-00> and RD 63-00> are the data of the two data buses L-DAT A12 and R-DAT A13 in the system bus 10, respectively, and are 8 bytes, that is, 64 bits. There is a width of the bird. LDE 7-0> and R table 1

DE is the error check code (ECC) added to LD-63-00> and RD-63-00>, respectively. The data buses are L-DATA12 and R-DATA13, respectively. included.

RQ (*) <3-0> is a 4-bit bus use request signal that each bus-connected device outputs individually to the arbiter. To the four bits Indicates the transfer data length as information. GRT (*) # is a bus grant signal that is individually input from the arbiter to each bus connection device, and LDS EL # is a data bus instruction signal that is output by the broadcaster simultaneously with the bus grant signal. is there.

All other signals are included in ADRZCNTL 11 in system bus 10. AS # is an address strobe signal, and indicates that an address and a command are output on ADRZCNTL11.

A-31-03> and C-28-00> are 29-bit address signals and command signals, respectively. The command signal includes a signal indicating which of the two data buses to use. Other command signals and address signals are the same as those of the prior art bus. AP <1-0> and CP <1-0> are the parity added to A <31-03> and C <28-00>, respectively, and are included in the address signal and command signal, respectively. RSP <7-0> is an 8-bit response code signal, which is a response from each bus connection device to the above address signal and command signal (normal reception of address signal and command signal, error detection, or retry) Request). In this embodiment, the address is output from the address Z bus control LSI 23.

PONRST # and BUSRST # are a power-on reset signal and a bus reset signal, respectively, and are the same as the bus reset signal according to the above-described conventional technology. ID * 2-0> (*) is a fixed value ID signal that gives an individual module number to each module connected to the system bus 10.

In Table 1, the maximum number of PEs is four, and the main memory controller 15 and the I / O controller 17 are integrated into one module.

Next, an example of bus control according to the present invention will be described with reference to these figures and FIG. I will tell. Fig. 4 illustrates an example of the split transfer protocol. In FIG. 4, the bus use right request signals RQ (0) to RQ (2) of the three bus connection devices (0) to (2) and the bus use right grant signals GRT (0) # to GRT ( 2) # is indicated. The device numbers in () are device numbers, but the bus connection devices (0) to (2) may be any of the PE 14 and the I / O bus control unit 17 shown in FIG. Hereinafter, the contents of the evening chart in FIG. 4 will be described.

In cycle T1, the bus connection devices (0) and (1) such as the PE 14 and the I / O bus control unit 17 output the bus use right request signal using RQ (0) and RQ (1) ( 10 1 and 20 1). This is output by the address control bus connection LSI 23 in the bus connection device. Reference numeral 101 denotes a transfer request of only an address such as a read request or a cache invalidation request. In this case, it is assumed that the data in the main memory control unit 15 is to be read. 201 is a write transfer request involving four cycles of data transfer. The arbiter in the main memory control unit 15 fetches this information at T1. The arbiter performs an erbitration to the bus connection device (0) at T3 using GRT (0) # and to the bus connection device (1) at T4 using GRT (1) #. The right to use the bus has been granted (102 and 202).

At T4, the arbiter bus connection device (1) is instructed to use the LD as the data bus by outputting the LD SEL # signal together with the right to use the bus (203).

At T5, the address control bus connection LSI 23 in the bus connection device (0) outputs the address and command A, C for GRT (0) # (102) together with the address strobe signal AS # (104) are doing.

At T7, the bus connection device (here, the main memory control unit 15) specified from the bus connection device (0) stores the address of T5 and the commands A and C. The response code RSP for (104) is output (106). In response to the GRT (1) # (202) and LDSEL # (203) of T4, the address 23 and the control bus connection LSI 23 in the bus connection device (1) send the address and the commands A and C at T6 to the address strobe signal. The data bus connection LSI 24 outputs the data along with AS # (204), and outputs the data on the LD for four cycles from T8 (205) under the control of the address / control bus connection LSI 23. At this time, the command output (204) of T6 indicates that the LD is used as the overnight bus.

When the bus connection device (1) is notified that data is to be written, the node connection device outputs the address of T6 and the response code RSP for the commands A and C outputs (204) at T8 (206). ) Next, at T3 and T4, the bus connection devices (2) and (0) output the bus use right request signal using RQ (2) and RQ (0), respectively (301 and 401). I have. 301 is a write transfer request involving four cycles of data transfer, and 401 is a transfer request for only addresses. The arbiter performs an arbitration, using GRT (2) # for the bus connection device (2) at T5 and GRT (0) # for the bus connection device (0) at T6. (302 and 402).

At T5, the arbiter bus connection device (2) is instructed to use the RD as the data bus due to the non-output of the LDSEL # signal together with the right to use the bus.

At T7, the address Z control bus connection LSI 23 in the bus connection device (2) outputs (304) the address and command A, C for the GRT (2) # (302) together with the address strobe signal AS #. .

At T9, the data bus connection LSI 25 in the bus connection device (2) is placed on the data RD under the control of the addressless control bus connection LSI 23. It has 4 cycle output (305). At this time, the command output (304) of T7 indicates that RD is used as the data bus. The bus connection device notified of data writing from the bus connection device (2) outputs (306) the response code RSP to the address of T7 and the command A and C outputs (304) at T9. . In response to the GRT (0) # (402), the bus connection device (0) outputs the address and commands A and C together with the address strobe signal AS # at T8 (404), and the bus connection device (0) The bus connection device to which the address has been transferred from (0) outputs the response code RSP corresponding to the address and the commands A and C at T10 (406).

In this embodiment, since the arbiter is included in the main memory control unit 15, the main memory control unit 15 is a bus connection device, but does not output a bus right request and a grant signal to the outside. The transfer request of the control unit 15 is internally processed by the arbiter. For this reason, although not shown, the main memory control unit 15 responds to the read request by the address and command A, C of T5 and the address strobe signal AS # (104), and outputs four cycles of data at T6. I requested a transfer overnight. As a result of the internal processing, the arbiter gives the main memory control unit 15 the right to use the bus at T8, outputs the LDSEL # signal together with the right to use the bus, and instructs the use of the LD as the data bus (503) ) are doing. At this time, the arbiter manages the schedules of the two data buses. Up to 11], both the 0 and RD data buses are used (205 and 305). It waits until T8 until the main memory controller 15 can be given the right to use the bus at 7, and the main memory controller 15 starts data transfer from T12.

The main memory control unit 15 receives the address and the commands A and C together with the address strobe signal AS # at T10 in response to the right to use the bus. (504), and the data is output on the LD from T12 for 4 cycles (505). However, at this time, there is no need to output the address. In this case, the command output of # 10 (504) indicates that the LD is used as the overnight bus. The bus connection device (0) that made a read request (104) to the main memory control unit 15 at $ 5 outputs a response code RSP to the command output (504) at $ 12 (506). I do. At this time, if the time slot transfer protocol is used, the data bus to be used is specified by the read request (104) in No. 5, so the address and commands A and C and the address strobe signal AS # (504) is unnecessary.

Further, at T8, the bus connection devices (0), (1) and (2) output the bus use right request signals (901, 601 and 801), and the T8 address and command A , C and the address strobe AS # (404), the main memory control unit 15 requests a 4-cycle data transfer at T9. 901 is a transfer request of only the address, 801 is a 4-cycle data transfer request, and 601 is a 1-cycle data transfer request. The arbiter performs arbitration, using the GRT (1) # to connect the bus connection device (1) to the bus connection device (1) (602) at T10, and to the main memory control unit 15 at T11 (not shown) to the GRT (not shown). (2) Use # to give bus connection device (2) to (802) at T12, and use GRT (0) # to give bus connection device (0) to (902) at T13 using GRT (0) #. I have.

At T10, the arbiter, ', and the bus connection device (1) are instructed to use the RD as the data bus by not outputting the LDSEL # signal together with the right to use the bus.

At T12, address Z control bus connection LS in bus connection device (1) 123 outputs the address and command A, C for GRT (1) # (602) together with the address strobe signal AS # (604), and the data bus connection LSI 25 controls the address / control bus connection LSI 23 The data is output on RD for one cycle at T14 (605). At this time, the command output (604) of T12 indicates that RD is used as the overnight bus. The bus connection device to which data is transferred from the bus connection device (1) outputs (606) a response code RSP to the command output (604) at T14.

At T 11, the arbiter has given the bus right to the main memory control unit 15, and instructs the use of the RD as the data bus by not outputting the LDSE L # signal together with the bus right. .

At T13, the main memory control unit 15 outputs (704) the address and command A and C for the right to use the bus together with the address strobe signal AS #, and further outputs the data on RD from T15. (705) have. At this time, the command output (704) of T13 indicates that RD is used as the data bus.

The bus connection device (0) to which data is transferred from the main memory control unit 15 outputs a response code RSP to the command output (704) at T15 (706).

At T12, the arbiter bus connection device (2) is instructed (803) to use the LD as the data bus by outputting the LD SEL # signal together with the right to use the bus.

At T14, the address / control bus connection L S in the bus connection device (2)

Reference numeral 123 outputs (804) an address and commands A and C for the GRT (2) # (802) together with an address strobe signal AS #. At this time, LD is used as the data bus for the command output (804) of T14. Is shown to be used.

At T15, the bus connection device (0) outputs (904) the address and command A, C for GRT (0) # (902) together with the address strobe signal AS #.

As can be seen from FIG. 4, in the present invention, addresses and data are pipeline-outputted on the address / data separation type bus in the same manner as the address / data multiplex type bus, and the address is output on the address bus. Specifies the data bus to be used when performing the operation.

Further, in the present embodiment, the interval from the grant of the bus use right to the output of the corresponding address and command is a fixed interval (two cycles in this embodiment), and after the output of the address and command. There is a constant interval (two cycles in this embodiment) until the response is output. The interval between the former and the latter may be different (for example, three cycles for the former and two cycles for the latter).

Next, examples of command and response formats in the protocol of the bus system shown in Table 1 will be described with reference to FIG.

Fig. 5 (1) shows the format of the command signal C-28-00>. RQC of the most significant 5 bits is a request command that indicates the distinction between read / write and memory access.I, 0 access, etc.Hereafter, L of 2 bits is transfer data length, D of 1 bit is used data bus. 4-bit ATTR is an attribute that indicates the type of cache control of write-through / write-back, etc., 6-bit RQ ID is the module number of the command output source and the transfer number added by each module, and 8 bits. The BE in the table is a bit enable, and the 3 least significant bits of the SPC are special commands indicating diagnostic access, error processing access, etc., except for the D bit, which is the same as the above-mentioned conventional bus. Responses in the split transfer protocol (hereinafter, split In some cases, only the RQC that indicates a split response and the RQ ID that indicates the transfer number are valid, and the transfer number is the same as the RQ ID that was assigned at the time of the transfer request in the split system. .

FIG. 5 (2) shows the format of the response code RSP <7-0> in the normal state (ie, at the time of a split request such as a transfer request or a write) and at the time of a split response. RE3 to RE0 and REM in the normal state are error detection bits of the four PEs 14 and the main memory control unit 15, respectively.T1 and TO are notices of the response time of the main memory control unit 15 to read requests, ACK is the normal response bit of the addressed module. At the time of the split response, each of the four PEs 14 uses two bits (R00 and R01, R10 and R11, etc.) to respond to the cache state control operation and the presence / absence of error detection. The contents of the above-mentioned response code RSP format are all the same as those of the bus of the split transfer protocol according to the conventional technology. Here, the number of PEs 14 is an example, and is determined according to the maximum number of PEs 14 at the time of design.

Next, the operation of the schedule management of the two data buses of the arbiter in FIG. 4 will be described with reference to FIG. In the present invention, the address bus can be arbitrated in the same manner as the bus according to the prior art. In order to manage the schedules for the two data buses, a new 8-bit internal table was set up at Erby. The internal table has four bits for each of the LD and RD sides, and indicates the usage status 5 to 8 cycles ahead. Here, five cycles means the cycle from when the bus right grant is given to the next cycle until the address and command are output from the bus connection device that has requested the pass right (in this embodiment, 2 cycles). ) And the cycle (2 in this embodiment) until a response is output from the bus connection device that is the partner of the bus connection device, and (1 + 2 + 2) is determined. Also 5 cycles 4 cycles (length of the internal table) from 8 to 8 are determined by the maximum value of the number of transfer cycles performed at one time (4 in this embodiment). The two columns, L and R, are determined by the number of data bus systems. These values are not limited to the present embodiment, but are determined by each response cycle, transfer cycle, and number of data bus systems, and the configuration of the internal table changes accordingly. This internal table can be configured using a known means such as a register inside the arbiter. FIG. 6 is a state diagram showing an example of the internal stapling process of the arbiter in the timing chart of FIG. The number in parentheses in the figure indicates the current number of cycles.

At T2, the arbiter has not granted the right to use the data bus to any bus-connected device. In this case, the internal table is the same as the initial state, and all bits are 0.

Since the transfer data length is 4 in the RQ (1) of T1, the arbiter gives the bus connection device (1) the right to use the bus and uses L1 DATA 12 as a data bus for 4 cycles from T8 Decide to let it. Then, the arbiter writes 1 to the L side 4 bits of the internal table at T3, and at T4

GRT (1) # is output.

Since the transfer data length is 4 in RQ (2) of T3, the arbiter gives the bus connection device (2) the right to use the bus and uses R—DATA1 3 as a data bus for 4 cycles from T9 Decide to let it. Then, at T4, 1 is written to the R side 4 bits of the internal table at T4, and at T5

GRT (2) # is output. On the other hand, the L side shifts one bit to the left over time, and writes 0 to the empty bits.

At T5 and T6, both sides are only shifted. Because the data buses on both sides are shown to be used together, the arbiter will not grant any new right to use the data bus to any bus-connected device. Because you can't. The arbiter allows bus-connected devices that want to use the data bus to wait, even if the address bus is free.

When the L side becomes empty at T7, the arbiter gives the right to use the bus to the main memory control unit 15 responding to the read request of T5, and writes 1 to the L side 4 bits of the internal table.

At T8, the R side is empty but there is no request, so the R side is all zeros.

At T9, the arbiter grants the bus connection device (1) the right to use the bus in response to RQ (1) (601) of T8, but since the use of the data bus is one cycle, the arbiter Write 1 to only the leftmost bit on the R side. However, writing of this one bit only can be omitted in actual operation.

As described above, the arbiter can use the partial table to manage the schedules of the two data buses. When there are two or more data buses, schedule management can be performed in the same manner as above. Also, when the time slot transfer protocol is adopted as the transfer protocol, the schedule management of the data buses of a plurality of systems is performed by writing the use of the data bus in response to the response after a certain interval in the internal table as described above. I can. In the case of the time slot transfer protocol, the length of the internal table is determined by the length of the fixed interval.

Another embodiment of the present invention will be described with reference to FIG.

In FIG. 7, one address Z control bus and four data buses are provided. In this figure, reference numeral 70 denotes a system bus according to the present invention, 71 denotes one address / control bus in the system bus 70, and 72, 73, 74 and 75 denote system buses. These are the four data buses (DATA-0 to DATA-3). FIG. 7 is the same as FIG. 1 except for the system bus 70. The PE 14 is, for example, a bus in FIG. This can be realized by connecting the data bus connection LSIs 24 and 25 in the interface controller to the system bus 70 and the data buses respectively.

FIG. 8 is a timing chart showing an example of the protocol of the bus system in FIG. D-0 to D-3 are four data buses (DATA-0 to DATA-3), DSEL is a data bus indication signal expanded to 2 bits, and the other signals are the same as in Fig. 4. is there.

In Fig. 8, as an example, all transfers are performed with a data length of four cycles. In this case, since the address bus has one system and the address transfer has one cycle, and the data bus has four systems and the data transfer has four cycles, the use efficiency of the address bus and all the data buses can be maximized.

At T21, the bus connection devices (0) and (1) output the bus use right request signals using the RQ (0) and RQ (1) (1101 and 1201). The arbiter in the main memory controller 15 performs arbitration, and connects to the bus connection device (0) at T23 using GRT (0) # and to the bus at T 24 using GRT (1) #. Device (1) is granted the right to use the bus (1102 and 1202).

At T23, the arbiter instructs the bus connection device (1) to use D-0 as the data bus by outputting the DSEL signal together with the right to use the bus (1 103). At T24, the arbiter The bus connection device (1) is instructed to use D-1 as the data bus (1203).

At T25, the bus connection device (0) receives GRT (0) # (1 102) and DSEL (1 103), and outputs the address and commands A and C together with the address strobe signal AS # (1 104), and from T27, the bus-connected device (0) outputs data on D-0 for 4 cycles (1 105). At this time, the T 25 command output (1 It is shown that D-0 will be used as an overnight bus.

At T26, the bus connection device (1) is GRT (1) # (1202),

The address and command A and C for DSEL (1 203) are output together with the address strobe signal AS # (1 204), and from T28, the bus connection device (1) outputs data on D-1 for 4 cycles. Output (1 20

5) Yes. At this time, the command output (1204) of T26 indicates that D-1 is used as the data bus.

Next, at T23 and T24, the bus connection devices (2) and (0)

By using RQ (2) and RQ (0), a bus use right request signal is output (1301 and 1401).

The arbiter performs arbitration, and at T25, uses the bus connection device (2) using GRT (2) # and the bus use right at T26 to the bus connection device (0) using GRT (0) #. (1 302 and 1

402) Yes.

At T25, the arbiter instructs the bus connection device (2) to use D-2 as the data bus by outputting the DSEL signal (1303) together with the right to use the bus, and at T26, the arbiter Is instructing the bus connection device (0) to use D-3 as the data bus by outputting the DSEL signal together with the right to use the bus.

The bus connection device (2) receives the GRT (2) # (1302) and the DSEL (1 303), and outputs the address and the commands A and C together with the address strobe signal AS # at T27. (1304), and data is output from D29 on T-2 for 4 cycles (1305). At this time, the command output (1304) of T27 indicates that D-2 is used as the data bus.

The bus connection device (0) is GRT (0) # (1402), DS In response to the EL (1403), at T28, the address and the commands A and C are output together with the address strobe signal AS # (1404), and the data from T30 is output on D-3 for 4 cycles from T30 (1404). 405). At this time, the command output (1404) of T28 indicates that D-3 is used as the data bus. In T30, the bus connection device (0) uses the two data buses D-0 and D-3 to separate data transfer based on two RQs (0) (1 101 and 140 1). It can be seen that the process is performed simultaneously.

In this embodiment, since the arbiter is included in the main memory control unit 15, the main memory control unit 15 does not output a bus request and a grant signal, which are bus-connected devices, to the outside. The transfer request of the control unit 15 is internally processed by the arbiter.

In the present embodiment, the main memory control unit 15 requests a 4-cycle data transfer at T24 in response to a read request from another bus-connected device before T21 (not shown). I have. As a result of the internal processing, the arbiter gives the main memory control unit 15 the right to use the bus at T27, outputs the DSEL signal together with the right to use the bus, and indicates that D-0 is to be used as the data bus ( 1 503). At this time, the arbiter manages the schedule of the four data buses, and since all data buses are used until T30 (1 105, 1205, 1 305, 1 405), the main memory control is performed. The unit 15 is made to wait until T27 to give the right to use the bus, and the main memory control unit 15 performs data transfer from T31.

The main memory control unit 15 outputs the address and the commands A and C together with the address strobe signal AS # (1 504) at T29 in response to being given the right to use the bus, and further outputs the data to D-0. It outputs 4 cycles (1505) from T31. In this case, the command output of T29 (1 504) Shows that D-0 is used as the data bus.

The bus connection device that issued a read request to the main memory control unit 15 before T20 sends a response code RSP (not shown) to the command output (1504). To output.

As described above, in this embodiment, a plurality of data buses operate in cooperation with a single address bus.

In the above two embodiments, the case where the number of data bus systems is 2 and 4 has been described. However, the same can be realized with other numbers of systems. According to the present invention, since there is one address bus, there is also scalability that the number of data bus systems can be easily increased.

Note that the bus system in the present invention refers to a mother board provided with an arbiter and connected to one or more bus connection devices including one or more bus masters, or a mother board configured to be connectable. Point. Further, the bus connection device may be mounted on a card that can be separated from the motherboard, or may be integrated on the motherboard.

In each of the above embodiments, each processor element further includes a plurality of processors. However, the present invention is not limited to this, and any one of the processor elements includes a single processor. Is also good. Further, as described above, according to the present invention, even if a plurality of bus right requests are output from one bus connection device, the transfer can be performed in parallel by selectively using the data bus. The present invention can be applied to any one of the processor elements provided with.

Further, in each of the above embodiments, the processor element and the I / O control unit are exemplified as including the bus master. However, the present invention is not limited thereto, and the present invention is applicable if a plurality of bus masters are provided. is there.

In each of the above embodiments, the address and the data are transferred by the same clock. However, it is also possible to use the source synchronous transfer method using a clock that is twice as fast, for example, by determining the data bus usage period by the number of clock cycles of the address bus. It is.

Further, when a failure occurs in any of the plurality of data buses, the arbiter can easily prohibit the use of the data bus and perform degeneration control.

As described above, according to the present invention, since the address bus is a single system, even if a plurality of data buses are installed in parallel, the control logic does not become complicated and the bus control with higher transfer capability is achieved. A method, a bus control LSI using the method, and a bus system using the method can be obtained.

Further, according to the present invention, since the address bus is a single system, it is possible to obtain a bus system that achieves a higher transfer capability while suppressing an increase in the number of signal pins of the entire bus system.

Further, according to the present invention, since the address bus is one system, it is possible to obtain a bus control LSI that can obtain a higher transfer capability while suppressing an increase in the number of signal pins.

Further, according to the present invention, it is possible to obtain a bus system or a bus control LSI which can obtain a higher transfer capability while suppressing the increase in the number of signal pins because the address bus is a single system. it can.

Further, according to the present invention, since the address bus is a single system, the control logic is not complicated, and the number of signal pins is not increased so much. A system or a bus control LSI can be obtained.

Further, according to the present invention, since there is only one system of the address bus, it is possible to obtain a system or a bus control LSI that achieves higher transfer capability while ensuring high reliability without complicating the control logic. Further, according to the present invention, since the address bus is one system, the control logic is not complicated, the number of development steps is short, and a bus system or a bus control LSI which can obtain higher transfer capability can be obtained. Industrial applicability

According to the present invention, a bus system having a high transfer capability can be obtained without requiring complicated control logic. Thus, while maintaining a high transfer capacity, the overall bus system, it can be kept rather small, increase in the number of signal pins of the bus control LSI, power consumption can be suppressed prices, the number of development steps _c

Claims

The scope of the claims

1.

An address / data separation type information processing device bus system for an information processing device, comprising: one address bus; and a plurality of data buses cooperating with the address bus.

2.

The bus system for an information processing device according to claim 1, wherein the arbiter for arbitrating the bus use right has means for designating a data bus to be used when granting the bus use right to the bus connection device. A bus system for information processing equipment, which is a distinctive feature.

3.

3. The bus system for an information processing device according to claim 1 or 2, wherein a read transfer is performed by dividing the request into a request and a response. A bus system for an information processing device, which is controlled.

Four .

3. The bus system for an information processing device according to claim 1 or 2, wherein an interval between a request and a response of a lead transfer is fixed to a fixed time, and controlled by a time slot transfer protocol. A bus system for an information processing device characterized by being performed.

Five . 5. The bus system for an information processing device according to claim 1, wherein the one address bus and the plurality of data buses are controlled in synchronization with a same clock. For information processing devices

6.

The information processing device bus system according to any one of claims 1 to 5, wherein a main storage control unit is connected to the information processing device bus; An arbiter for arbitrating the right to use is provided in the main memory control unit.

7.

The bus system for an information processing device according to any one of claims 1 to 6, wherein when a failure is detected in some of the plurality of data buses, a failure occurs. A bus system for an information processing device, characterized in that it has a degeneration function and operates using only a data bus of a normal system without using a data bus of a system in which is detected.

8.

An information processing apparatus comprising the information processing apparatus bus system according to any one of claims 1 to 7.

9.

A bus connection device that is connected to an information processing device bus system that is an address-data separated type and has a plurality of data buses, and is used to determine the data bus used when outputting an address to the address bus. To A bus connection device for an information processing apparatus, comprising:

Ten .

10. The bus connection device for an information processing device according to claim 9, further comprising means for notifying a transfer data length to an arbiter when a bus use right is requested.

1 1.

An address-separated type aviator used in an information processing device bus system having a plurality of data buses, connected to the information processing device bus system and requesting a right to use the bus. Arbiter _c for use in a bus system for an information processing device, which includes means for designating a data bus to be used when granting a bus use right to a bus connecting device to be used.

1 2.

12. An apparatus for use in the bus system for an information processing apparatus according to claim 11, wherein the use state of said plurality of data buses is managed in order to specify said data bus to be used. An arbiter for use in a bus system for an information processing device, characterized by comprising means.

13 .

13. A bus connection device for an information processing device, comprising an arbiter used in the bus system for an information processing device according to claim 11 or 12, wherein the device operates as a bus slave.

14 . 14. The bus connection device for an information processing device, wherein the bus connection device according to claim 13 is a main storage control unit.