JPH0381855A - Data transfer equipment - Google Patents

Abstract

PURPOSE:To improve the utilizing efficiency of a data bus by dynamically allocating data buses by means of data bus busy signal lines indicating the utilizing states of respective data buses and a priority order determining circuit. CONSTITUTION:It is supposed that a data transfer circuit 22 executes data transfer with another data transfer circuit through a data bus 20. The priority order determining part 28 obtains which bus out of plural data buses 20 is used from the corresponding data bus busy signal line 21. The circuit 28 determines which data bus is to be used out of unused data buses based upon a previously determined rule. The information is transmitted to a data bus connecting circuit 24 as a data bus number through a data bus selecting signal line 30. The circuit 24 connects an internal data bus 26 to one of the buses 20 in accordance with the data bus number transmitted through the signal line 30. Thus, an unused data bus is dynamically selected b the signal line 21 and the circuit 28 and can be used by connecting the selected data bus with the internal data bus 26.

Description

DETAILED DESCRIPTION OF THE INVENTION FIELD OF INDUSTRIAL APPLICATION The present invention relates to a data transfer device that utilizes information on the availability of a plurality of data buses to effectively utilize the data buses.

2. Description of the Related Art Conventionally, data transfer speed has been increased by constructing a data transfer device using a plurality of data buses.

A conventional data transfer device will be described below with reference to FIG.

FIG. 3 is a diagram showing the configuration of a conventional data transfer device.

, In FIG. 3, 1 is a plurality of data buses, 2゜3.
12 is a data transfer circuit that sends and receives transfer data to and from the data bus 1; 6 and 7 are internal data buses of the data transfer circuits 2 and 3, respectively; and 4 and 5 are a plurality of data nodes in the data transfer circuits 2 and 3, respectively. Data bus connection circuits 8 and 9 are used to instruct the data bus connection circuit 4.5 to connect the internal transfer bus 6.7 to which of the data buses 1. selection register, 1
0°11 is a data bus selection signal line for transmitting the values of the data bus selection registers 8 and 9 to the data bus connection circuits 4 and 5.

The operation of the above configuration will be explained below.

Consider a case where the data transfer circuit 2 transfers data to another data transfer circuit via the data bus 1.

First, data bus selection register 8 in data transfer circuit 2
Set which bus of the plurality of data buses 1 is to be used. For example, assume that data bus 1 is made up of three data buses, each numbered 0°1.20. When transferring data using the first data bus, 1 is set in the data bus selection register 8.

The value set in the data bus selection register 8 is transmitted to the data bus connection circuit 4 through the data bus selection signal line 10. The data bus connection circuit 4 connects the data bus numbered from the data bus 1 indicated by the data bus selection signal line 10 to the internal data bus 6. Thereby, the data transfer circuit 2 is connected to one specific bus among the data buses 1.

When data is transferred between the data transfer circuit 2 and the data transfer circuit 30 using the second data bus of the data buses 1, 2 is set in each of the data bus selection registers 8.9. As a result, the internal data buses 6 and 7 of each data transfer circuit 2 and 3 are connected to the second bus of the data bus 1.

Note that setting of the data bus selection register is performed by, for example, a processor that controls the present transfer device.

Problems to be Solved by the Invention However, in the above-described configuration, there is no mechanism for monitoring the usage status of the data bus 1, so it is not possible to dynamically allocate the data bus 1 according to the usage status. In this configuration, the data bus is normally allocated statically. For example, bus number 0 of data bus 1 is used for transfer from data transfer circuit 2 to data transfer circuit 3, and bus number 1 is used for transfer from data transfer circuit 3 to data transfer circuit 12. While statically allocating data buses in this manner simplifies control, it also reduces data bus usage efficiency.

The present invention solves the above problem and enables dynamic allocation of data buses.

Means for Solving the Problems The present invention achieves the above object by providing a signal line that indicates the usage status of a data bus and a priority determining circuit that determines which unused data bus is to be used. It is something to do.

Effect of the Invention With the above configuration, the present invention can monitor the usage status of the data bus and dynamically allocate the data bus.

Embodiment Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a data transfer device in a first embodiment of the invention.

In FIG. 1, 20 is a plurality of data buses; 21 is a data bus busy signal line that corresponds one-to-one to each bus of the plurality of data buses 20 and indicates whether the corresponding bus is currently in use; 22 and 23 are data transfer circuits that transmit and receive transfer data to and from the data bus 20; 26 and 27 are internal data buses of the data transfer circuits 22 and 23, respectively;
24.25 are data bus connection circuits that connect an internal data bus 26.27 to one of the plurality of data buses 20 in the data/event transfer circuits 22.23; 28.2;
9 is a priority determining circuit for selecting which of the data buses I to connect the internal transfer bus 26 and 27 to from the data bus busy signal line in the data bus connection circuits 24 and 25;
30.31 is a data bus selection signal line for transmitting the value of the priority determination circuit 28.29 to the data bus connection circuit 24.25.

The operation of the above configuration will be explained below.

First, consider a case where the data transfer circuit 22 transfers data to another data transfer circuit via the data bus 20. The priority determination circuit 28 determines which bus of the plurality of data buses 20 is being used based on the data bus busy signal line 21.
Get from. The priority determining circuit 28 determines which data bus to use from among the unused data buses according to predetermined rules. This information is transmitted to the data bus connection circuit 24 via the data bus selection signal line 30 using the data bus number. In the data bus connection circuit 24,
The internal data bus 26 is selected from the data bus 20 according to the data bus number conveyed by the data bus selection signal 30.
Connect to one of them.

Next, consider a case where data is transferred between the data transfer circuit 22 and the data transfer circuit 23 using the data bus 20 as a specific example. It is assumed that the data bus 20 consists of three data buses, each numbered 0°1.2. Let us consider a case where the number 0 data bus among the three data buses is in use. The priority determining circuits 28 and 29 select the data bus with the lowest number among the unused data buses. That is, in this case, the priority order determining circuits 28 and 29 select the No. 1 data bus among the data buses 20. This information is transmitted to the data bus connection circuit 24.2 through the data bus selection signal line 30.31.
5, and internal data buses 26 and 27 are connected to data bus number 2001.

As described above, according to this embodiment, unused data buses can be dynamically selected by the data bus busy signal line 21 and the priority order determining circuits 28 and 29, and used by connecting them to each other.

Next, a second embodiment of the present invention will be described.

FIG. 2 is a block diagram of a data transfer device according to a second embodiment of the present invention.

In FIG. 2, 40 is a data bus consisting of multiple lines;
1 corresponds one-to-one to each data bus of the plurality of data buses 40, and indicates whether the corresponding bus is currently in use.A data bus busy signal line 42 indicates whether or not the corresponding bus is currently in use, according to the value of the data bus busy signal line 41. A priority determining circuit selects which data bus to use from unused data buses among the buses 40; 43 is a data bus selection signal line that conveys the number of the data bus selected by the priority determining circuit 42; , 45 are data transfer circuits that transmit and receive transfer data to and from the data bus 40, 46 and 47 are data transfer circuits Kaede and 45's internal data bus, respectively, 49 are data transfer circuits a, and in 45, data bus selection signal lines. This is a data bus connection circuit that connects one internal data bus 46 and 47 of a plurality of data buses 40 according to the value of 43.

The operation of the above configuration will be explained below.

First, consider a case where the data transfer circuit 44 transfers data to another data transfer circuit via the data bus 40. The priority determination circuit 42 determines which bus of the plurality of data buses 40 is being used based on the data bus busy signal line 41.
Get from. The priority determining circuit 42 determines which data bus to use from among unused data buses according to predetermined rules. This information is sent to each data transfer circuit a via the data bus selection signal line 43 as a data bus number.

45 will be informed. In the case of the data transfer circuit 44, the data bus selection signal line 43 is connected to the data bus connection circuit 48, and the data bus connection circuit 48 selects internal data according to the data bus number transmitted by the data bus selection signal line 40. Bus 46 is connected to one of data buses 40.

Next, as a specific example, a case where data is transferred between the data transfer circuit and the data transfer circuit 450 using the data bus 40 will be considered. It is assumed that the data bus 40 consists of three data buses, each numbered O11.20. , among the three data buses, if the data bus No. 0 is in use, the priority determination circuit 42 selects the data bus with the lowest number among the unused data buses. The determining circuit 42 selects the first data bus from among the data buses 40. This information is transmitted to the data bus connection circuits 49 of each data bus transfer circuit 45 through the data bus selection signal line 43. The data bus connection circuit O, 49 selects the internal data bus 46°4 based on the information on the data bus selection signal line 43.
As described above, according to this embodiment, an unused data bus is dynamically selected by the data bus busy signal line 41 and the priority determination circuit 42, and Can be connected and used.

Effects of the Invention As described above, the present invention can dynamically allocate data buses by using a data bus busy signal line that indicates the usage status of each of a plurality of data buses and a priority determination circuit. The data bus usage efficiency can be improved, and the effect is significant.

[Brief explanation of drawings]

FIG. 1 and FIG. 2 respectively show the first embodiment of the present invention. A block wiring diagram of a data transfer device in the second embodiment, and FIG. 3 is a block wiring diagram of a conventional data transfer device. 20... Data bus, 21... Data bus busy signal line, 22, 23... Data transfer circuit, 24.25.
...Data bus connection circuit, 28.29...Data bus connection circuit, 4o...Data bus, 41...Data bus busy signal line, 42...Priority selection circuit, 43.
...Data bus selection signal line, play. 45...Data transfer circuit, edict, 49...Data bus connection circuit.

Claims (2)

[Claims] (1) A plurality of data buses, the same number of data bus busy signal lines as the data buses indicating whether or not each data bus is transferring data, and data to be transferred to each other via the data buses. a transfer circuit, the data transfer circuit selects a data bus that is not undergoing transfer among the plurality of data buses based on the signal of the data bus busy signal line, and a priority determination circuit that selects and determines only one data bus according to the priority determined by the priority determination circuit; and a data bus that connects the other side and its own internal data bus via the data bus based on the selection result of the priority determination circuit. A data transfer device having a connection circuit. (2) a plurality of data buses, the same number of data bus busy signal lines as the data buses indicating whether or not each of the data buses is performing transfer; a priority determination circuit that selects a data bus that is not performing transfer among the main data buses, and selects and determines the only data bus according to a predetermined priority order of that data bus; , a plurality of data transfer circuits each having a data bus connection circuit that connects the other party and its own internal data bus via the data bus based on the data bus selection signal selected and determined by the priority determination circuit; data transfer equipment.