JP4691899B2 - Semiconductor integrated circuit - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit capable of acquiring correct data by adjusting the timing of reading data from an external memory.

  In a system LSI that requires an external memory, a margin is usually given at the design stage so that the input / output timing between the system LSI and the external memory matches, but in recent years, the operation speed has been increased. When there is an unexpected delay on the PAD and board wiring, the read data is not always output at a desired timing during reading, and correct data may not be acquired.

For example, Document 1 provides a mode for analyzing whether a write error or a read error is separated, in addition to the normal mode for actual use, in case an error occurs during actual use. In the analysis mode, “read” and “write” modes are provided at the speed “low speed” for reliable operation and the speed “high speed” for actual use, respectively. Perform “low-speed write” → “high-speed read”, “high-speed write” → “low-speed read”, increase the clock delay amount until the write data and read data match in each operation, and register the delay amount when they match With the above operation, the clock is delayed until the timing at which correct data can be read and written, and correct data is read and written.
Japanese Patent Laid-Open No. 11-328961

  However, since the process of delay adjusting the clock is repeated until the written data matches the read data, there is a problem that the processing amount in the analysis mode is large. In addition, it takes time when the amount of processing is large, but when used in an environment where the amount of delay changes frequently, it is often necessary to switch from the normal mode to the analysis mode to adjust the read / write timing, resulting in a lot of dead time. Therefore, there was a risk of squeezing normal operation.

In order to solve the above problems, a memory interface that enables access to an external memory, a register group that holds adjustment latency, a read buffer that holds data read from a latency investigation address of the external memory, and A comparison circuit that compares the data held in the read buffer with the latency investigation data, and a sequencer that conducts a latency investigation based on the result of the comparison circuit, and has a built-in memory controller that controls the external memory through the memory interface In the semiconductor integrated circuit, after writing the latency investigation data to the latency examination address of the external memory, the sequencer starts counting after issuing a latency investigation read command, and the comparison circuit The latency buffer is compared with the latency check data, and the sequencer count value at the time of coincidence is held in the register as the adjustment latency, and in the normal operation, the wait time for the adjustment latency is issued after the read command is issued. A latency adjustment operation for handling data as valid data is performed every predetermined time .

  The latency investigation data is two or more pieces of data, and the read buffers are used in the same number as the latency investigation data, and the data are continuously compared during the latency investigation operation.

It has a register for storing the latency check data, and after writing the data to two consecutive addresses in the external memory, the latency check operation is performed.
The latency check operation is performed after writing the inverted latency check data for each data bit in the first address and writing the inverted data in the second address relative to the first address. And

It has a register for storing the latency investigation address, reads out data at the address during the latency investigation operation, and implements the latency investigation operation.
The semiconductor integrated circuit according to claim 1,
A latency investigation operation is executed every predetermined time.

  With the configuration described above, a cycle in which data is taken into the CPU from the issue of the read command is a timing at which correct data can be read regardless of whether there is a delay or not. Further, even when a delay variation occurs during use, the data latency is periodically corrected, so that it is always time to read correct data.

  In addition, the delay that varies depending on the usage conditions of the memory and the board has to be suppressed within one cycle. However, it is not necessary to be aware of the restriction, and the board can be manufactured easily.

  Compared to the prior art, there are the following advantages. Incorporating into normal operation adjusts the latency that correct data is always read in the latest state even if there is a delay variation. In addition, since the amount of processing required for one delay adjustment is small, frequent adjustment is possible.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  The semiconductor integrated circuit 1 includes a memory I / F 5 that enables a write operation or a read operation to the external memory 2, a CPU 2, and a memory controller 4 that controls access to the memory. In FIG. 1, the CPU 2 incorporated in the semiconductor integrated circuit 1 may be externally attached.

  The memory controller 4 issues a command issuance 6 for issuing a read command and a write command, a first read buffer 7 and a second read buffer 8 for holding read data, and values stored in the latency investigation data register. Comparing circuit 9 that compares the data held in read buffers 7 and 8, a sequencer 10 that starts counting at the same time when a read command is issued, and a register group 11 that stores latency investigation data and addresses and adjustment latencies. The In the embodiment of FIG. 1, the number of read buffers is two, but two or more may be used. However, it is necessary to prepare the same number of latency investigation addresses and data as there are read buffers.

  FIG. 2 is a flowchart of the latency investigation operation. Before performing the operation for adjusting the latency, the latency from when the read command is issued until the head of the data arrives is examined.

The latency investigation data is written to the first address and the second address. These two addresses need not be contiguous, but are desirably contiguous. ... Are written to the first address, and data that becomes the inverted 1010... Of the data written to the first address is written to the second address. The data input to the first address and the second address must be inverted for all bits, but the reverse is also possible. It should be noted that, as the latency investigation address, an arbitrary address that is not overwritten by normal operation is designated according to the system to be used. Further, the write operation is performed only once before the latency is investigated, and it is not necessary to perform the write operation after that. (Fig. 2, S1)
In order to investigate the latency of data, a read command is continuously issued to the first address and the second address. As soon as the command is issued, the sequencer starts counting cycles. (Fig. 2, S2)
In response to the read command, two data read from the external memory arrive at the read buffer. The comparison circuit compares the data arriving at the first read buffer and the second read buffer with the latency investigation data read from the first address and the second address. When the data in the read buffer is shifted and the two data match, the cycle count counted by the sequencer is stopped and the value is stored in the adjustment latency register. If the values do not match within a predetermined time due to a failure of the external memory or the like, the value of the adjustment latency register is not overwritten, and the latency check operation is terminated. (Fig. 2, S3-S5)
FIG. 3 is a flowchart of the latency adjustment operation. The latency adjustment operation is included in the normal operation of the system.

After the system is turned on, initial operations such as system reset are performed. (Fig. 3, S11)
After the initial operation, the latency investigation operation (FIG. 2) is performed to obtain the adjustment latency. (Fig. 3, S12)
A normal operation calculation process is started, a read command is issued, data in the external memory is read, and at the same time, the sequencer starts counting the number of cycles. (Fig. 3, S13)
The adjustment latency stored in the register at the time of the latency investigation operation is read, and when the number of cycles counted by the sequencer reaches that value, a signal indicating that the data read from the external memory is valid is issued. With this signal, calculation is started on the read data. (Fig. 3, S14 to S16)
Over time, the delay on the PAD and the board wiring may fluctuate due to external factors such as ambient temperature. Therefore, the latency check operation is re-executed every predetermined time, and the correct data timing is always maintained. (Fig. 3, S17-S18)

  The semiconductor integrated circuit of the present invention is useful as a circuit that can read correct data from an external memory during high-speed operation.

1 is a configuration diagram showing a semiconductor integrated circuit according to a first embodiment of the present invention. Flow chart explaining latency investigation operation Flowchart explaining latency adjustment operation

Explanation of symbols

1. 1. Semiconductor integrated circuit External memory CPU
4). 4. Memory controller Memory I / F
6). Issue command 7. First read buffer 8. Second read buffer 9. Comparison circuit 10. Sequencer 11. Register group

Claims (4)

A memory interface that allows access to external memory;
A register group for holding latency for adjustment; a read buffer for holding data read from a latency check address in the external memory; a comparison circuit for comparing data held in the read buffer and latency check data; and the comparison A sequencer that performs a latency investigation based on a circuit result, and a memory controller that controls the external memory through the memory interface,
After writing the latency investigation data to the latency investigation address of the external memory,
After the read command for latency check is issued, the sequencer starts counting, the read circuit and the latency check data are compared by the comparison circuit, and the count value of the sequencer at the time of coincidence is set as the adjustment latency in the register. The latency investigation operation to be held is performed every predetermined time ,
A semiconductor integrated circuit characterized by performing a latency adjustment operation in which data waiting for the adjustment latency after issuing a read command during normal operation is treated as valid data. The semiconductor integrated circuit according to claim 1,
The latency investigation data is two or more pieces of data, the same number of read buffers are used as the latency investigation data, and the data is continuously compared during the latency investigation operation. . The semiconductor integrated circuit according to claim 2.
A semiconductor integrated circuit having a register for storing the latency checking data, and writing the data to two consecutive addresses in an external memory, and then performing a latency checking operation. The semiconductor integrated circuit according to claim 2.
The latency check operation is performed after writing the inverted latency check data for each data bit in the first address and writing the inverted data in the second address relative to the first address. A semiconductor integrated circuit.

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