JP2003044367A - Data processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data processor capable of accessing memory data even in a period in which compensation data is outputted from a memory and which requires a small amount of time for ECC compensation. SOLUTION: The data processor is provided with an external user memory 1, an internal user memory 2, a CPU 4, a data bus 5, an address bus 6 to be required for data access to the external user memory 1, the internal user memory 2 and the CPU 4, a data port 7 and an address port 8 to be required for access to the external user memory 1. The CPU 4 is provided with an IFU 3 having first to fifth registers (15, 16, 17, 18, 19), an ECC compensation circuit 11 and an ECC processing selection selector 12 and an instruction register 14.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device, and more particularly to a data processing device including ECC correction processing.

[0002]

2. Description of the Related Art In recent years, it is well known that a data processing device for accessing memory data from an external user memory or an internal user memory and processing the data is used in a personal computer or a communication terminal.

Such a prior art data processing device is
For example, it is disclosed in Japanese Patent Laid-Open No. 7-56758.

FIG. 10 shows an example of the configuration of such a conventional data processing apparatus, and FIG. 11 shows a timing chart of the operation example.

Referring to FIG. 10, the structure of a conventional data processing apparatus will be described.

As shown in FIG. 10, a conventional data processing apparatus includes an external user memory 1 having an ECC correction circuit 109, an internal user memory 2 having an ECC correction circuit 110, and an instruction fetch unit 3 ( In the following, abbreviated as IFU) Built-in CPU 4, external user memory 1 or internal user memory 2, and data bus 5 and address bus 6 required for data access of CPU 4.
And a data port 7 and an address port 8 necessary for accessing the external user memory.

Next, the operation of the conventional data processing apparatus will be described with reference to FIG.

First, in the conventional data processing apparatus, either the external user memory 1 or the internal user memory 2 is designated by the address signal sent through the address bus 6.

Next, the addressed external user memory 1 or internal user memory 2 is corrected by the ECC correction circuit 109 provided in the external user memory 1 or the ECC circuit 110 provided in the internal user memory 2 to correct the memory data. Detect.

The ECC correction data of the ECC correction circuit 109 provided in the external user memory 1 is output to the data bus 5 via the data port 7. Further, the ECC correction data of the ECC correction circuit 110 provided in the internal user memory 2 is output to the data bus 5.

Next, the ECC correction data output to the data bus 5 is set in the 1st register 15 of the IFU 3 incorporated in the CPU 4.

Next, the set ECC correction data is
As shown in FIG. 11, as the machine cycle progresses, 1
Set 16 from st register 15 to 2nd register, 3rd register 17, 4th register 18, 5th
It is sequentially set in the register 19.

Finally, the ECC correction data set in the final stage 5th register 19 is output to the instruction decoder 14, and the CPU 4 executes the instruction.

Here, the final stage register (nth
The example in which the register) 20 is the 5th register 19 has been described.

[0015]

However, in the prior art, the data processing device for accessing the memory data from the external user memory 1 or the internal user memory 2 to process the data is an ECC provided in the external user memory 1. Since the correction circuit 109 or the ECC correction circuit 110 provided in the internal user memory 2 performs the correction detection and the correction data is output from the memory, the memory data cannot be accessed and the time required for the ECC correction is large. There is a limit to how fast the memory access cycle can be.

Further, high performance and low price of the data processing device are important demands from the market, and a data processing device which does not require the ECC correction circuit in the external user memory, the internal user memory and the data bus is required. Met.
That is, the first problem is that when the memory data is accessed from the external user memory 1 or the internal user memory 2, the ECC correction circuit 109 provided in the external user memory 1 or the ECC correction circuit 110 provided in the internal user memory 2 is accessed. Since the ECC correction detection is performed during the limited access period of the machine cycle of the data bus 5, the memory access period is overwhelmed with the ECC correction time, and it is impossible to access with the access time of the original memory.

A second problem is that the access period of the memory data is limited if the ECC correction circuit is added to the EPU as in the data processing device described in Japanese Patent Laid-Open No. 7-56758. When correction is performed, the speed becomes severe during the ECC correction time during the read period. In addition, since the memory data and the check bit data are required for the correction detection, the number of data buses becomes large.

For example, when there are 8 memory data buses, 4 check bit data buses are required. When there are 16 memory data buses, 5 check bit data are required, and 32 memory data buses are required. In this case, the check bit data requires 6 buses. Therefore, when this data processing device is configured by a semiconductor integrated circuit, the chip area of the semiconductor integrated circuit becomes large.

A third problem is that if the number of ECC correction circuits 110 provided in the internal user memory 2 increases, the chip area of the semiconductor integrated circuit increases when the data processing device is formed of a semiconductor integrated circuit.

The fourth problem is that the ECC correction circuit 109 provided in the external user memory 1 and the internal user memory 2 are
The function switching between “use and not use” of the correction detection of the ECC correction circuit 110 provided in the above is performed by the ECC correction circuit 109 provided in the external user memory 1 and the ECC correction circuit 110 provided in the internal user memory 2, respectively. Select control must be set.

The fifth problem is that when accessing memory data in the external user memory 1, the external user memory 1
Must use expensive memory with ECC correction circuit,
Data reliability cannot be guaranteed.

Therefore, in view of the above problems, the present invention is to provide a data processing device which solves these problems.

[0023]

A data processing apparatus according to the present invention comprises an external user memory, an internal user memory, and 1s.
t register to nth register (n is a positive integer), E
C including an IFU having a CC correction circuit and an ECC processing selection selector, and an instruction register
A data bus and an address bus required for data access between the CPU, the external user memory and the internal user memory, and the CPU; and a data port and an address port required for access to the external user memory. The memory data output to the bus is set in the 1st register of the IFU built in the CPU, and the memory data set in the 1st register is shifted from the 1st register to the 2nd register in a predetermined machine cycle. At the same time,
Check bit data written in the external user memory or the internal user memory is set in the 1st register, and the memory data set in the 2nd register is set to 1
Check bit data set in st register and E
The CC correction circuit performs correction detection and outputs it to the ECC process selection selector. The ECC process selection selector receives the ECC correction data output from the ECC correction circuit and the memory data set in the 2nd register, and outputs it according to the ECC selection signal. , Any of the data is set in the 3rd register.

Further, the data processing apparatus of the present invention has a function of temporarily storing data, and is provided with a secondary IFU for sequentially storing ECC-processed data in the data output section of the ECC processing selection selector.

Furthermore, the data processing device of the present invention is
This is a configuration in which a secondary IFU and a tertiary IFU for holding ECC-corrected data, a write selection circuit, and a data selector are provided in the data output section of the ECC selection selector.

Further, the data processing device of the present invention has an ECC
The data output from the process selection selector has a configuration in which the write selection circuit executes the selection of writing to the secondary IFU, the tertiary IFU or directly outputting to the data selector by judging the content of the instruction.

Furthermore, the data processing device of the present invention is
When the interrupt request 1 occurs, the correction data A that does not branch (NO) in the branch 1 is stored in the secondary IFU, and the correction data B that branches in the branch 1 (YES) is stored in the tertiary IFU. The correction data B is directly output from the write selection circuit to the data selector, the necessary correction data is selected by the data selector, and stored in the third, fourth, and fifth registers sequentially.

Further, the data processor of the present invention does not branch at branch 2 when an interrupt of interrupt request 1 occurs and an interrupt request of interrupt request 2 occurs (N
O) The correction data B has already been stored in the tertiary IFU, so branching is performed at branch 2 (YES).
The correction data A written in the secondary IFU is erased by sequentially storing in the FU, and at the same time, the correction data C is directly output from the write selection circuit to the data selector, and the necessary correction data is selected by the data selector. , The third, fourth, and fifth registers are sequentially stored.

Further, in the data processor of the present invention, when the interrupt of the interrupt request 2 is generated and further the interrupt of the interrupt request n is generated, the correction data C which is not branched at the branch n (NO) is already the secondary IFU. The correction data n branched at the branch n (YES) are sequentially stored in the tertiary IFU, and the correction data B written in the tertiary IFU is stored.
Is erased, and at the same time, the correction data n is directly output from the write selection circuit to the data selector, the necessary correction data is selected by the data selector, and sequentially stored in the third, fourth, and fifth registers.

Further, in the data processor of the present invention, when the interrupt request 1 is generated and further the interrupt request 2 is generated and there is no interrupt request n, the correction data A of the secondary IFU is not erased and the branch is performed. The (YES) correction data C branched at 2 is directly output from the write selection circuit to the data selector, and the necessary correction data is selected by the data selector.
In this configuration, the data is sequentially stored in the third, fourth and fifth registers.

Further, the data processing apparatus of the present invention includes a DMA (dynamic memory access) for the external user memory and the internal user memory, and a DM for controlling the DMA.
This is a configuration including an A controller.

Further, the data processing device of the present invention is configured such that the data output section of the CPU is provided with an ECC check bit generation circuit and a data selector.

Furthermore, the data processing device of the present invention is
In this configuration, an ECC check bit generation circuit is provided on the input side of the internal user memory.

[0034]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described in detail below with reference to the drawings.

The feature of the present invention is that the ECC correction circuit provided in the plurality of external user memories and the plurality of internal user memories is built in the CPU, and the ECC correction circuits are collectively operated.
This is a data processing device that performs C correction. With this device, when the data processing device is configured by a semiconductor integrated circuit, the chip area of the semiconductor integrated circuit can be reduced, and high-speed and highly reliable memory access can be realized even if an inexpensive memory is used. .

FIG. 1 is a block diagram of a data processing apparatus according to the first embodiment of the present invention. Referring to FIG. 1, a data processing apparatus according to a first embodiment of the present invention is configured to access data between an external user memory 1, an internal user memory 2, a CPU 4, an external user memory 1, an internal user memory 2 and a CPU 4. A data bus 5 and an address bus 6 required for the above, and a data port 7 and an address port 8 required for accessing the external user memory 1.

Further, the CPU 4 of the data processing device according to the first embodiment of the present invention includes the 1st register to the 5th register (15, 16, 17, 18, 19), the ECC correction circuit 11 and the ECC process selection selector 12. The IFU 3 and the instruction register 14 are provided.

In the following description of each embodiment, only one external user memory 1 and one internal user memory 2 are shown, but in reality it is shown that there are one or more. .

In the IFU 3, a plurality of registers actually exist, but in the following description of each embodiment, up to the 5th register is assumed for convenience of description.

Next, the operation of the data processing apparatus according to the first embodiment of the present invention will be described with reference to FIG.

In the data processing apparatus according to the first embodiment of the present invention, first, an address signal sent via the address bus 6 specifies one of the external user memory 1 and the internal user memory 2.

Next, the memory data at the designated address is output to the data bus 5.

Then, the memory data output to the data bus 5 is stored in the 1st of the IFU 3 incorporated in the CPU 4.
It is set in the register 15.

Further, the memory data set in the 1st register 15 is shifted from the 1st register to the 2nd register 16 in the machine cycle 2 as shown in FIG. At that time, the check bit data written in the external user memory 1 or the internal user memory 2 is set in the 1st register 15 in advance.

Next, the memory data set in the 2nd register 16 is subjected to correction detection by the check bit data set in the 1st register 15 and the ECC correction circuit 11, and is output to the ECC process selection selector 12.

Next, the ECC processing selection selector 12 outputs E
ECC correction data output from the CC correction circuit 11 and 2
The memory data set in the nd register 16 is received, and one of the data is set in the 3rd register 17 by the ECC selection signal 13.

Finally, the output of the ECC process selection register 12 set in the 3rd register 17 is set in the 4th register 18 and the 5th register 19 as the machine cycle progresses, and the instruction register 1
4 and the CPU 4 executes the instruction.

Next, a data processing apparatus according to the second embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 3 is a block diagram of a data processing device according to the second embodiment of the present invention. Referring to FIG. 3, the data processing device according to the second embodiment of the present invention is the first embodiment of the present invention.
In addition to the data processing device of the embodiment,
Is provided in the data output section of the ECC selection selector 12.
The secondary IFU has a function of temporarily storing data and a function of sequentially storing ECC-processed data.

Next, the operation of the data processing device according to the second embodiment of the present invention will be described.

First, in the data processing apparatus according to the second embodiment of the present invention, either the external user memory 1 or the internal user memory 2 is designated by the address signal sent via the address bus 6.

Next, the memory data at the designated address in the external user memory 1 or the internal user memory 2 is output to the data bus 5.

Further, the memory data output to the data bus 5 is set in the 1st register of the IFU 3 incorporated in the CPU 4.

Then, the memory data set in the 1st register is shifted from the 1st register to the 2nd register in the machine cycle 2 as shown in FIG.

At that time, the external user memory 1 or
The check bit data written in the internal user memory 2 is set in the 1st register.

Next, the memory data set in the 2nd register is subjected to correction detection by the check bit data set in the 1st register and the ECC correction circuit 11,
It is output to the ECC processing selection selector 12.

Further, the ECC processing selection selector 12 is
The ECC correction data output from the ECC correction circuit 11 and the memory data set in the 2nd register are received, and the ECC correction data or the memory data in the 2nd register is transferred to the ECC selection selector 12 in FIG. 2 in sequence as shown in the chart
It will be accumulated in the next IFU at any time.

When the data is read from the secondary IFU, it is output to the 3rd register every machine cycle as shown in the timing chart of FIG.
The data is shifted to the h and 5th registers and output to the instruction register 14.

From the above description, according to the data processing device of the second embodiment of the present invention, the data subjected to the ECC correction processing is sequentially stored in the secondary IFU so that the ECC correction processing can be performed as necessary. You can read the data already
CPU instructions can be executed without depending on the ECC processing.

Next, a data processing device according to a third embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 4 is a block diagram of a data processing apparatus according to the third embodiment of the present invention, and FIG. 8 shows a flowchart of data processing.

Referring to FIG. 4, the data processing device according to the third embodiment of the present invention is the same as the data processing device according to the first embodiment of the present invention, except that the secondary IFU 43 and the tertiary IF
U44 and write selection circuit 42 are connected to the ECC selection selector 12
It is provided in the data output part of and the data selector 45 is added.

The secondary IFU 43 and the tertiary IFU 44 are
It has a function of holding the data subjected to the ECC correction processing.

Next, the operation of the data processing apparatus according to the third embodiment of the present invention will be described.

In the data processing apparatus according to the third embodiment of the present invention, first, an address signal sent via the address bus 6 specifies one of the addresses of the external user memory 1 and the internal user memory 2.

Next, the memory data at the designated address is output to the data bus 5.

Then, the memory data output to the data bus 5 is stored in the 1st of the IFU 3 incorporated in the CPU 4.
It is set in the register.

Further, the memory data set in the 1st register is shifted from the 1st register to the 2nd register in the machine cycle 2 as shown in FIG. At that time, the check bit data written in the external user memory 1 or the internal user memory 2 in advance is set to 1st.
Set in register.

Next, the memory data set in the 2nd register is subjected to correction detection by the check bit data set in the 1st register and the ECC correction circuit 11,
It is output to the ECC processing selection selector 12.

Next, the ECC processing selection selector 12 selects E
ECC correction data output from the CC correction circuit 11 and 2
The memory data set in the nd register is received, one of the data is selected by the ECC selection signal 13, and the selected data is output from the ECC processing selection selector 12.

Next, the data output from the ECC process selection selector 12 is transferred to the secondary IF in the write selection circuit 42.
U, write to tertiary IFU or direct data selector 45
The selection of whether to output to is executed by judging the content of the instruction.

This processing will be described in detail with reference to FIGS. 4 and 8.

First, (a) when the interrupt request 1 is generated, the correction data A not branched at the branch 1 (NO) is stored in the secondary IFU, and the correction data B branched at the branch 1 (YES) is 3 It is stored in the next IFU.

At the same time, the correction data B is written in the selection circuit 4
2 directly outputs to the data selector 45, and the necessary correction data is selected by the data selector 45.
Sequentially store in registers.

Next, (b) when the interrupt request 1 and the interrupt request 2 are further generated, the correction data B not branched in the branch 2 (NO) is already stored in the tertiary IFU. Therefore, branch at branch 2 (Y
(ES) The correction data C is sequentially stored in the secondary IFU (the correction data A written in the secondary IFU is erased).

At the same time, the correction data C is written into the write selection circuit 4
2 directly outputs to the data selector 45, and the necessary correction data is selected by the data selector 45.
Sequentially store in registers.

Next, (c) when the interrupt of the interrupt request 2 is generated and the interrupt of the interrupt request n is further generated, the correction data C not branched at the branch n (NO) is already stored in the secondary IFU. Therefore, branch at branch n (YE
S) The correction data n are sequentially stored in the third IFU (third I
The correction data B written in the FU is erased).

At the same time, the correction data n is written into the write selection circuit 4
2 directly outputs to the data selector 45, and the necessary correction data is selected by the data selector 45.
Sequentially store in registers.

(D) When the interrupt request 1 is generated and the interrupt request 2 is further generated, and there is no interrupt request n, the correction data A of the secondary IFU is not erased, and the process branches to branch 2 (YES). The correction data C is the write selection circuit 4
2 directly outputs to the data selector 45, and the necessary correction data is selected by the data selector 45.
Sequentially store in registers.

In this case, the correction data A and the correction data B, which are processed when the processing of the correction data C branched (YES) in the branch 2 ends and the process returns to the main routine, the memory data is read again to perform the ECC correction. You don't have to.

The data temporarily stored in the secondary IFU and the tertiary IFU and the data directly sent from the ECC processing selection selector are set by the data selector 45 in the 3rd register as the data required for the instruction execution of the CPU 4. .

Then, as the machine cycle progresses,
It is set in the 4th and 5th registers and output to the instruction register 14, and the CPU 4 executes the instruction.

Therefore, according to the data processing apparatus of the third embodiment of the present invention, the effect of the invention shown in the data processing apparatus of the first embodiment of the present invention and the second embodiment of the present invention.
In addition to the effect of the invention shown in the data processing device according to the embodiment of the present invention, the content of the instruction is determined in advance for both the non-branching data and the branching data that have undergone ECC processing, and the secondary IFU
Also, it can be stored in the tertiary IFU, the load on the data bus can be further reduced, and the processing speed can be improved.

Next, a data processing device according to a fourth embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 5 is a block diagram of a data processing device according to the fourth embodiment of the present invention.

Referring to FIG. 5, the data processor according to the fourth embodiment of the present invention has a configuration for executing DMA (Dynamic Memory Access) between the external user memory 1 and the internal user memory 2. It has the same components as the data processing device according to the first exemplary embodiment of the present invention, except that the DMA controller 51 for controlling is provided.
The same components are designated by the same reference numerals, and detailed description of the configurations will be omitted.

Next, the operation of the data processing apparatus according to the fourth embodiment of the present invention will be described.

In the data processor according to the fourth embodiment of the present invention, the CPU 4 sends the DMA execution instruction to the DMA controller 51. The DMA controller 51 is
Data is transferred to the internal user memory 2 by designating the address of the external user memory 1.

Next, the DMA controller 51 is set in advance so that the memory data is transferred to the internal user memory 2, and the transfer is performed directly from the external user memory 1 to the internal user memory 2 without passing through the CPU 4. It

Further, after the necessary memory data is transferred, the CPU 4 specifies the address of the internal user memory, and the address of the internal user memory 2 is specified via the address bus 6.

Then, the memory data at the designated address is output to the data bus 5.

Further, the memory data output to the data bus 5 is set in the 1st register of the IFU 3 incorporated in the CPU 4, and the memory data set in the 1st register is set in the machine cycle as shown in the timing chart of FIG. At 2, the 1st register is shifted to the 2nd register.

At that time, the check bit data written in the internal user memory 2 is set in the 1st register in advance.

Next, the memory data set in the 2nd register is subjected to correction detection by the check bit data set in the 1st register and the ECC correction circuit 11,
It is output to the ECC processing selection selector 12.

Further, the ECC processing selection selector 12 is
The ECC correction data output from the ECC correction circuit 11 and the memory data set in the 2nd register are received, and one of the data is set to 3r by the ECC selection signal 13.
The output of the ECC processing selection register 12 set in the d register and set in the 3rd register is set in the 4th and 5th registers as the machine cycle progresses, is output to the instruction register 14, and the CPU 4 executes the instruction.

According to the data processor of the fourth embodiment of the present invention, since the CPU 4 does not execute the instructions related to the DMA transfer, the CPU operation is possible even during the DMA transfer and the internal user memory As soon as the data related to the instruction execution of the CPU 4 is written in 2, the necessary data is pre-read in advance and the data corrected by ECC is CP.
U4 can be used to execute instructions.

Next, a data processing device according to a fifth embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 6 is a block diagram of a data processing device according to the fifth embodiment of the present invention.

Referring to FIG. 6, in the data processing device according to the fifth embodiment of the present invention, the data output unit of the CPU 4 is provided with E.
CC check bit generation circuit 63 and data selector 62
The data processing apparatus has the same components as the data processing apparatus according to the first embodiment of the present invention except that The same components are designated by the same reference numerals, and detailed description of their configurations will be omitted.

Next, the operation of the data processing apparatus according to the fifth embodiment of the present invention will be described.

In the data processor of the fifth embodiment of the present invention, the external user memory 1 and the internal user memory 2 are used.
From the reading of the data to the execution of the instruction of the CPU 4, the data processing apparatus according to the first embodiment of the present invention is the same.

Therefore, the EC after the instruction of the CPU 4 is executed
The operation up to C check bit generation and writing to the external user memory 1 and the external user memory 2 will be described.

In the data processor according to the fifth embodiment of the present invention, the data subjected to the arithmetic processing is input to the ECC check bit generation circuit 63 and the check bit generation circuit 6
3 generates check bit data required for ECC correction based on the arithmetic processing data. That is, when the CPU arithmetic processing data is 8 bits, the check bit data is 4 bits.
When t is generated and the CPU arithmetic processing data is 16 bits, 5 bits are generated as the check bit data, and CP is generated.
When the U arithmetic processing data is 32 bits, 6 bits are generated as the check bit data.

Next, the check bit data is controlled by the data selector 62 to be output to the data bus 5 only when the external user memory 1 or the internal user memory 2 has a write instruction. Further, the check bit data output to the data bus 5 is written in the internal user memory 2 or the external user memory 1.

When using the DMA, it is once written in the internal user memory 2 and then directly transferred to the outside by the DMA.

When ECC correction is performed, check bit data for correction is required. In the conventional data processing device disclosed in Japanese Patent Laid-Open No. 7-56758, the bus control unit is provided. According to the data processing device of the fifth embodiment, by adding the ECC check bit generation circuit 63 to the output unit of the CPU 4, it is possible to generate check bit data for all data executed by the CPU. Correction detection can be performed consistently from check bit generation.

Next, a data processing device according to a sixth embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 7 is a block diagram of a data processing device according to the sixth embodiment of the present invention.

Referring to FIG. 7, the data processor according to the sixth embodiment of the present invention is the same as the first embodiment of the present invention except that an ECC check bit generation circuit 71 is provided on the input side of the internal user memory 2. It has the same components as the data processing device of the embodiment. The same components are designated by the same reference numerals, and detailed description of their configurations will be omitted.

Next, the operation of the data processing apparatus of the sixth embodiment of the present invention will be described.

In the data processor according to the sixth embodiment of the present invention, the external user memory 1 and the internal user memory 2 are used.
From the data read of the above to the instruction execution of the CPU 4 is the same as that of the data processing device according to the first embodiment of the present invention, and therefore the operation from the instruction execution of the CPU 4 until the writing to the external user memory 1 and the external user memory Will be explained.

In the data processing device according to the sixth embodiment of the present invention, the address for writing in the internal user memory 2 is designated by the CPU 4.

Next, based on the designated address, the CPU
The data output from 4 passes the data bus 5 to the ECC.
The ECC check bit generation circuit 71 is sent to the check bit generation circuit 71, and the ECC check bit generation circuit 71 generates check bit data based on the CPU output data. Specifically, when the CPU arithmetic processing data is 8 bits, the check bit data is 4 bits.
When it is generated and the CPU arithmetic processing data is 16 bits, 5 bits are generated as the check bit data, and CP
When the U arithmetic processing data is 32 bits, 6 bits are generated as the check bit data.

Then, the CPU output data and the check bit generation data are written in the internal user memory 2.

On the other hand, when writing to the external user memory 1, like the data processor of the fourth embodiment of the present invention, the check bit data is written from the internal user memory 2 to the external user memory 1 by DMA. Whether to write or not write to the external user memory 1 depends on the presence or absence of the check bit generation circuit of the external user memory 1 and therefore needs to be controlled.

As described above, in the data processing device according to the sixth embodiment of the present invention, when ECC correction is performed,
Check bit data is required, and the check bit data can be generated by providing the ECC check bit generation circuit 71 in the data input section of the memory.

[0117]

As described above, the first effect of the present invention is that when the memory data is accessed from the external user memory 1 or the internal user memory 2, the external user memory 1 or the internal user memory 2 is EC at the time of reading.
Since C correction processing is not performed, memory access can be performed without ECC correction time during the limited machine cycle period of memory data access, and the memory access speed originally possessed by the memory can be obtained.

The second effect of the present invention is that it is not necessary to provide the ECC correction circuit circuit 10 provided in the internal user memory 2 as in the prior art, and the chip area of the semiconductor integrated circuit can be reduced.

In particular, the larger the number of internal user memories 2, the greater the effect. Furthermore, since it is not necessary to use an external user memory with an ECC, an inexpensive memory can be used.

The third effect of the present invention is described in JP-A-7-5.
If the bus control unit is provided with a check bit generation circuit and the CPU is provided with an ECC correction circuit as described in Japanese Patent No. 6758, the bit width of the processor bus increases and the chip size increases. When using 8 buses, 4 check bit data buses are required, and when using 16 memory data buses, 5 check bit data buses are required.
In the case of 32 memory data buses, 6 check bit data buses are required.) In the data processing device according to the first embodiment of the present invention, the memory data and the check bit data are divided and transferred from the internal user memory 2. Since the number of data buses can be realized only by the width of the number of memory data, the present invention does not affect the chip size.

The fourth effect of the present invention is that the ECC correction data provided in the ECC correction circuit 9 of the external user memory 1 and the ECC correction circuit 10 of the internal user memory 2 of FIG. By providing the function switching in the ECC correction circuit 11 of FIG. 1, it is not necessary to set the selection control, and the switching can be easily performed.

The fifth effect of the present invention is that when accessing memory data with the external user memory 1, the ECC correction can be performed inside the CPU even if the external user memory 1 without ECC is used. Highly reliable data processing can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram of a data processing device according to a first embodiment of this invention.

FIG. 2 is a time chart explaining the operation of the data processing device of the first exemplary embodiment of the present invention shown in FIG.

FIG. 3 is a block diagram of a data processing device according to a second embodiment of this invention.

FIG. 4 is a block diagram of a data processing device according to a third embodiment of this invention.

FIG. 5 is a block diagram of a data processing device according to a fourth embodiment of the present invention.

FIG. 6 is a block diagram of a data processing device according to a fifth embodiment of the present invention.

FIG. 7 is a block diagram of a data processing device according to a sixth embodiment of the present invention.

FIG. 8 is a flowchart of a branch instruction.

FIG. 9 is a time chart explaining the operation of the data processing device of the second exemplary embodiment of the present invention shown in FIG.

FIG. 10 is a block diagram of a conventional data processing device.

FIG. 11 is a time chart explaining the operation of the conventional data processing device.

[Explanation of symbols]

1 External User Memory 2 Internal User Memory 3 IFU 4 CPU 5 Data Bus 6 Address Bus 7 Data Port 8 Address Port 11 ECC Correction Circuit 12 ECC Processing Selection Selector 13 ECC Data Selection Signal 14 Instruction Register 15 1st Register 16 2nd Register 17 3rd Register 18 4th register 19 5th register 20 nth register 21 ECC correction circuit and ECC processing selection selector register 31 Secondary IFU 42 Write selection circuit 43 Secondary IFU 44 Tertiary IFU 45 Data selector 51 DMA controller 52, 53 DMA bus 62 Data selector 63 , 71 ECC check bit generation circuit 109, 110 ECC correction circuit S11 to S23 Steps

Claims (11)

[Claims] 1. A CPU having an external user memory, an internal user memory, an IFU having a 1st register to an nth register (n is a positive integer), an ECC correction circuit and an ECC processing selection selector, and an instruction register. A data bus and an address bus required for data access between the external user memory and the internal user memory and the CPU; and a data port and an address port required for access to the external user memory. The memory data output to the
The memory data set in the 1st register of the IFU built in the U and further set in the 1st register is 2n from the 1st register in a predetermined machine cycle.
The check bit data written in the external user memory or the internal user memory at the same time as being shifted to the d register is set in the 1st register in advance, and the memory data set in the 2nd register is set in the 1st register.
Check bit data and ECC set in the register
The correction circuit performs correction detection and outputs it to the ECC processing selection selector. The ECC processing selection selector receives the ECC correction data output from the ECC correction circuit and the memory data set in the 2nd register, and by the ECC selection signal, A data processing device characterized by setting any data in a 3rd register. 2. An EC having a function of temporarily storing data
C ECC for secondary IFU for sequentially storing processed data
The data processing device according to claim 1, which is provided in a data output unit of the selection selector. 3. The data output unit of the ECC processing selection selector according to claim 1, further comprising a secondary IFU and a tertiary IFU holding the data subjected to the ECC correction processing, a write selection circuit, and a data selector. Data processing device. 4. The data output from the ECC processing selection selector is a write selection circuit for a secondary IFU and a tertiary IFU.
4. The data processing device according to claim 3, wherein the selection as to whether to write to or directly output to the data selector is executed by judging the content of the instruction. 5. Branch 1 when interrupt request 1 occurs
The correction data A not branched at (NO) is stored in the secondary IFU, and the correction data B branched at branch 1 (YES) is
The correction data B is stored in the tertiary IFU, and at the same time, the correction data B is directly output from the write selection circuit 42 to the data selector, the necessary correction data is selected by the data selector, and sequentially stored in the third, fourth, and fifth registers. The data processing device according to claim 3 or 4. 6. When the interrupt of the interrupt request 1 is generated and further the interrupt request of the interrupt request 2 is generated, the correction data B not branched in the branch 2 (NO) is already the tertiary IF.
Since it is stored in U, the correction data C branched at branch 2 (YES) is sequentially stored in the secondary IFU, and the correction data A written in the secondary IFU is deleted, and at the same time, the correction data C is stored. Directly output to the data selector from the write selection circuit,
Select the required correction data with the data selector and
The data processing device according to claim 5, wherein the data is stored in the fourth and fifth registers sequentially. 7. When the interrupt of the interrupt request 2 is generated and the interrupt of the interrupt request n is further generated, the correction data C not branched in the branch n (NO) is already stored in the secondary IFU. The correction data n branched at n (YES) is sequentially stored in the tertiary IFU to erase the correction data B written in the tertiary IFU, and at the same time, the correction data n is directly written from the write selection circuit to the data selector. Output,
Select the required correction data with the data selector and
7. The data processing device according to claim 6, wherein the data is sequentially stored in the fourth and fifth registers. 8. When an interrupt request 1 is generated and an interrupt request 2 is further generated and there is no interrupt request n, 2
The correction data A of the next IFU is not erased, and the correction data C branched (YES) in branch 2 is directly output from the write selection circuit to the data selector, and the necessary correction data is selected by the data selector. The data processing device according to claim 7, wherein the data is stored in the fourth and fifth registers sequentially. 9. The data processing apparatus according to claim 1, further comprising a DMA (Dynamic Memory Access) for the external user memory and the internal user memory, and a DMA controller for controlling the DMA. 10. The data processing apparatus according to claim 1, further comprising an ECC check bit generation circuit and a data selector in a data output section of the CPU. 11. The data processing device according to claim 1, further comprising an ECC check bit generation circuit on the input side of the internal user memory.