JPH04346112A - Method and device for reset signal identification - Google Patents

Abstract

PURPOSE:To identify the difference of a reset signal by detecting, holding, and deciding the H level of the power reset signal based upon the power-ON operation of a low-order device and changing the holding of the H level to an L level. CONSTITUTION:When the low-order device 2 is powered ON, the H level of the power-ON reset signal RS2 based upon the power-ON operation is detected by a power source detecting circuit 3 and held in a register 4. This held H level is read by a processor 5, which decides whether or not the signal is the power-ON reset signal RS2 and then varies the output of the register 4 to the L level after deciding that the signal is the power-ON reset signal RS2. Further, when a reset signal RS1 is inputted to the low-order device 2 from a host device 1, the power source detecting circuit 3 does not operate, so the level is still the L level and the processor 5 inputs this L level, so no power-ON resetting process is performed.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention provides two reset methods: one is to output a reset signal from a higher-level device to a lower-level device when a problem occurs, to reset the lower-level device, and the other is to reset the lower-level device by a power-on reset signal when the power is turned on. This invention relates to a method and apparatus for identifying signals.

In particular, the present invention relates to a reset signal identification method and apparatus that avoids performing processing only when a lower-level device is powered on for each reset signal from a higher-level device.

0003

2. Description of the Related Art FIG. 3 is a conventional flow chart. Referring to FIG. 1, the conventional method will be explained according to this flow chart. The lower unit 2, microprocessor 5, program memory 6, and work memory 7 are initialized by RS1.

When initialized, the microprocessor 5 executes (starts) from address 0 of the program memory 6.
At power-on reset, all memory areas of the work memory 7 are set to "0" value (memory 0 cleared), a memory check of the program memory 6 is performed (a process performed once after power is turned on), and after that, the lower device 2 The microprocessor 5 starts operation based on the output of the host device 1.
The lower device 2 is controlled according to the program in the program memory 6.

[0005]

[Problems to be Solved by the Invention] In the above-mentioned conventional example, since the software cannot distinguish between the two types of reset signals, the process that should be performed only once after the power is turned on is performed only once by the host device.
There is a problem that the process is performed every time there is a reset signal from the .

[0006]

[Means for Solving the Problems] In order to solve the above-mentioned problems, the method of the present invention, as shown in FIG. In a method for identifying two reset signals RS1 and RS2 that reset the lower device 2 by a power-on reset signal RS2 caused by power-on of the lower-level device 2, the reset signal is a power-on reset signal RS2 caused by power-on of the lower-level device 2. The power supply detection circuit 3 detects the H level of the power reset signal RS2 only at certain times, the detected H level of the power-on reset signal RS2 is held by the register 4, and the held H level is sent by the processor 5. It is characterized in that it is read and determined to be the power-on reset signal RS2, and then the contents of the register 4 are set to L level.

In order to solve the same problem, the device of the present invention outputs a reset signal RS1 from the higher-level device 1 to the lower-level device 2 in the event of a problem as shown in FIG. In a device that identifies two reset signals RS1 and RS2 that reset the lower device 2 by a power-on reset signal RS2 caused by A power supply detection circuit 3 that detects the H level of the on-reset signal RS2, a register 4 that holds the H level of the power-on reset signal RS2 output from this power supply detection circuit 3, and a register 4 that reads the H level held in this register 4. It is determined that it is the power-on reset signal RS2, and
Thereafter, the processor 5 sets the contents of the register 4 to L level.

[0008]

[Operation] When the lower device 2 is powered on, the power detection circuit 3 detects the H level of the power-on reset signal RS2 due to the power-on, and the register 4 holds the detected H level of the power-on reset signal RS2. Ru. This held H level is read by the processor 5, and it is determined whether or not it is the power-on reset signal RS2, and it is determined that it is the power-on reset signal RS2. Thereafter, the processor 5 sets the output of the register 4 to the L level.

When the reset signal RS1 from the higher-level device 1 is input to the lower-level device 2, the power supply detection circuit 3 does not operate, so it remains at the L level. Since the processor 5 inputs this L level, it does not perform power-on reset processing.

0010

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing the structure of an embodiment of the method and apparatus of the present invention, and FIG. 2 is a flowchart thereof. In FIG. 1, numeral 1 denotes a higher-level device such as a control device, and 2 denotes a lower-level device such as a controlled device controlled by this higher-level device 1. In FIG. 3 is a power supply detection circuit that detects the H level of the power-on reset signal RS2 obtained when the power is turned on to the lower device 2; 4 is a set/reset circuit that maintains the H level of the power-on reset signal RS2 output from the power supply detection circuit 3; It's a flip flop.

5 reads the H level held in this flip-flop circuit 4 and outputs a power-on reset signal RS2.
6 is a program memory, 7 is a work memory, and 8 is a system bus. Upper and lower devices 1 and 2, power supply detection circuit 3, flip-flop circuit 4, microprocessor 5, program memory 6
and the work memory 7, etc., are implemented as ICs and LSIs, respectively.

In this embodiment with the above configuration, the lower device 2
The lower device 2, microprocessor 5, program memory 6, and work memory 7 are initialized by a power-on reset signal RS2 when the power is turned on or by a reset signal RS1 from the higher device 1. When initialized, the microprocessor 5 starts execution from address 0 of the program memory 6 (
start).

On the other hand, when the lower device 2 is powered on, the power detection circuit 3 detects the H level of the power on reset signal RS2 due to the power on, and the detected H level of the power on reset signal RS2 is detected by the flip-flop circuit. 4 is maintained. This held H level is read by the microprocessor 5, and it is determined whether or not it is the power-on reset signal RS2, and it is determined that it is the power-on reset signal RS2.

At power-on reset, the microprocessor 5 sets all memory areas of the work memory 7 to the "0" value (clears memory 0), and performs a memory check of the program memory 6 (processing performed once after power is turned on). After that, the output of the flip-flop circuit 4 is cleared by the microprocessor 5 and changed from H level to L level. Thereafter, the operation of the lower-level device 2 is started, and the lower-level device 2 is controlled by the microprocessor 5 according to the program in the program memory 6 based on the output of the higher-level device 1.

When the reset signal RS1 from the higher-level device 1 is input to the lower-level device 2, the power supply detection circuit 3 remains at L level because it does not operate. Since the microprocessor 5 inputs this L level, it does not perform power-on reset processing. Note that when the microprocessor 5 receives the reset signal RS1 from the host device 1, the work memory 7 is not cleared and the program memory 6 is not checked.

[0016]

As described above, according to the present invention, the H level of the power reset signal RS2 is detected when the lower device 2 is powered on, and the detected power reset signal RS2 is
2 is held at the H level, the held H level is read and determined to be the power-on reset signal RS2, and then the held H level is changed to the L level to generate the power reset signal RS2 when the power is turned on. and the reset signal RS1 from the host device 1 can be identified, and it is possible to avoid performing a process that is performed only when the power of the host device 2 is turned on for each reset signal from the host device 1.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of one embodiment of the method and apparatus of the present invention.

FIG. 2 is a flowchart of the same.

FIG. 3 is a conventional flowchart.

[Explanation of symbols]

1 Upper device 2 Lower device 3 Power supply detection circuit 4 Register (set/reset flip-flop circuit) 5 (Micro)processor 6 Program memory 7 Work memory RS1 Reset signal RS2 Power-on reset signal

Claims (2)

[Claims] Claim 1: A host device (1) outputs a reset signal (RS1) to a lower device (2) in the event of a problem to reset the lower device (2), and also outputs a power-on reset signal (RS2) when the power is turned on. ) by the lower device (
2) two reset signals (RS1, R
In the method for identifying a power reset signal (S2), the reset signal is a power reset signal (
This power reset signal (
The power supply detection circuit (3) detects the H level of the power-on reset signal (RS2) and outputs the detected power-on reset signal (RS2).
) is held by the register (4), this held H level is read by the processor (5) and determined to be the power-on reset signal (RS2), and then the contents of the register (4) are read. A reset signal identification method characterized by setting it to L level. [Claim 2] The upper device (1) outputs a reset signal (RS1) to the lower device (2) in the event of a problem to reset the lower device (2), and also outputs a power-on reset signal (RS2) when the power is turned on. ) by the lower device (
2) two reset signals (RS1, R
A power supply detection circuit detects the H level of the power-on reset signal (RS2) only when the reset signal is a power-on reset signal (RS2) caused by power-on of the lower-order device (2) in the device for identifying the power-on reset signal (RS2). (3), a register (4) that holds the H level of the power-on reset signal (RS2) output from this power supply detection circuit (3), and a power-on by reading the H level held in this register (4). Reset signal (RS2)
A reset signal identification device comprising a processor (5) that determines that the register (4) is L level after that.