JPH0426913Y2 - - Google Patents

Description

[Detailed explanation of the invention] [Purpose of the invention] (Field of industrial application) The present invention is a microprocessor unit (hereinafter referred to as CPU) that comprehensively controls the operation of electronic equipment such as personal computers and workstations. The present invention relates to an indicator circuit provided to correctly identify whether a control program is loaded in main memory during a cold boot (when power is turned on) or during a warm boot (in the middle of operation).

(Prior Art) Conventionally, in electronic devices such as personal computers and workstations, for example, a CPU that comprehensively controls the operation of the device has a CPU that determines whether a control program is loaded in the main memory by a cold boot or a warm boot. An indicator circuit is provided for correct identification.

FIG. 3 is a diagram showing the configuration of an indicator circuit in a conventional electronic device.

In the figure, a is the CPU, b is the main memory where a control program (machine language) that controls the operation of CPUa is written, c is the disk where the user program (high-level language) is written, and d is the main memory. e is a register in which specific data is set when the control program is loaded in the memory by cold boot, and e is a register in which data to be written to peripheral LSIfs such as timers and each interface is temporarily set. It shows.

In such a circuit, during the cold boot or warm boot, a control program is written from disk c to main memory b via a compiler, etc., and this control program is sequentially written to an instruction register (not shown) inside CPUa. Embedded,
CPUa operates according to the microcode corresponding to each control program.

Further, the data output from the CPUa to the peripheral LSIf is temporarily set in the register e.

In such a circuit, the CPUa identifies whether the boot is cold or warm based on the state of the register d, and controls writing of the control program to the main memory b depending on each case.

For example, in the case of a cold boot, the control program is written from disk C to main memory B starting at the first address, but in the case of a warm boot, a certain part of the control program on main memory B is left enabled until the next step. Write a new control program from the address.

Therefore, if the CPUa cannot distinguish between a cold boot and a warm boot at a certain point, all previously loaded control programs may be cleared and a waiting time may be required to reload them. .

FIG. 4 is a diagram specifically showing the register d, register e, and peripheral LSIf in FIG. 3.

In the figure, 1 is a register d for latching specific data set at the time of cold boot;
2 is a driver for controlling whether or not to read the data latched in register 1; 3 is a register e for latching data to be written to peripheral LSI 6; and 4 is a driver for controlling whether or not to read data latched in register 3. Driver for, 5 is peripheral
A driver for outputting the data read from LSIf6 to a 4-bit data bus _D1 , _D2 is a 4-bit data bus that connects register 1 and driver 2, and _S1 is a write function that sets data to register 1. signal, _S2 is a clear signal that clears register 1 when power is turned on, _S3 is an enable signal that activates driver 2, _D3 is a 4-bit data bus that connects register 3 and driver 4, _S4 is data _S5 is a clear signal that clears register 3 when power is turned on, _S6 is an enable signal that activates driver 4, _S7 is an enable signal that activates driver 5, _D4 is a write signal that sets A 4-bit data bus connecting drivers 4, 5 and LSI 6, A ₁ is a 4-bit address bus for LSI 6, S ₈ is a write signal for LSI 6, S ₉ is a read signal for LSI 6,
_S10 indicates a chip select signal for LSI6.

This circuit uses the clear signal at cold boot.
Register 1 is cleared by S ₂ , and then CPUa
sets specific data in register ₁ via data bus D1.

At the time of warm boot, CPUa identifies the warm boot from the state of register 1.

That is, the CPUa identifies a cold boot when register 1 is in a clear state, and identifies a warm boot when specific data is set in register 1.

On the other hand, when CPUa sets data to LSI 6, it temporarily holds the data to be set in register 3, disables signal _S7 , and disables signal _S6 .
and activates address bus A ₁ , write signal S ₈ and chip select signal S ₁₀ .

Also, when reading data from LSI6, the signal
Disable S ₆ , enable signal S ₇ ,
Address bus A ₁ , read signal S ₉ and chip select signal S ₁₀ are activated.

(Problem to be solved by the invention) However, as described above, in the conventional indicator circuit, register 1 is set with specific data set at the time of cold boot, and register 3 is set with write data for LSI 6. Because they are separate, the number of parts is large and the circuit configuration is complex.

The present invention was developed under these circumstances, and aims to provide an indicator circuit with a small number of parts and a simple circuit configuration.

[Structure of the invention] (Means for solving the problem) The indicator circuit of the invention consists of a main control circuit (CPU), a peripheral circuit (LSI) capable of reading and writing data, and an operation of the main control circuit. a main memory circuit that sequentially stores control programs that control the main control circuit; a register circuit that can hold either data to be written from the main control circuit to the peripheral circuits or specific data that is set when the power is turned on; When indicating the contents, there is a judgment means for judging the presence or absence of specific data stored in the register circuit, a control means for controlling the operation of the main control circuit based on the judgment result of the judgment means, and a control means for controlling the operation of the main control circuit in the register circuit. The present invention is characterized in that, when it becomes necessary to hold write data, the register circuit is equipped with a data moving means for temporarily moving specific data already set when the power is turned on to the main memory circuit.

(Function) In the indicator circuit of the present invention, when it becomes necessary to cause the register circuit to hold data to be written to the peripheral circuit, if the register circuit already holds specific data, the specific data is transferred to the main memory circuit. The conventional 2
One register has the functions of two registers, which reduces the number of parts and simplifies the circuit configuration.

(Example) Hereinafter, details of an example of the present invention will be described based on the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and parts common to those in FIG. 3 are given the same reference numerals.

In the figure, a is the CPU, b is the main memory in which the control program (machine language) that controls the operation of CPUa is written, c is the disk where the user program (high-level language) is written, and f is the timer. and peripheral LSIs such as each interface, g indicates a register in which either data to be written to LSIf or specific data set at the time of cold boot is set, as will be described later.

In such a circuit, at the time of cold boot or warm boot, a control program is loaded from disk c to main memory b via a compiler, etc., and this control program is sequentially set in an instruction register (not shown) inside CPUa,
CPUa operates according to the microcode corresponding to each control program.

At the time of cold boot, specific data indicating this is set in register g, but if it becomes necessary to write data to peripheral LSIf in this state, the data set in register g is temporarily stored in main memory b. After being moved to , the data to be written is set in register g.

When writing to the peripheral LSIf is completed, register g is cleared, and specific data is moved from main memory b to register g.

FIG. 2 is a diagram specifically showing the peripheral LSIf and register g in FIG. 1.

In the figure, 3' is a register g for latching either the data to be written to the peripheral LSIf6 or the specific data set at the time of cold boot.
4 is a driver for controlling readability of data latched in register 3', 5 is peripheral LSI 6
The data read from the 4-bit data bus
A driver for outputting data to _D1 , _D3 is a 4-bit data bus that connects register 3' and driver 4, _S4 is a write signal to set data in register 3', and _S5 is a data bus that connects register 3' to driver 4. Clear signal that clears driver 4, _S6 is an enable signal that activates driver 4, _S7 is an enable signal that activates driver 5, _D4 is driver 4,
5 and LSI6, _A1 is a 4-bit address bus for LSI6, _S8 is a write signal for LSI6, _S9 is LSI6
_S10 indicates a chip select signal for the LSI6.

In this circuit, at cold boot, register 3' is first cleared by clear signal _S5 ,
CPUa (described above) sets specific data from data bus _D1 to register 3'.

During a warm boot, it can be determined that the CPUa has been warm booted from the set state of this register 3'.

That is, the CPUa identifies a cold boot when the register 3' is in a clear state, and identifies a warm boot when specific data is set in the register 3'.

And when writing data to peripheral LSI6,
First enable signal S ₆ and signal S ₇ , and then
S ₈ , S ₉ and S ₁₀ are made inactive, the specific data set in register 3' is temporarily stored on main memory b, then the write data is set in register 3', and signal S ₆ is enable,
The signal _S7 is disabled, the address bus _A1 , the write signal _S8 and the chip select signal _S10 are activated to write data to the peripheral LSI 6, and furthermore, the specific data stored on the main memory is set in the register 3'.

Note that when reading data from peripheral LSI 6,
Disable signal S ₆ , enable signal S ₇ ,
Address bus A ₁ , read signal S ₉ and chip select signal S ₁₀ are activated.

In this way, the circuit of this embodiment has a small number of parts and a simple configuration because the register in which the specific data set at the time of cold booting the CPUa is set and the register in which the data to be written to the peripheral LSI 6 are set are common. is also simple.

In the above-described embodiment, the specific data set in the register 3' is set at the time of cold boot, but the specific data may be any data set at power-on. Therefore, this specific data is not necessarily used only for distinguishing between a cold boot and a warm boot, but may also be used for determining other controls.

[Effects of the invention] As explained above, in the indicator circuit of the invention, the register in which specific data set when the power is turned on and the register in which data to be written to the peripheral LSI are set are common. Because of this, the number of parts is small and the configuration is simple.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing the overall configuration of a circuit according to an embodiment of the present invention, Fig. 2 is a circuit diagram specifically showing a part of the circuit of Fig. 1, and Fig. 3 is a circuit diagram of a conventional indicator circuit. A circuit diagram showing the overall configuration, Figure 4 is the third
FIG. 2 is a circuit diagram specifically showing a part of the circuit shown in the figure. a...CPU, b...Main memory, c...Disk, d, e, g, 1, 3, 3'...Register,
2, 4, 5... Driver, f, 6... Peripheral LSI.

Claims (1)

[Claims for Utility Model Registration] A main control circuit that comprehensively controls the operation of an electronic device, a peripheral circuit that can read and write data, and a main circuit that sequentially stores a control program that controls the operation of the main control circuit. a memory circuit; a register circuit capable of holding either data to be written from the main control circuit to the peripheral circuit or specific data set at power-on; and when indicating the contents of the register circuit, the register circuit determining means for determining the presence or absence of specific data stored in a circuit; control means for controlling the operation of the main control circuit based on the determination result of the determining means; and controlling the register circuit to write data to the peripheral circuit. An indicator circuit comprising data moving means for temporarily moving specific data already set in the register circuit when the power is turned on to the main memory circuit when it becomes necessary to hold the data.