JPS58101360A - Data processor - Google Patents

Abstract

PURPOSE:To simplify the operation and to eliminate the time difference between communications, by providing a means which gives simultaneous interruption from one set of a central processor to other central processors, in a data processor comprising a plurality of central processors. CONSTITUTION:A data processor comprises a plurality of central processors CPUs 11, 12...1n. When simultaneous interruption is provided from a CPU (e.g., 11) to the other CPUs 12-1n, an interruption start circuit 21 is started, and level 1 is set to specific bits 72-7n of interruption registers 62-6n via gates 52-5n of the CPUs 12-1n on an interruption start signal line 31. Thus, interruption processing sections 82-8n of the CPUs 12-1n execute interruption processing. Further, the CPU11 inhibits the input of a gate 51 to an interruption register 61 with a signal on an interruption inhibit line 41. Thus, simultaneous interruption from each CPU to the other CPUs can be done, the operation can be simplified and the communication time can be arranged.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data processing device comprised of a plurality of central processing units.

Conventionally, at 5 o'clock when communicating with a partner central processing unit, the content of the communication is stored in advance at a specific address in the storage device of the partner central processing unit, and is sent to a predetermined bit of the interrupt register of the partner central processing unit by a command. 1" is written to the specified bit of the scissors interrupt register. On the other hand, the central processing unit that has written "1" to the predetermined bit of the scissors interrupt register knows that the predetermined bit of the interrupt register is 11" and writes the contents of the specific address. The content of the communication can be known by reading the .

However, in a data processing device composed of multiple central processing units, when one central processing unit communicates the same content to multiple other central processing units, the number of other central processing units is exceeded. The drawback is that the reprimand command must be executed the correct number of times. Moreover, there is a time difference between the first communication and the last communication among the other plurality of central processing units, and there is also the disadvantage that a complicated program is required to absorb this time difference.

SUMMARY OF THE INVENTION An object of the present invention is to provide a communication means that simplifies a program for communicating with a plurality of other central processing units.

The present invention achieves the above-mentioned object by providing five means for simultaneously interrupting a plurality of other central processing units from one central processing unit with one instruction.

Examples will be described below with reference to the drawings. The figure shows a data processing device of the present invention. 11 to 1n are central processing units, 21 to 2n are interrupt activation circuits for other central processing units,
51-buttons are interrupt activation signal lines, 41-n are interrupt activation prohibition signal lines for the own device, 81-i are gates, 41-buttons are interrupt registers, and 71-7n are interrupt activation signal lines for the own device. Specific bits of the interrupt register for identification, 81 to axis are specific bits of the interrupt register 71 to 7n IIC'''1'''
This is an interrupt processing unit that is activated when .

Here, as an example, the operation in the case where the central processing unit 11 and other central processing units 12, 4flK are simultaneously interrupted will be described.

First, the central processing unit 11 executes an instruction to activate the interrupt activation circuit 21. As a result, the interrupt activation circuit 21 is activated,
The signal on the interrupt activation signal line s1 is prohibited from being set to "1" in the interrupt register 61 of the own device at the gate 51 by the signal on the interrupt activation prohibition signal line 41, and is also prohibited from being set to "1" in the interrupt register 61 of the own device.
The specific bit 7 of the interrupt register 6Nn is set to ``@1'' to the door II via the gate 52-5-6n.The interrupt processing unit 1a of the other central processing units 12 to 1n register 4)-60 specific bit 7 to 7W&'
Since "1" is set, interrupt processing is executed.

In this way, simultaneous interrupts from the central processing unit 11 to the other central processing units 1 )-I n are executed. The operation of each central processing unit after the simultaneous interrupt is the same as in the prior art. Simultaneous interrupts to the central processing unit 11.1 and 1n can also be explained in the same way.

As described above, by implementing the present invention, it is possible to interrupt simultaneously from one central processing unit to multiple other central processing units with a single instruction, which has the effect of simplifying the program. .

[Brief explanation of drawings]

The figure is a pull diagram of an embodiment of a data processing device according to the present invention. 11 to 1n-・Central processing unit 21 to 1m...Interrupt activation circuit 51 to button--Interrupt activation signal line 4l-4n...Interrupt activation prohibition signal line 51 to button--
41S411-Interrupt register 1~7n
...Specific bits 8l-8n ...Interrupt processing department attorney + Maro 1) Kai -

Claims (1)

[Claims] 1. A data processing device comprising a plurality of central processing units, characterized in that the data processing device includes means for simultaneously interrupting one central processing unit to another central processing unit based on a command.