JPH05143197A - Arithmetic processor - Google Patents

Abstract

PURPOSE:To selectively restart only a device in which a microprocessor is disabled to operate. CONSTITUTION:At the time of detecting the operation disablement of the microprocessor 2, a microprocessor down detecting circuit 4 sends an inter-device intra-interface reset signal 111 in an inter-device interface 100 to an OR circuit 8 as a reset command signal 112. The OR circuit 8 sends the signal 112 inputted from the circuit 4 to the microprocessor 2, an interface controller 3 and arithmetic processing circuits 6, 7 as an intra-device reset signal 113 to respectively start the microprocessor 2, the interface 3 and the circuits 6, 7.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to an arithmetic processing unit, and more particularly to a method of activating a microprocessor of the arithmetic processing unit.

[0002]

2. Description of the Related Art Conventionally, in an arithmetic processing unit, the microprocessor is activated by turning on the power of the unit or performing a reset operation such as operating a reset switch of the unit to enable a reset terminal of the microprocessor. Is going.

When the microprocessor is activated, it sequentially executes the programs stored in the ROM in the device. Generally, the interface test program is executed when the power of the device is turned on to test and initialize the arithmetic processing circuit in the device.

Further, the above arithmetic processing unit is provided with an inter-device interface in order to interface with an arithmetic processing unit outside the device. When an arithmetic processing unit outside the device executes various instructions for this arithmetic processing unit, the microprocessor in the arithmetic processing unit outside the device judges the instruction code after performing data transfer according to the inter-device interface protocol. And instructs the arithmetic processing circuit in the apparatus to perform arithmetic processing.

Further, there is an arithmetic processing unit that can activate a microprocessor in the device by a reset signal in the inter-device interface from an arithmetic processing unit outside the device, similarly to when the power of the device is turned on.

An example of the above-mentioned inter-device interface is a SCSI (small computer system interface) protocol interface. In the case of this SCSI protocol interface, the instruction code is normally transferred via the data signal line, but when resetting the other arithmetic processing unit, the reset signal in the SCSI protocol interface is made effective so that the normal instruction is executed. The reset instruction can be sent to another processing unit without transferring the code.

In such a conventional arithmetic processing unit, when the microprocessor becomes inoperable due to some failure, the reset signal in the inter-device interface is activated from the arithmetic processing unit outside the device to activate the microprocessor. It can be started by doing
At this time, all the arithmetic processing units connected to the inter-device interface are also restarted.

Further, in the arithmetic processing unit in which the failure has occurred, the inside of the apparatus is initialized by restarting, so no analysis information remains in the apparatus to analyze the cause of the failure. It has the drawback of not having it.

[0009]

SUMMARY OF THE INVENTION The present invention has been made in order to eliminate the above-mentioned drawbacks of the prior art, and provides an arithmetic processing device capable of selectively restarting only the device in which the microprocessor is inoperable. For the purpose of provision.

Another object of the present invention is to provide an arithmetic processing unit capable of easily analyzing the cause of failure after restart.

[0011]

A position detecting device according to the present invention is an arithmetic processing device having a microprocessor activated in response to a reset operation of the device and a reset signal from the outside, and detects occurrence of a failure in the microprocessor. And a means for determining whether the reset signal is valid or invalid according to the detection result of the detecting means.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, the processing unit 1 resets the reset signal by turning on the power of the device or performing a reset operation such as operating a reset switch of the device.
When 101 becomes valid, the in-device reset signal 113 output from the OR circuit 8 to the microprocessor 2, the interface controller 3, and the arithmetic processing circuits 6 and 7 becomes valid, so that the microprocessor 2, the interface controller 3, and the arithmetic operation are performed. The processing circuits 6 and 7 are activated respectively.

When activated by an in-device reset signal 113 from the OR circuit 8, the microprocessor 2 reads out the program from the ROM 5 via the data bus 110 and executes it in order. Further, the interface controller 3 and the arithmetic processing circuits 6 and 7 are initialized when activated by the in-device reset signal 113 from the OR circuit 8, and initialized by the initialization program executed by the microprocessor 2.

A signal is sent from the microprocessor 2 to the microprocessor down detection circuit 4 via the data bus 110 at regular intervals. If the signal from the microprocessor 2 has not been sent for a certain period of time, the microprocessor down detection circuit 4 sends the inter-device interface reset signal 111 in the inter-device interface 100 to the OR circuit 8 as a reset instruction signal 112.

At this time, if the reset signal 111 in the inter-device interface is valid by an arithmetic processing device (not shown) outside the device, the OR circuit 8 causes the microprocessor 2, the interface controller 3, the arithmetic processing circuit 6, and the like. Since the in-apparatus reset signal 113 output to each of 7 and 7 becomes effective, the microprocessor 2, the interface controller 3, and the arithmetic processing circuits 6 and 7 are activated respectively.

FIG. 2 is a diagram showing the configuration of the microprocessor down detection circuit 4 of FIG. In the figure, the processor down detection timer 41 of the microprocessor down detection circuit 4 is instructed to start or reset by a signal from the microprocessor 2 which is input via the data bus 110 at regular intervals.

If a signal from the microprocessor 2 is not input for a certain period of time, the processor down detection timer 41 outputs a timer overflow signal 141 to a processor down detection flip-flop (hereinafter referred to as processor down detection F / F) 42. Validate. When the timer overflow signal 141 becomes valid, the processor down detection F /
The F42 holds "1" and outputs "1" to the processor down instruction signal 142 to the AND circuit 43.

The AND circuit 43 resets the inter-device interface reset signal when the processor down instruction signal 142 from the processor down detection F / F 42 becomes "1".
111 is output as a reset instruction signal 112. Therefore,
When the reset signal 111 in the inter-device interface becomes valid, the reset instruction signal 112 also becomes valid.

As a result, the inter-device interface 100
Among the plurality of arithmetic processing units connected above, only the arithmetic processing unit 1 in which the microprocessor down detection circuit 4 detects the inoperability of the microprocessor 2 is selectively restarted.

FIG. 3 is a block diagram showing the configuration of another embodiment of the present invention. In the figure, a processor 9 according to another embodiment of the present invention stores a reset instruction for storing whether the microprocessor 2 is activated by the reset signal 101 or the reset instruction signal 112 from the microprocessor down detection circuit 4. The configuration is the same as that of the embodiment of the present invention except that the memory circuit 10 is provided, and the same components are designated by the same reference numerals. The operation of the same component is also the same as that of the embodiment of the present invention.

The reset instruction storage circuit 10 receives a reset signal 101 when the power of the device is turned on or the device is reset.
When the reset instruction signal 112 from the microprocessor down detection circuit 4 becomes valid, "1" is stored as the state value when "1" becomes valid.

The microprocessor 2 uses the reset signal 101
Alternatively, when the reset instruction signal 112 is activated and activated, the programs read from the ROM 5 via the data bus 110 are sequentially executed. At this time, first, the data bus
The state value is read from the reset instruction storage circuit 10 via 110.

If the state value from the reset instruction storage circuit 10 is "0", the microprocessor 2 outputs the reset signal 10
It recognizes that it has been activated by 1, and executes the initialization program to initialize the interface controller 3 and the arithmetic processing circuits 6 and 7.

On the other hand, if the state value from the reset instruction storage circuit 10 is "1", the microprocessor 2 receives the reset instruction signal 11 from the microprocessor down detection circuit 4.
Recognizes that it was started by 2 and suppresses the execution of the default program. As a result, the interface controller 3 and the arithmetic processing circuits 6 and 7 are not initialized, so that each circuit retains the state before the failure.

After this, from the other arithmetic processing units connected to the inter-device interface 100, the arithmetic processing circuit 6,
By outputting the transfer instruction of the state value of 7, the state values of the arithmetic processing circuits 6 and 7 before the occurrence of the fault are transferred to another arithmetic processing device via the inter-device interface 100. Therefore, since the state in which the failure has occurred can be read from the arithmetic processing unit 9, it is possible to easily analyze the cause of the failure.

FIG. 4 is a block diagram showing the configuration of another embodiment of the present invention. In the figure, an arithmetic processing unit 11 according to another embodiment of the present invention sequentially stores addresses on an address bus 120 to trace the operation of the microprocessor 2 and outputs a tracer enable instruction signal 121 from a reset instruction storage circuit 10. The structure is the same as that of the other embodiment of the present invention except that the address tracer 12 for performing the trace operation is provided, and the same components are designated by the same reference numerals. The operation of the same component is also similar to that of the other embodiment of the present invention.

The address tracer 12 performs a trace operation for sequentially storing addresses on the address bus 120 each time the microprocessor 2 reads a program from the ROM 5 via the data bus 110.

When the reset instruction storage circuit 10 stores the state value "0" indicating that the microprocessor 2 has been activated by the reset signal 101, the reset instruction storage circuit 10 outputs the tracer validation instruction signal 121. Since "0" is input, the address tracer 12 performs the above trace operation.

When the reset instruction storage circuit 10 stores the state value "1" indicating that the microprocessor 2 is activated by the reset instruction signal 112, the reset instruction storage circuit 10 issues a tracer activation instruction. Since "1" is input as the signal 121, the address tracer 12 does not perform the above trace operation. Therefore, when the microprocessor 2 is activated by the inter-device interface reset signal 111, the address tracer 1
The contents of 2 are never updated.

After this, by outputting a transfer command of the contents of the address tracer 12 from another arithmetic processing unit connected to the inter-device interface 100, it is possible to detect the occurrence of a failure stored in the address tracer 12. The address data is transferred to another arithmetic processing unit via the inter-device interface 100. Therefore, since the state in which the failure has occurred can be read from the arithmetic processing unit 11,
The cause of the failure can be easily analyzed.

The microprocessor down detection circuit 4
The reset instruction signal 112 from the above may be used as it is as the tracer validation instruction signal 121 to the address tracer 12. In this case, if the contents of the address tracer 12 are not updated, it does not matter even if each circuit in the device is initialized.

FIG. 5 is a block diagram showing another embodiment of the present invention. In the figure, an arithmetic processing unit 13 according to still another embodiment of the present invention includes a reset instruction selection memory circuit 14 and AND circuits 15 to 17 for selecting which of the arithmetic processing circuits 21 to 23 is to be initialized. The configuration is the same as that of the embodiment of the present invention except that OR circuits 18 to 20 are provided, and the same components are designated by the same reference numerals. The operation of the same component is also the same as that of the embodiment of the present invention.

A circuit to be initialized by the microprocessor 2 via the data bus 110 is previously set in the reset instruction selection storage circuit 14, and "0" or "0" is given to the reset valid signals 131 to 133 according to the set contents. "1"
Is output.

The AND circuits 15 to 17 are reset instruction signals 112 from the microprocessor down detection circuit 4 and reset valid signals from the reset instruction selection storage circuit 14, respectively.
AND with 131 to 133 and reset instruction signal 134 to 1
36 is output to the OR circuits 18 to 20.

The OR circuits 18 to 20 have reset signals 10 respectively.
1 and reset instruction signal 134 from AND circuits 15-17
~ 136 and reset signal inside the device 137 ~ 139
Is output to the arithmetic processing circuits 21 to 23.

That is, when the reset signal 101 becomes valid, all the in-apparatus reset signals 137 to 139 become valid and the arithmetic processing circuits 21 to 23 are all initialized. Further, when the reset instruction signal 112 from the microprocessor down detection circuit 4 becomes valid, the arithmetic processing circuits 21 to 21 set in the reset instruction selection storage circuit 14
Only the in-apparatus reset signals 137 to 139 corresponding to 23 are valid, and only the arithmetic processing circuits 21 to 23 set in the reset instruction selection storage circuit 14 are initialized.

For example, if the microprocessor 2 sets the arithmetic processing circuit 21 in the reset instruction selection storage circuit 14 because it is a failure at the time of restart unless it is initialized,
"1" is output to the reset valid signal 131, and "0" is output to the other reset valid signals 132 and 133.

In this state, when the inter-device interface reset signal 111 becomes valid and the reset instruction signal 112 from the microprocessor down detection circuit 4 becomes valid, only the reset instruction signal 134 from the AND circuit 15 becomes valid, and The reset instruction signals 135 and 136 from the AND circuits 16 and 17 are invalidated.

Therefore, from the OR circuit 18 to the arithmetic processing circuit 2
The in-device reset signal 137 output to 1 becomes valid,
Only the arithmetic processing circuit 21 is initialized. Other OR circuit 1
Since the in-device reset signals 138 and 139 output from the arithmetic processing circuits 22 and 23 from 9 and 20 become invalid, the arithmetic processing circuits 22 and 23 are not initialized and the arithmetic processing circuits 22 and 2 are not initialized.
No. 3 remains as it was when the failure occurred.

As a result, the arithmetic circuit 21 to be initialized
23 to 23 are set in the reset instruction selection storage circuit 14, internal device reset signals to the arithmetic processing circuits 21 to 23 are set.
137 to 139 can be selectively enabled, and the arithmetic processing circuits 21 to 23 can be selectively initialized.

Therefore, the arithmetic processing circuits 21 and 2 are restarted.
Of the three, only the minimum required circuit can be selectively initialized. Since the setting in the reset instruction selection storage circuit 14 is performed by the microprocessor 2, RO
By changing the program in M5, the initialization target can be easily changed. Therefore, if the initialization of the circuit necessary for the analysis of the cause of the failure after the restart is suppressed, the analysis of the cause of the failure can be easily performed.

As described above, when the in-device interface reset signal 111 becomes valid, the in-device reset signal 113 is made valid only when the microprocessor down detection circuit 4 detects that the microprocessor 2 is inoperable. As a result, among the plurality of arithmetic processing units connected to the inter-device interface 100, only the arithmetic processing unit 1 in which the microprocessor 2 is inoperable can be selectively restarted.

When the reset instruction storage circuit 10 stores that the microprocessor 2 has been activated by the inter-device interface reset signal 111, the arithmetic processing circuits 6 and 6 are included in the program executed by the microprocessor 2 after the activation. By not performing the initial setting of 7, it is initialized by outputting an instruction to transfer the state value of the arithmetic processing circuits 6 and 7 from another arithmetic processing device connected to the inter-device interface 100. The state values of the unprocessed arithmetic processing circuits 6 and 7 can be transferred to another arithmetic processing device, and the cause of failure occurrence after restart can be easily analyzed.

Further, when the microprocessor 2 is activated by the inter-device interface reset signal 111, the trace operation of the address tracer 12 for tracing the operation of the microprocessor 2 is suppressed so that the inter-device interface 100 can be implemented. By outputting an instruction to transfer the contents of the address tracer 12 from another connected arithmetic processing unit, the contents of the address tracer 12 not updated can be transferred to another arithmetic processing unit, and after restarting The cause of failure can be easily analyzed.

Furthermore, when the inter-device interface reset signal 111 becomes valid, only the arithmetic processing circuits 21 to 23 set in the reset instruction selection storage circuit 14 are activated so that the arithmetic processing circuit 21 is restarted. ~
Only the minimum necessary circuit out of 23 can be selectively initialized, and the initialization target can be easily changed by changing the program in the ROM 5. Therefore, if the initialization of the circuit necessary for the analysis of the cause of the failure after the restart is suppressed, the analysis of the cause of the failure can be easily performed.

[0047]

As described above, according to the arithmetic processing unit of the present invention, the microprocessor is activated in response to a reset signal from the outside only when a failure is detected in the microprocessor. The effect is that only the device in which the microprocessor is inoperable can be selectively restarted.

Further, according to another arithmetic processing apparatus of the present invention, it is stored which one of the reset operation of the apparatus and the reset signal from the outside has activated the microprocessor, and the apparatus is responsive to the stored contents. By executing the initialization of each circuit inside, there is an effect that the cause of failure occurrence can be easily analyzed after the restart.

Further, according to another arithmetic processing unit of the present invention, when the microprocessor is started by a reset signal from the outside, the trace operation to the microprocessor is suppressed, so that the failure occurs after the restart. There is an effect that the cause can be easily analyzed.

Further, according to still another arithmetic processing unit of the present invention, by activating only the circuit designated in advance when the reset signal from the outside becomes effective, the minimum time is required for restarting. Only necessary circuits can be selectively initialized, and it is possible to easily change the initialization target by changing the program, so it is possible to easily analyze the cause of failure after restart. effective.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a microprocessor down detection circuit of FIG.

FIG. 3 is a block diagram showing the configuration of another embodiment of the present invention.

FIG. 4 is a block diagram showing the configuration of another embodiment of the present invention.

FIG. 5 is a block diagram showing the configuration of still another embodiment of the present invention.

[Explanation of symbols]

 1, 9, 11, 13 Arithmetic processing device 2 Microprocessor 4 Microprocessor down detection circuit 5 ROM 6,7,21-23 Arithmetic processing circuit 8,18-20 OR circuit 10 Reset instruction storage circuit 12 Address tracer 14 Reset instruction selection Storage circuit 15 to 17,43 AND circuit 41 Processor down detection timer 42 Processor down detection flip-flop

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical display location G06F 15/78 510 P 7530-5L

Claims (4)

[Claims] 1. An arithmetic processing device having a microprocessor which is activated in response to a reset operation of the device and a reset signal from the outside, the detecting device detecting an occurrence of a fault in the microprocessor, and the detecting device. And a means for determining validity / invalidity of the reset signal according to the detection result of 1. 2. A storage unit that stores which of the reset operation and the reset signal the microprocessor has activated, and initialization of each circuit in the device according to the stored contents of the storage unit. The arithmetic processing unit according to claim 1, further comprising: 3. A trace means for tracing the operation of the microprocessor, and a means for suppressing the trace operation of the trace means when the microprocessor is activated by the reset signal. The arithmetic processing unit according to claim 1 or claim 2. 4. The arithmetic processing device according to claim 1, further comprising means for activating only a predesignated circuit when the reset signal becomes valid.