JP3062124B2 - Microprocessor development support equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a microprocessor development support device, and more particularly to a microprocessor development support device for emulating an interrupt processing program in real time.

[0002]

2. Description of the Related Art In the development of microcomputer-applied equipment (target system), a development support system for system debugging and system evaluation substitutes a function of a microprocessor included in the target system, that is, emulation of a target microprocessor. ) While debugging the system.

[0003] The microprocessor development support device is also called an emulator, and includes a microprocessor equivalent to the target microprocessor. The microprocessor executes a user program to be debugged and controls the target system on behalf of the target microprocessor. At this time, the control state by arbitrarily changing the contents of the user program through the host system is traced, and the trace result can be confirmed at a preset breakpoint, thereby supporting software debugging of the target system.

[0004] As this kind of debug target software, there is an interrupt processing program. Generally, interrupt processing occurs independently of the operation of the interrupted microprocessor program, that is, the operation of the interrupted program. Therefore, if there is no countermeasure, the interrupt processing and the operation of the interrupted program interfere with each other,
Problems such as the interrupted program operation being disturbed and the interrupt processing not operating properly occur.

Conventionally, analysis of a problem relating to mutual interference between an interrupt processing program and an interrupted program has been performed because the interrupt processing program is generated independently of the operation of the interrupted program as described above. It was difficult to analyze on a processor development support device. In particular, it is very difficult to emulate an interrupt processing program in which normal operation cannot be expected unless it is connected to an external circuit in real time.

Japanese Unexamined Patent Application Publication No. 2-207 has solved the above problem.
Reference is made to FIG. 4, which shows a block diagram of a conventional first microprocessor development support device described in Japanese Patent Publication No. 340, and includes a CPU 1 having a control function equivalent to that of a target CPU, CP
An event detector 2 for monitoring the operation of U1, an internal bus 7 for data transmission, a serial input / output circuit (I / O) 81 connected to an external circuit 15, and an analog / digital conversion circuit (A / D) 82 Peripheral circuit group 8 including terminal 83
And a shared memory 101 for storing access data to the peripheral circuit group 8, and an external host system 102 connected by the shared memory 101.

Next, the operation of the first conventional microprocessor development support device will be described with reference to FIG. 4. First, an interrupt for accessing the peripheral circuit group 8 is intentionally generated on the interrupted program. A place to be caused, that is, a pseudo interrupt state is set in the event detector 2 in advance. When detecting the pseudo interrupt state, the event detector 2 supplies the event signal EV to the CPU 1 as an operation interruption signal. Thereafter, the host system 1 stores the memory image as if the peripheral circuit group 8 was accessed.
02 to the shared memory 101. Then the CPU
1 is given a signal for resuming operation.

With this series of operations, the peripheral circuit group 8 is not operated and no actual interrupt is generated.
This is a technology that makes it appear as if an interrupt occurs and interrupt processing has been executed.

[0009] Similarly, Japanese Patent Laid-Open No.
FIG. 5 is a block diagram of a second conventional microprocessor development support device disclosed in Japanese Patent Application Laid-Open No. 7-73045, in which constituent elements common to FIG. The second microprocessor development support device includes a CPU 1, an event detector 2, and an internal bus 7 which are common to the first microprocessor development support device of the related art.
And an interrupt control circuit 4 for generating an interrupt signal IR in response to the supply of the event signal EV output from the event detector 2.

Next, the operation of the second conventional microprocessor development support apparatus will be described with reference to FIG. 5. The event detector 2 detects the pseudo interrupt state similar to the first conventional technique. In response to the event signal EV, the interrupt control circuit 4 generates an interrupt signal IR in response to the supply of the event signal EV, and supplies the interrupt signal IR to the CPU 1.

The purpose of the first and second conventional microprocessor development support devices described above is to realize that a pseudo interrupt state is generated at an arbitrary position of an interrupted program in a pseudo interrupt state, thereby enabling a designer However, it is possible to analyze whether or not the interrupted program can normally operate with respect to the portion of the program that is likely to cause a problem when the interrupt processing occurs or the operation of the location where the high-frequency interrupt processing occurs.

[0012]

In the above-mentioned first conventional microprocessor development support apparatus, the CPU is stopped immediately before interrupt processing, and during that time, the host system generates a pseudo memory image after the interrupt processing in the shared memory. By doing so, the actual interrupt is not input to the CPU, so that the operation does not match the hardware operation in the CPU when the interrupt actually occurs, so that the result is not always the same as the actual operation. There were drawbacks.

Also, since no interrupt is generated, the CPU
Had the disadvantage that it did not execute the interrupt program.

Further, there is a disadvantage that real-time execution cannot be performed because the CPU is interrupted.

In the second conventional microprocessor development support device, an interrupt is generated independently of peripheral circuits, but access to the peripheral circuits is not considered at all. Therefore, the interrupt processing program operates normally. There was a disadvantage that it did not.

As described above, the first and second conventional microprocessor development support devices have a common problem that the interrupted program side can be analyzed, but the interrupt processing program side cannot. .

An object of the present invention is to solve the above-mentioned drawbacks, to input an interrupt to the CPU without connecting to an external circuit, to execute an interrupt processing program in real time by the interrupt, and to execute the interrupt processing program. An object of the present invention is to provide a microprocessor development support device capable of accessing peripheral circuits without any contradiction during execution.

[0018]

According to the present invention, there is provided a microprocessor development support apparatus comprising: a CPU having a control function equivalent to that of a target CPU; and an interrupt for generating an interrupt signal to the CPU in response to supply of an interrupt request signal. Control means; and at least one peripheral circuit for generating the interrupt request signal corresponding to the interrupt state.
A micro processor for emulating a microprocessor which executes the processing of the software corresponding to the interrupt request signal by temporarily suspending the processing of the software being executed by the CPU by receiving the interrupt request signal from the peripheral circuit to the PU. In the processor development support device, an event detecting means for monitoring the operation of the CPU and outputting an event signal in response to detection of an event corresponding to a predetermined interrupt state for the CPU;
Interrupt integrating means for setting which of the interrupt request signals from each of the peripheral circuits is simulated by the event signal, outputting a corresponding integrated interrupt request signal and supplying the integrated integrated request signal to the control means; and Access detecting means for detecting a predetermined access in response to a match between a peripheral access to a peripheral circuit and a previously stored access and outputting an access detection signal; and determining predetermined access data of each of the peripheral circuits to be replaced as replacement data An alternative memory for storing the peripheral circuit and the alternative memory exclusively in response to the supply of the access detection signal;
A switch means for connecting to a transmission bus to the U and event detection means, and an address counter for updating a read address value of the alternative memory in response to the supply of the access detection signal.

[0019]

FIG. 4 shows an embodiment of the present invention.
Referring to FIG. 1, in which the same components are denoted by the same reference characters / numbers and similarly indicated by blocks, the microprocessor development support apparatus of this embodiment shown in FIG. A CPU 1 having a control function equivalent to a common target CPU with the processor development support device;
An event detector 2 for monitoring the operation of the PU 1, an internal bus 7 for data transmission, a serial input / output circuit (I / O) 81 connected to an external circuit 15, and an analog / digital conversion circuit (A / D) 82 , A peripheral circuit group 8 including a terminal 83, and an event signal E from the event detector 2.
V is the serial I / O 81, A / D 82,
An interrupt integrator 3 that sets which of the interrupt request signal groups RIG from each of the terminals 83 is to be simulated and outputs an interrupt integrated signal SI, and generates an interrupt signal IR in response to the supply of the interrupt integrated signal SI and generates a CPU 1 And the internal bus 7 and the serial I / O in response to the supply of the coincidence signal CA from the access detector 10.
A switch group 9 including switches 91, 92, and 93 for connecting and disconnecting O81, A / D, and terminal 83 so as to directly connect each of them, and a serial I / O 81,
The alternative memory 10 storing the access data DA of each of the A / D 82 and the terminal 83 in the order requested by the program and the access data DA of the alternative memory 10 to the internal bus 7 in response to the supply of the inverted signal of the coincidence signal CA. A switch 11 for interrupting connection and an inverter 12 for inverting the coincidence signal CA
An access detector 13 that detects an access and outputs a match signal CA; and an address counter that is cleared in response to the supply of a clear signal CR and outputs an address signal A to the alternative memory 10 in response to the supply of the match signal CA 14.

Next, the operation of the present embodiment will be described with reference to FIG. 1 and FIG. 2 which is a flowchart showing an example of a processing program according to the present embodiment. Access data to the peripheral circuit group 8 to be replaced in the future is stored in the memory 10 in the order required by the program. Here, for convenience of explanation, a specific description will be given assuming a serial I / O 81 as an example of data of the peripheral circuit group 8 stored in the alternative memory 10. FIG. 2 is a flowchart showing a serial data reception processing program of the serial I / O 81.

Referring also to FIG. 2, this processing flow is based on the interrupt request signal RIG from the serial I / O 81.
From the point at which the CPU 1 automatically starts the interrupt processing program based on.

First, in step S1, a reception status value is read from the reception status address.

Next, in step S2, the reception status value is determined, and if this determination result indicates normal reception, the process proceeds to step S3. If the result of the determination indicates a bad reception, the process proceeds to step S4.

At step S3, an operation for taking in the reception data from the reception data storage address is performed, and at step S4
Proceed to.

In step S4, the serial data receiving program ends and the program returns to the main program.

As a set value for the alternative memory 10 according to the flowchart of FIG. 2, a normal reception value is stored as a reception status value at the address 0 of the alternative memory 10.
The received data is stored at the next address 1. This setting is equivalent to the normal data setting.

The case of data setting in an abnormal system will be described. In FIG. 2, for example, when it is assumed that normal reception is performed after six consecutive bad receptions, address 0 of the substitute memory 10 is assumed. , The defective received value is stored from address 5 to address 5, and the normal received value is stored at address 6. Further, it can be realized by storing the received data at address 7.

That is, the operation of the alternative memory 10 can be realized with a simple configuration for outputting data in accordance with the address A from the address counter 14.

Next, the access detector 13 stores a list of addresses of the peripheral circuit group 8.

Next, the operation state of the CPU 1 for generating an interrupt is set in the event detector 2, and the event signal E supplied from the event detector 2 to the interrupt integrator 3 is set.
V is set to which of the peripheral circuits in the peripheral circuit group 8 is to be used as the integrated interrupt signal SI corresponding to the request. For example, a setting is made so as to output the integrated interrupt signal SI in response to the interrupt request signal RIG of the serial I / O 81.

Finally, the clear signal CR is input to the address counter 14, and the address signal A to the substitute memory 10 is set to an initial set value 0.

After making all of these settings, the CPU
1 is set to the operating state. When the CPU 1 is set by the event detector 2, the event detector 2 outputs an event signal EV and supplies it to the interrupt integrator 3. The interrupt integrator 3 outputs an integrated interrupt signal SI corresponding to the previously set interrupt request signal RIG,
A. In this example, an integrated interrupt signal SI is output in response to the interrupt request signal RIG of the serial I / O 81. The interrupt control circuit 4A outputs an interrupt signal IR in response to the supply of the integrated interrupt signal SI,
Supply to U1. The software (program) being executed by the CPU 1 in response to the supply of the interrupt signal IR is:
Start execution of the interrupt processing part.

On the other hand, when the CPU 1 accesses the peripheral circuit group 8 according to the program, the access detector 1
3 outputs the coincidence signal CA. Only the switch 11 corresponding to the alternative memory becomes valid in response to the supply of the inverted signal of the coincidence signal CA, and the switch group 9 corresponding to the other peripheral circuit group 8 becomes invalid in response to the supply of the coincidence signal CA. at the same time,
The address counter 14 counts up in response to the supply of the coincidence signal CA, outputs the address signal A, and supplies it to the alternative memory 10. According to the value of the address signal A, the alternative memory 10 supplies the above-described setting data to the CPU 1 via the switch 11 and the internal bus 7.

By the above-described series of operations, the CPU 1 receives the interrupt signal IR, and obtains data from the CPU 1 as if the access to the peripheral circuit group 8 was operating normally.

Further, in the above series of operations, C
There is no need to suspend PU1. Next, a second embodiment of the present invention will be described with reference to FIG. 3, which is similar to FIG. This embodiment differs from the first embodiment in that the maximum value detector 1 monitors the address signal A and generates a clear signal CR when the maximum value is detected.
6 is provided.

When it is desired to execute a program operation in a specific pattern, there is a method of embedding repetitive data of the specific pattern in the alternative memory 10 to fill the memory. In this embodiment, however, the address signal A is monitored and the maximum address is monitored. Is realized by generating a clear signal CR.

The difference between the operation of the present embodiment and the first embodiment will be described with reference to FIG. 3. The maximum value detector 16 monitors the address signal A from the address counter 14 and If the address is determined, a clear signal CR is generated.

Thus, for example, when it is desired to handle a 10-byte data pattern, it is easy to set only 10-byte data in the substitute memory 10 and set a value of 10 in the maximum value detector 16. Infinite repetition is possible.

A typical microprocessor development support device is equipped with a plurality of event detectors.
An equivalent function can be realized by using one in place of the address detector.

Also, a terminal for enabling or disabling the operation is prepared for the peripheral circuit itself without using a switch for exclusively controlling the alternative memory and the peripheral circuit, and a coincidence signal from the address detector is connected. By doing so, equivalent functions can be realized.

[0041]

As described above, the microprocessor development support apparatus of the present invention comprises an interrupt integrating means for setting which of the interrupt request signals from the peripheral circuits is simulated by the event signal, and an access detecting means. A replacement memory for storing access data of a peripheral circuit to be replaced as replacement data in a predetermined order, and a switch for exclusively connecting the peripheral circuit and the replacement memory to an internal bus in response to supply of an access detection signal Means and an address counter for updating an address value, so that an interrupt signal to the CPU can be input without connecting to an external circuit, and the interrupt signal is used to execute the interrupt processing program in real time. Access from the CPU to peripheral circuits during the execution of There is a result.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a microprocessor development support device of the present invention.

FIG. 2 is a flowchart illustrating an example of an operation in the microprocessor development support device of the present embodiment.

FIG. 3 is a block diagram showing a second embodiment of the microprocessor development support device of the present invention.

FIG. 4 is a block diagram showing an example of a first conventional microprocessor development support device.

FIG. 5 is a block diagram showing an example of a second conventional microprocessor development support device.

[Explanation of symbols]

 Reference Signs List 1 CPU 2 event detector 3 interrupt integrator 4, 4A interrupt control circuit 7 internal bus 8 peripheral circuit group 9 switch group 10 alternative memory 11, 91 to 93 switch 12 inverter 13 access detector 14 address counter 15 external circuit 16 maximum value Detector 81 Serial I / O 82 A / D conversion circuit 83 Terminal 101 Shared memory 102 Host system

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 11/22-11/26 G06F 9/46

Claims (2)

(57) [Claims] A CPU having a control function equivalent to that of a target CPU; interrupt control means for generating an interrupt signal to the CPU in response to supply of an interrupt request signal; And at least one peripheral circuit that generates
A microprocessor for emulating a microprocessor that temporarily suspends processing of software being executed by the CPU by receiving the interrupt request signal from the peripheral circuit and executes processing of the interrupt request signal corresponding portion of the software. In the development support device, an event detection unit that monitors an operation of the CPU and outputs an event signal in response to detection of an event corresponding to a predetermined interrupt state for the CPU; and the interrupt request signal from each of the peripheral circuits. Interrupt integration means for setting which of the event signals is simulated, outputting a corresponding integrated interrupt request signal and supplying the integrated interrupt request signal to the control means, and peripheral access and pre-stored access from the CPU to the peripheral circuit. Predetermined access in response to a match Access detection means for detecting and outputting an access detection signal; an alternative memory for storing access data of each of the peripheral circuits to be replaced as alternative data in a predetermined order; and the peripheral circuit in response to the supply of the access detection signal Switch means for exclusively connecting the alternative memory to a transmission bus to the CPU and event detecting means; and an address counter for updating a read address value of the alternative memory in response to the supply of the access detection signal. A microprocessor development support device comprising: 2. The microcontroller according to claim 1, further comprising: a read address maximum value detecting means for monitoring the read address value and clearing the address counter in response to detection of the maximum read address value. Processor development support device.