JPH07225700A - In-circuit emulator - Google Patents

Abstract

PURPOSE:To provide an in-circuit emulator for executing a monitoring program and enabling debugging. CONSTITUTION:This emulator is provided with a comparator 5 for comparing an instruction address 6 outputted by an MPU 1 with a comparison value 15 and outputting coincidence detection signals 10, a memory 2 provided with a function for prohibiting data output by interruption signals 8 for outputting the data of a pertinent address corresponding to the instruction address 6 from the MPU 1, an FIFO memory 3 provided with the function for permitting the data output by the interruption signals 8 for outputting data in synchronism with synchronous signals 9 from a control part 4 and the control part 4 for inputting the coincidence detection signals 10 and outputting the interruption signals 8 and the synchronous signals 9.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an in-circuit emulator capable of executing a monitor program and debugging in an MPU having no interrupt function.

[0002]

2. Description of the Related Art Generally, an in-system for debugging hardware or software of a system using an MPU.
In the circuit emulator, a monitor program is used to confirm the status of registers and memories.

In debugging, a breakpoint is set and a user program is executed. When the executed program reaches a breakpoint, the MPU is interrupted and the monitor program is executed or step-executed, and the state at that time is checked. To do. When the monitor program ends, the user program is re-executed for debugging.

As described above, in order to use the monitor program for debugging, it is necessary to interrupt the MPU. When an interrupt occurs, the MPU stacks the value of the program counter on the stack, reads the start address of the interrupt processing routine from the interrupt vector, sets it in the program counter, and executes the interrupt processing routine. In this interrupt processing routine, the states of registers, memories, etc. are checked, and when the interrupt processing routine ends, the address saved in the stack is set in the program counter and the normal routine is restored. Therefore, the monitor program can be executed by setting the start address in which the monitor program is stored in the interrupt vector in advance.

[0005]

However, in the conventional configuration as described above, in the MPU having the interrupt function, the execution address is saved in the stack at the time of the interrupt, and the operation is branched to the interrupt vector. It was possible to execute the monitor program by storing the monitor program in a different address space. However, the MPU having no interrupt function has a problem that the monitor program cannot be executed because the instruction address cannot be changed by the interrupt process.

SUMMARY OF THE INVENTION The present invention has been made in consideration of such a problem in debugging an MPU having no conventional interrupt function, and an object of the present invention is to provide an in-circuit emulator capable of executing a monitor program for debugging. Is.

[0007]

According to the present invention, a memory for storing a second program, a comparison value setting means for setting an interrupt address for executing the first program as a comparison value, and an output from an MPU. A comparator that compares the instruction address of the second program with the comparison value, a control unit that outputs an interrupt signal and a synchronization signal when the comparison result address matches, and outputs the data of the first program. An in-circuit emulator that includes a data output unit, the memory stops outputting the data of the second program in response to the interrupt signal, and the data output unit outputs the data in synchronization with the synchronization signal in response to the interrupt signal. is there.

[0008]

According to the present invention, when the instruction address of the second program output from the MPU reaches the comparison value, the execution of the second program is interrupted and the first address is output regardless of the instruction address output from the MPU. When the program is executed and the return address to the second program is reached during the execution of the first program, the first program is stopped and the execution of the second program is returned to, so that there is no interrupt function.
The PU can be debugged.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings showing its embodiments. (Embodiment 1) FIG. 1 is a block diagram of an in-circuit emulator according to a first embodiment of the present invention. In FIG. 1, 1 is an MPU that does not have an interrupt function to be debugged, 2 is a memory that stores a user program,
3 is a FIFO memory for storing a monitor program, 4 is a control unit for controlling program switching, and 5 is an M
It is a comparator that compares the instruction address output from PU1 with the address of the set comparison value. An instruction address 6 is output from the MPU 1 and is input to the memory 2 and the comparator 5. Reference numeral 7 is instruction data, which is the memory 2 and the FIFO.
It is output from the memory 3 and input to the MPU 1. Reference numeral 8 denotes an interrupt signal output from the control unit 4, which includes the memory 2 and the F
It is input to the IFO memory 3. Reference numeral 9 is a synchronization signal output from the control unit 4, and is input to the MPU 1 and the FIFO memory 3. Reference numeral 10 denotes a coincidence detection signal output from the comparator 5, which is input to the control unit 4. 11 is a console for setting a monitor program, 12 is a console 1
The write signal is output from 1 and is input to the FIFO memory 3. A reset signal 13 is output from the console 11 and is input to the FIFO memory 3. Reference numeral 14 is a data line for setting a monitor program, which is output from the console 11 and input to the FIFO memory 3. 15
Is a comparison value (address indicating a breakpoint), which is output from the console 11 and input to the comparator 5. Reference numeral 16 is a control signal output from the console 11, which is input to the control unit 4 and designates execution permission of the synchronization signal 9 and ON / OFF of the output of the interrupt signal 8.

The above-mentioned console 11 constitutes the comparison value setting means, and the FIFO memory 3 constitutes the data output means. The monitor program is the first program and the user program is the second program.

Next, the operation of the in-circuit emulator configured as described above will be described with reference to FIG.

First, the console 11 outputs the comparison value 15 to the comparator 5. Next, the reset signal 13 causes the FIF
After resetting the O memory 3, the write signal 12 causes
A monitor program including a jump instruction to the same instruction address as the comparison value is stored in the FIFO memory 3 via the data line 14. Then, from the console 11 to the control unit 4,
When execution is designated by the control signal 16, the control unit 4 outputs the synchronization signal 9. As a result, the MPU 1 starts operating and the instruction address 6 is output. And memory 2
Outputs the instruction data 7 to the MPU 1 according to the instruction address 6, and the user program is executed.

When the comparator 5 recognizes a match between the instruction address 6 and the comparison value 15 during execution of the user program, the control unit 4
The coincidence detection signal 10 is output to. When the coincidence detection signal 10 is input, the control unit 4 stops the synchronization signal 9 and stops the MPU 1
Stop the operation of.

Next, an interrupt signal is designated from the console 11 to the control unit 4 by the control signal 16 and the interrupt signal 8 is output. As a result, the data output of the memory 2 is prohibited and the data output of the FIFO memory 3 is permitted. After that, when execution is designated by the control signal 16 from the console 11 to the control unit 4, the synchronization signal 9 is output from the control unit 4 and the read pointer of the FIFO memory 3 is raised. As a result, the instruction data 7 is synchronized with the synchronization signal 9.
Is output from the FIFO memory 3 and the monitor program is executed.

Next, when the jump instruction to the same instruction address as the comparison value 15 included in the monitor program is executed during execution of the monitor program, the instruction address is output from the MPU 1 and the instruction is issued by the comparator 5. A match between the address 6 and the comparison value 15 is recognized, and the match detection signal 10 is output. When the coincidence detection signal 10 is input again, the control unit 4 stops the synchronization signal 9 and stops the operation of the MPU 1.

Next, the console 11 releases the designation of the interrupt to the control unit 4 by the control signal 16 and stops the output of the interrupt signal 8. As a result, the data output of the FIFO memory 3 is prohibited and the data output of the memory 2 is permitted. Then, the console 11 instructs the control unit 4 to execute the control signal 16 to restart the execution of the user program.

As described above, in this embodiment, the function of comparing the instruction address 6 from the MPU 1 with the comparison value 15 and outputting the coincidence detection signal 10 and the function of inhibiting the data output by the interrupt signal 8 are described. And a FIFO memory 3 having a function of outputting data at the corresponding address according to the instruction address 6 from the MPU 1 and a function of permitting data output by an interrupt signal 8 and outputting data in synchronization with a synchronization signal 9. And the control section 4 which receives the coincidence detection signal 10 and outputs the interrupt signal 8 and the synchronization signal 9, the execution of the user program is interrupted when the specified address is reached, and the monitor program is executed regardless of the instruction address. By executing, it is possible to perform debugging in the MPU that does not have the interrupt function. (Embodiment 2) FIG. 2 is a configuration diagram of an in-circuit emulator according to a second embodiment of the present invention. In FIG. 2, 1 is an MPU, 2 is a memory for storing a user program, 4 is a control unit, and 5 is a comparator. Reference numeral 17 is a tristate buffer, and 18 is a register for storing instruction data.

An instruction address 6 is output from the MPU 1 and is input to the memory 2 and the comparator 5. Reference numeral 7 is instruction data, which is output from the register 18 via the memory 2 and the tristate buffer 17 and input to the MPU 1. Reference numeral 8 denotes an interrupt signal output from the control unit 4, which is input to the memory 2 and the tristate buffer 17.
Reference numeral 9 is a synchronization signal output from the control unit 4 and input to the MPU 1. Reference numeral 10 denotes a coincidence detection signal output from the comparator 5, which is input to the control unit 4. Reference numeral 11 is a console, and 12 is a write signal output from the console 11, which is input to the register 18. Reference numeral 14 is a data line for setting a monitor program, which is output from the console 11 and input to the register 18. 15 is a comparison value, console 11
And is input to the comparator 5. 16 is a control signal output from the console 11, which is input to the control unit 4,
The permission of execution of the synchronization signal 9 and the step execution and ON / OFF of the output of the interrupt signal 8 are designated.

The above-mentioned tri-state buffer 17 and register 18 constitute data output means.

The configuration of this embodiment is different from that of the first embodiment shown in FIG. 1 in that the FIFO memory 3 for storing the monitor program in FIG. 1 is replaced with a tristate buffer 17 and a register 18, and a control unit is provided. The point is that the interrupt signal 8 output from 4 is input to the enable terminal of the tristate buffer 17 and the reset signal 13 is deleted.

Next, the operation of the in-circuit emulator configured as described above will be described with reference to FIG.

First, the comparison value 15 is output from the console 11 to the comparator 5. Then, when execution is designated by the control signal 16 from the console 11 to the control unit 4, the control unit 4
Outputs the synchronization signal 9. As a result, the MPU 1 starts operating and the instruction address 6 is output. Then, the memory 2 sends the instruction data 7 according to the instruction address 6 to the MPU 1
And the user program is executed.

When the comparator 5 recognizes a match between the instruction address 6 and the comparison value 15 during execution of the user program, the control unit 4
The coincidence detection signal 10 is output to. When the coincidence detection signal 10 is input, the control unit 4 stops the synchronization signal 9 and stops the MPU 1
Stop the operation of.

Next, an interrupt is designated by the control signal 16 from the console 11 to the control unit 4, and the interrupt signal 8 is output. As a result, the data output of the memory 2 is prohibited and the tristate buffer 17 is enabled.

In this state, a command is set in the register 18 by the write signal 12 from the console 11 through the data line 14, and the control signal 1 is sent from the console 11 to the control unit 4.
6 designates one-step execution. As a result, the control unit 4 outputs the synchronization signal 9 for only one step, and M
The instruction data 7 is input to the PU 1 from the register 18 for only one instruction. The monitor program is executed by repeating this.

At the last execution of the monitor program,
A jump instruction to the same instruction address as the comparison value is set in the register 18 from the console 11 via the data line 14, and one-step execution is designated by the control signal 16 from the console 11 to the control unit 4. Accordingly, the comparator 5 recognizes the match between the instruction address 6 and the comparison value 15, and outputs the match detection signal 10 to the control unit 4. When the coincidence detection signal 10 is input again, the control unit 4 stops the synchronization signal 9 and stops the operation of the MPU 1.

Next, the console 11 releases the designation of the interrupt to the control unit 4 by the control signal 16 and stops the output of the interrupt signal 8. As a result, the tristate buffer 17 is disabled and data output from the memory 2 is permitted. Then, the console 11 instructs the control unit 4 to execute the control signal 16 to restart the execution of the user program.

As described above, in the present embodiment, the function of comparing the instruction address 6 from the MPU 1 with the comparison value 15 and outputting the coincidence detection signal 10 and the function of inhibiting the data output by the interrupt signal 8 are described. A memory 2 for outputting data at the corresponding address according to the instruction address 6 from the MPU 1, a tristate buffer 17 for permitting data output by an interrupt signal 8, a register 18 for storing instruction data, and a match detection signal 10 And the control unit 4 which outputs the interrupt signal 8 and the synchronizing signal 9 are input, the execution of the user program is interrupted when the specified address is reached, and the monitor program is executed regardless of the instruction address. Debugging can be performed in an MPU that does not have an interrupt function.

Further, in this embodiment, there is an advantage that the hardware scale can be reduced as compared with the first embodiment by replacing the FIFO memory 3 with the tristate buffer 17 and the register 18.

As described above, when the instruction address output from the MPU reaches the designated address, the execution of the user program is interrupted, and the monitor program can be executed regardless of the instruction address output from the MPU. Debugging can be performed in an MPU that does not have an interrupt function.

[0031]

As is apparent from the above description, the present invention is applied to the case where the comparator for comparing the instruction address of the second program output from the MPU and the comparison value and the comparison result address are matched. A control unit that outputs an interrupt signal and a synchronization signal, and a data output unit that outputs data of the first program, the memory stops outputting data in response to the interrupt signal, and outputs data in response to the interrupt signal. Since the means outputs the data in synchronization with the synchronization signal, it has an advantage that the monitor program can be executed and debugging can be performed.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an in-circuit emulator according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of an in-circuit emulator according to a second embodiment of the present invention.

[Explanation of symbols]

 1 MPU 2 memory 3 FIFO memory 4 control unit 5 comparator 6 instruction address 8 interrupt signal 9 synchronization signal 10 match detection signal 11 console 15 comparison value 16 control signal 17 tristate buffer 18 register

Claims (4)

[Claims] 1. A memory for storing a second program,
Comparison value setting means for setting an interrupt address for executing the first program as a comparison value, a comparator for comparing the instruction value of the second program output from the MPU with the comparison value, and a comparison value thereof. A control unit that outputs an interrupt signal and a synchronization signal when the result addresses match and a data output unit that outputs the data of the first program are provided, and the memory stores the second program in response to the interrupt signal. Is stopped, and the data output means outputs the data in synchronization with the synchronizing signal in response to the interrupt signal. 2. The first program has a return address instruction for returning to the second program, and when the return address instruction is executed, the control unit stops the interrupt signal and the synchronization signal. 2. The in-circuit emulator according to claim 1, wherein the data output means stops outputting data and the execution of the second program in the memory is restarted. 3. The in-circuit device according to claim 1 or 2, wherein the data output means is a memory.
emulator. 4. The in-skit emulator according to claim 1, wherein the data output means is a tristate buffer and a register.