JPH0265395A - Channel diagnosing device - Google Patents
Channel diagnosing deviceInfo
- Publication number
- JPH0265395A JPH0265395A JP21521988A JP21521988A JPH0265395A JP H0265395 A JPH0265395 A JP H0265395A JP 21521988 A JP21521988 A JP 21521988A JP 21521988 A JP21521988 A JP 21521988A JP H0265395 A JPH0265395 A JP H0265395A
- Authority
- JP
- Japan
- Prior art keywords
- channel
- order
- answer
- diagnosis
- communication path
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000003745 diagnosis Methods 0.000 claims abstract description 24
- 238000002405 diagnostic procedure Methods 0.000 claims description 25
- 230000002401 inhibitory effect Effects 0.000 claims 1
- 238000001514 detection method Methods 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 4
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
Landscapes
- Monitoring And Testing Of Exchanges (AREA)
Abstract
Description
【発明の詳細な説明】
[産業上の利用分野コ
本発明は、−重化通話路構成の交換システムの通話路診
断を行なう通話路診断装置に関し、特に、運用中に通話
路の診断試験を行なうことが可能な通話路診断装置に間
する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a communication path diagnostic device for diagnosing communication paths in a switching system having a redundant communication path configuration, and in particular, to a communication path diagnosis device for performing communication path diagnosis during operation. Install a channel diagnostic device that can perform this test.
[従来の技術]
従来、交換システムの通話路の診断試験を行なう通話路
診断装置では、二重化通話路を有するものは通話路がス
タンバイ時に行なっていた。しかし、−重化通話路の運
用中には診断試験を行なうことができなかった。[Prior Art] Conventionally, in a communication path diagnostic device that performs a diagnostic test on a communication path of a switching system, the test is performed when the communication path is on standby in those having a duplex communication path. However, it was not possible to perform diagnostic tests while the -duplex channel was in operation.
[解決すべき課題]
上述した従来の通話路診断装置は、二重化構成の通話路
のスタンバイ側に対してのみ行なうようになっていたた
め、−i化通話路を運用中に診断試験することができな
いという課題があった。[Problems to be Solved] The conventional communication path diagnosis device described above is designed to perform diagnostic tests only on the standby side of a duplexed communication path, so it is not possible to perform diagnostic tests while the -i communication path is in operation. There was a problem.
本発明は、上記課題にかんがみてなされたものて、−重
化通話路でも運用中に診断試験を行なうことが可能な通
話路診断装置の提供を目的とする。The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a communication line diagnostic device that is capable of performing a diagnostic test during operation even on a redundant communication line.
[=!!届の解決手段]
上記目的を達成するため、本発明の通話路診断装置は、
−重化通話路構成の交換システムの通話路診断を行なう
通話路診断装置において、空通話路を検出して診断試験
を行なう空通話路診断試験手段と、この空通話路診断試
験手段が通話路診断試験を開始すると通話路診断試験が
終了するまでパス設定オーダをインヒビットするパス設
定オーダインヒビット手段と、同じく空通話路診断試験
手段が通話路診断試験を開始すると処理装置から受信し
た次のオーダに対して、通話路診断試験が終了するまで
パス設定オーダ送出を待ち合わせさせるアンサを返送す
るパス設定オーダ送出待合アンサ返送手段とを備えた構
成としである。[=! ! Means for solving the problem] In order to achieve the above object, the communication path diagnosis device of the present invention has the following features:
- In a communication path diagnosis device for performing communication path diagnosis in a switching system having a duplex communication path configuration, the communication path diagnosis test means detects an empty communication path and performs a diagnostic test; When the diagnostic test is started, the path setting order inhibit means inhibits the path setting order until the call path diagnostic test is completed; On the other hand, the configuration includes path setting order sending waiting answer returning means for returning an answer for waiting for sending out a path setting order until the channel diagnostic test is completed.
[実施例コ 以下、図面にもとづいて本発明の詳細な説明する。[Example code] Hereinafter, the present invention will be explained in detail based on the drawings.
第1図は、本発明の一実施例に係る通話路診断装置のブ
ロック図、第2図は第1図の通話路診断装置における制
御部のブロック図である。FIG. 1 is a block diagram of a communication path diagnosis device according to an embodiment of the present invention, and FIG. 2 is a block diagram of a control section in the communication path diagnosis device of FIG.
第1図において、lは処理装置(CC)、2は制御部(
○DER)、3は通話路メモリ(S PMM)、4は診
断試験回路(T E S T)である。In FIG. 1, l is a processing unit (CC), 2 is a control unit (
○DER), 3 is a speech path memory (SPMM), and 4 is a diagnostic test circuit (TEST).
また、第2図において、5はアドレス制御ゲート、6は
データ制御ゲート、7はアドレス/データ制御信号作成
部、8はオーダデコーダ(DEC)、9は制御部タイミ
ング回路(TIM)、10はアンサ制御回路(ANS)
である。In FIG. 2, 5 is an address control gate, 6 is a data control gate, 7 is an address/data control signal generation section, 8 is an order decoder (DEC), 9 is a control section timing circuit (TIM), and 10 is an answer Control circuit (ANS)
It is.
上記構成において、処理装置lは制御部2にオーダ・ア
ドレスとデータを送信し、アンサを受信する。また、制
御部2はオーダデコーダ8の出力により、オーダに応じ
た制御を行なう。この際、パス設定オーダの場合は、ア
ドレス/データ制御信号作成部7で診断試験回路4から
インヒビットされない限りは、アドレス制御ゲート5と
データ制御ゲート6をイネーブルする信号を作成し、通
話路メモリ3の該当アドレスにデータを書き込む。In the above configuration, the processing device 1 transmits an order address and data to the control unit 2, and receives an answer. Further, the control unit 2 performs control according to the order based on the output of the order decoder 8. At this time, in the case of a path setting order, the address/data control signal generator 7 generates a signal that enables the address control gate 5 and the data control gate 6, unless inhibited by the diagnostic test circuit 4, and Write data to the corresponding address.
また、アンサ制御回路lOは制御部タイミング回路9か
らの信号と診断試験回路4からの通知から、アンサ信号
を作成して処理装置1に送信する。Further, the answer control circuit IO creates an answer signal from the signal from the control unit timing circuit 9 and the notification from the diagnostic test circuit 4, and transmits it to the processing device 1.
さて、診断試験を行なう場合は、診断試験回路4が通話
路メモリ3の内容を読み込む。そして、空通話路を検出
するとアドレス/データ制御信号作成部7はパス設定オ
ーダを受信してもアドレス制御ゲート5とデータ制御ゲ
ートをイネーブルしないようにする。Now, when performing a diagnostic test, the diagnostic test circuit 4 reads the contents of the communication path memory 3. When an empty channel is detected, the address/data control signal generator 7 does not enable the address control gate 5 and the data control gate even if it receives a path setting order.
一方、アンサ制御回路10は、次の受信オーダに対して
処理装alがパス設定オーダの送出を通話路診断試験に
要する時間だけ待ち合わせるようなアンサな送信する。On the other hand, the answer control circuit 10 sends an answer such that the processing device al waits for the next received order to send out the path setting order for the time required for the channel diagnosis test.
このようにして、検出した空通話路が使用されることを
防止しつつ、診断試験回路4から通話路診断試験を行な
う。In this way, the diagnostic test circuit 4 performs the communication path diagnostic test while preventing the detected empty communication path from being used.
このように本実施例は、−重化通話路構成の交換システ
ムの通話路診断を行なう通話路診断装置において、通話
路メモリの内容を読んで空通話路を検出し、制御部に通
知した後、当該空通話路に対して診断試験を行なう診断
試験回路と、空通話路検出通知を受信すると処理装置か
らのパス設定オーダを通話診断試験が終了するまでイン
ヒビットするアドレス/データ制御信号作成部と、同じ
く空通話路検出通知を受信すると処理装置から受信した
次のオーダに対して、パス設定オーダ送出を診断試験に
要する時間だけ待ち合わせるよう指示するアンサを返送
するアンサ回路とを備えている・
[発明の効果]
以上説明したように本発明は、通話路メモリの内容を読
んで空通話路を検出し、この空通話路に対して診断試験
を行なうため、−重化通話路でも運用中に診断試験をを
行なうことができ、さらには通話路障害の平明検出が可
能な通話路診断装置を提供できるという効果がある。In this way, the present embodiment is a communication path diagnosis device that performs communication path diagnosis in a switching system having a duplex communication path configuration. , a diagnostic test circuit that performs a diagnostic test on the empty communication path; and an address/data control signal generation unit that inhibits a path setting order from the processing device until the communication diagnostic test is completed upon receiving an empty communication path detection notification. Similarly, when an empty channel detection notification is received, an answer circuit is provided that returns an answer instructing the next order received from the processing device to wait for the time required for the diagnostic test to send out the path setting order. Effects of the Invention] As explained above, the present invention reads the contents of the communication path memory to detect an empty communication path, and performs a diagnostic test on the empty communication path. This has the advantage that it is possible to provide a communication path diagnostic device that can perform diagnostic tests and also can detect communication path failures plainly.
第1図は本発明の一実施例に係る通話路診断装置のプロ
・ツク図、第2図は第1図の通話路診断装置における制
御部のブロック図である。
1:処理装置(CC)
7↓ご診断試験回路(TEST)
7:アトレス/データ制御信号作成部FIG. 1 is a block diagram of a communication path diagnosis device according to an embodiment of the present invention, and FIG. 2 is a block diagram of a control section in the communication path diagnosis device of FIG. 1: Processing unit (CC) 7↓ Diagnostic test circuit (TEST) 7: Atres/data control signal creation section
Claims (1)
通話路診断装置において、空通話路を検出して診断試験
を行なう空通話路診断試験手段と、この空通話路診断試
験手段が通話路診断試験を開始すると通話路診断試験が
終了するまでパス設定オーダをインヒビットするパス設
定オーダインヒビット手段と、同じく空通話路診断試験
手段が通話路診断試験を開始すると処理装置から受信し
た次のオーダに対して、通話路診断試験が終了するまで
パス設定オーダ送出を待ち合わせさせるアンサを返送す
るパス設定オーダ送出待合アンサ返送手段とを具備する
ことを特徴とする通話路診断装置。In a call path diagnosis device that performs call path diagnosis in a switching system having a single call path configuration, the empty call path diagnosis test means detects an empty call path and performs a diagnostic test; When the test is started, the path setting order inhibiting means inhibits the path setting order until the call path diagnosis test is completed; and a path setting order sending waiting answer return means for returning an answer for waiting for sending out a path setting order until the completion of a calling path diagnostic test.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21521988A JPH0265395A (en) | 1988-08-31 | 1988-08-31 | Channel diagnosing device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21521988A JPH0265395A (en) | 1988-08-31 | 1988-08-31 | Channel diagnosing device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0265395A true JPH0265395A (en) | 1990-03-06 |
Family
ID=16668673
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP21521988A Pending JPH0265395A (en) | 1988-08-31 | 1988-08-31 | Channel diagnosing device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0265395A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03267850A (en) * | 1990-03-16 | 1991-11-28 | Nec Corp | Automatic diagnostic test system for vocoder |
-
1988
- 1988-08-31 JP JP21521988A patent/JPH0265395A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03267850A (en) * | 1990-03-16 | 1991-11-28 | Nec Corp | Automatic diagnostic test system for vocoder |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5452443A (en) | Multi-processor system with fault detection | |
JP2996440B2 (en) | Diagnosis method of data processing system | |
US4839895A (en) | Early failure detection system for multiprocessor system | |
JPH02224140A (en) | Interruption testing device | |
JPH0265395A (en) | Channel diagnosing device | |
JP2998804B2 (en) | Multi-microprocessor system | |
JPS6155759A (en) | Interface control device | |
JPH0588933A (en) | Parallel processing system with debugging function | |
KR950022612A (en) | Error detection device and processing method on redundancy board of redundancy device | |
JPH0415834A (en) | Test system for computer | |
JP2685289B2 (en) | Write enable signal check method | |
JPS60140438A (en) | System switching control system of information processing system | |
JPS6158051A (en) | False trouble generating system | |
JPS59121519A (en) | Clock stop control system of input and output controller | |
JP3087481B2 (en) | In-circuit emulator | |
JPH0229833A (en) | Maintenance diagnostic system | |
JPH07225700A (en) | In-circuit emulator | |
JPS63140342A (en) | Test system for error detecting circuit | |
JPH08249200A (en) | Redundant system computer system | |
JPS59116998A (en) | Trouble detecting system of main memory | |
JPS63273950A (en) | Data processor containing duplex memory | |
JPH02135544A (en) | Duplex controller | |
JPS63278147A (en) | Control system for preventing erroneous use of register | |
JPH0594325A (en) | Monitoring controller | |
JPH0496123A (en) | Printer interface circuit |