JPS63278147A - Control system for preventing erroneous use of register - Google Patents

Abstract

PURPOSE:To detect a program error in the initial stage to improve the reliability of software by providing each register with a circuit which indicates that the register can be used or the use of the register is inhibited and detecting whether the register can be used or not. CONSTITUTION:The usable/unusable state of each register 16 is freely set to an invalid state storage circuit 15 by a usable/unusable state change instruction 11. Consequently, the calling side can preliminarily inhibit the use of registers, which should not be used, in a module interface or the like by the usable/ unusable state change instruction 11. If a called module erroneously uses a register, the use of which is inhibited, because of a failure in interface, an error interrupt signal is outputted by an error detecting circuit 17. Since the program interrupt is caused, the program does not run away and the instruction of the interruption cause is checked to detect the error.

Description

[Detailed Description of the Invention] [Summary] By providing a circuit in a computer that instructs each register to be enabled or disabled, and by providing a mechanism that can detect whether a register is allowed or not to be used, module interfaces, etc. to prevent incorrect use of registers.

It is possible to achieve high reliability of software.

[Industrial application field]

The present invention relates to an instruction control circuit for a computer equipped with a plurality of registers that load/store data according to instructions, and particularly relates to a register misuse prevention control system that enables early detection of program errors.

[Conventional technology]

When a program module calls another program module and requests some processing, it sets parameters in a predetermined register.

The contents of the request are communicated. Registers and the like used at this time are defined in advance as a module interface.

In such a module interface.

Even though the calling side has not set anything in a certain register, due to an interface error, the receiver may make a mistake such as using that register on the receiving side. Similarly, when a subroutine is called, register usage errors are likely to occur, and even during the flow of processing, registers are often used incorrectly even though they have not been set.

[Problem that the invention seeks to solve]

Incorrect use of registers can corrupt memory contents in unexpected locations, causing the program to run out of control. However, since register usage errors do not result in assembling errors, it is extremely difficult to detect such errors.

The present invention aims to solve the above problems, and when executing instructions,
By providing means for detecting register usage errors, the purpose is to enable early detection of program errors and improve the reliability of software.

[Means for solving problems]

FIG. 1 is a block diagram of the principle of the present invention.

In FIG. 1, 10 is a computer that fetches and executes an instruction, 11 is an availability state change instruction that changes the availability state of a register, 12 is a register usage instruction such as a load instruction/store instruction, and 13 is an instruction decoded. 14 is a state change instruction execution circuit that executes the usability state change instruction 11; 15 is an invalid state storage circuit that records the usability state of each register; 16 is a general-purpose register used in the program; 17 represents an error detection circuit that detects an error in the use of the register 16.

In the case of the present invention, an invalid state storage circuit 15 is provided corresponding to each register 16 to indicate whether or not it can be used.

When the invalid state storage circuit 15 stores "0", the corresponding register 16 is enabled, and when it stores "1", it is disabled.

In order to set the state to the invalid state storage circuit 15,
A usability state change command 11 is newly established.

When this instruction is decoded by the instruction decoder 13, the status change instruction execution circuit 14 sets the usability status of the specified invalid status storage circuit 15.

When a register usage instruction 12 that uses registers such as load/store is issued, the instruction decoder 13
The register use signal is transmitted to error detection circuit 17. The error detection circuit 17 is.

Invalid state storage circuit 15 corresponding to the corresponding register
If the invalid state storage circuit 15 indicates that it cannot be used, an error interrupt signal is output.

[Effect]

The usability state of each register can be freely set in the invalid state storage circuit 15 by the usability state change instruction 11. Therefore.

In module interfaces, etc., the caller may use registers that should not be used.

Use of the device can be prohibited in advance using the usability status change command 11. If the called module mistakenly uses the prohibited register due to an interface error, the error detection circuit 17 outputs an error interrupt signal.

Since a program interrupt occurs, the error can be immediately found by examining the instruction that caused the interrupt, without causing the program to run out of control.

〔Example〕

FIG. 2 shows one embodiment of the present invention, FIG. 3 is an explanatory diagram of saving/restoring the usability state, and FIG. 4 shows another embodiment of the present invention.

In FIG. 2, 20 is the calling module, 21
represents a called module, and AND represents an AND circuit.

S I issued in module (A) 20
The R (Set Invalid Register) command is a usability state change command that turns on the invalid display of the invalid state storage circuit 15. That is.

By issuing the command of rsIR2J, the invalid display of the invalid state storage circuit 15 for the register R2 becomes O.
Become N. Thereafter, register R2 is prohibited from use.

Parameters are set in register R1 by the load command of module (A>20 is rL 1.PARM).
Next rL15. Module (ABC) 21 by XJ
Set the start address of rBALR in register R15,
14, 15J branch instruction, module (ABC)
Calling 21.

Here, the module (ABC) 21 mistakes the register R1 and the register R2, as shown in FIG.
rsT 2. Assume that a store instruction for XXXJ is issued.

In this case, invalid state storage circuit 1 of register R2
5 is "1", and upon comparison with the register R2 use signal output from the instruction decoder 13, an error interrupt signal is output. Therefore, register usage errors can be detected immediately.

When the module (ABC) 21 wants to use the disabled register R2 for a purpose unrelated to the interface to the module (A) 20, as shown in FIG. 2(b).

Before using the register, set S V R (Set V
(alid Register) instruction. This r
By issuing the SVR2J command, the invalid display in the invalid state storage circuit 15 is turned off.

Register R2 becomes available. Module (AB
Since C) 21 issues the SVR command with the register in mind, there is no need to worry about errors in the use of this register.

In the example shown in FIG. 2, the invalid indication is turned ON10FF for only one register, but it is of course possible to turn the invalid indication of a plurality of registers ON10FF with one instruction. In this case, for example, multiple registers may be specified by a bit pattern corresponding to the register number, or an RR format instruction may be used to specify a continuous register group from the first operand register to the second operand register. , it is also possible to set the invalid display to 0N10FF.

For example, if an interrupt such as an input/output interrupt occurs,
Control is transferred to the operating system's interrupt handler, and execution of the previously executing program is interrupted. In such cases.

It is considered that it becomes necessary to save/restore the invalid state stored in the invalid state storage circuit 15.

This can be countered by newly providing a usability status save command 32 and a usability status restore command 34, for example, as shown in FIG. As shown in FIG. 3(a), it is assumed that two interrupts occur while task 30 is running. As a result, control is transferred to the interrupt handler 31 registered in advance. Interrupt handler 31
Well then.

After saving the general-purpose registers in a predetermined area, a usability state save instruction 32 is issued to save the contents of the invalid state storage circuit 15.

After that, when the 9 interrupt processing etc. are completed and the dispatcher 33 returns execution control to the original task 30, the saved registers are restored and the contents of the invalid state storage circuit 15 are restored by the usability state restore instruction 34. Restore and pass control to the 9 interrupt point.

FIG. 4 shows invalid state management according to another embodiment of the present invention.

In the example shown in FIG. 4, an invalid state display register 4 corresponds to the invalid state storage circuit 15.
0 is set. Invalid status display register 4
Starting from the first bit of 0, each bit is displayed as invalid corresponding to each register in turn. Then, as a special write command to this register 40, WRI
A TE invalid status instruction 41 is provided, and a READ invalid status instruction 42 is provided as a read instruction from this register 40.

By WtTE invalid state instruction 41.

It is possible to set/reset and restore the invalid indication corresponding to each register, and it is possible to save the invalid indication by the READ in-state command 42. Note that an execution circuit for one or more instructions need not be described in detail, and can be configured in the same manner as a conventional execution circuit for load/store instructions.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to prevent interface errors due to incorrect use of registers in module interfaces, subroutine calls, etc., and it is possible to improve the reliability of software. In addition, it is now possible to reduce/expand the range of registers that can be used.1 For example, by allowing a higher-level module to specify the registers that can be used by a lower-level module, general register saving/restoring can be done in part. Registers can be made optional.

[Brief explanation of drawings]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is an embodiment of the invention, Fig. 3 is an explanatory diagram of saving/restoring the usability state, and Fig. 4 is another embodiment of the invention. . In the figure, 10 is a computer, 11 is a usability state change command, 1
Reference numeral 2 represents a register use instruction, 13 an instruction decoder, 14 a state change instruction execution circuit, 15 an invalid state recording circuit, 16 a register, and 17 an error detection circuit.

Claims (1)

[Scope of Claims] A register misuse prevention control method in a computer equipped with a plurality of registers that load/store data according to instructions, comprising an invalid state storage circuit that stores the usability status of each register. (15), a state change instruction execution circuit (14) that updates the memory contents of the invalid state storage circuit (15) and changes the usability state; ), and an error detection circuit (17) that checks the usability status of the register stored in the register and determines an instruction error when the register is unusable.