JPS62278643A - Retrial control system - Google Patents

Abstract

PURPOSE:To improve the retrial success factor when intermittent errors occur by setting the retrial start waiting time suited to the system environment. CONSTITUTION:The retrial start waiting time can be optionally set to a retrial start waiting time memory means 9 in a system rise mode. Then a retrial propriety display means 8 displays whether the retrial is possible or not when error detecting means 1 and 2 detect errors within the system. In the retrial is possible, a retrial executing means carries out the retrial after waiting a time designated by the means 9. In such a way, the retrial success factor is improved when intermittent errors occur.

Description

[Detailed Description of the Invention] 3. Detailed Description of the Invention (Field of Industrial Application) The present invention relates to a retry control method in an information processing device [Prior Art] Conventionally, this type of retry control method has been A detection means for detecting an error occurring in the system, a retryability determination bit indicating whether or not a retry can be performed depending on the state of the system at the time of error detection, and a means for executing a retry. When an error occurs in the system, the content of the above-mentioned retry permission determination bit is determined, and if a retry is possible, the retry is immediately performed.

[Problem that the invention seeks to solve]

By the way, errors that occur within the system, especially intermittent errors, can be caused by various things such as static electricity mischief, wave noise, and poor contact at the cable connector.
The time during which these causes act usually varies depending on the environment of the system. Therefore, in the conventional retry control method described above, which performs a retry immediately without waiting time after determining the contents of the retry permission determination bit, depending on the system environment, the retry may be attempted before the cause of the intermittent error is removed. It had the disadvantage of doing the following.

The present invention solves these conventional drawbacks, and its purpose is to provide a retry control method that can improve the retry success rate when intermittent errors occur.

[Means for solving problems]

In order to achieve the above object, the present invention includes: a retry activation waiting time storage means that can set a retry activation waiting time at the time of system startup; an error detection means that detects an error occurring in the system; and an error detection means. a retry possibility display means for displaying whether a retry is possible in response to error detection by the means; and when the retry possibility display means indicates that a retry is possible, the retry is performed before executing the retry; and retry execution means for executing a retry after waiting for a time specified by the activation waiting time storage means.

[Effect]

The retry startup waiting time storage means can arbitrarily set a retry startup waiting time at the time of system startup, and when an error in the system is detected by the error detection means,
Whether retry is possible or not is displayed by the retry possibility display means, and if retry is possible, the retry execution means executes the retry after waiting for the time specified by the retry start waiting time storage means. do.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, which includes a plurality of error detection circuits (hereinafter referred to as CHK) 1゜2 for detecting errors in each hardware (not shown), and this CHKl.
, a plurality of error indicators (hereinafter referred to as ETFs) for storing that there is an error in accordance with the error detection of 2.
3.4, an OR circuit 5 that takes the logical sum of the output signals of ErF3 and ErF4, and the output of this OR circuit 5 and CHKI, CHK2.
A NOR circuit 6 that takes a NOR condition with the output of , an AND circuit 7 that takes a logical product of the program visible register write request and the output of the above-mentioned NOR circuit 6 when a program visible register write request occurs, and an execution start signal of each instruction. and a retry permission display circuit (hereinafter referred to as RTB) 8 which is reset by the output of the AND circuit 7, that is, a register write signal for actually writing to the program visible register, and an arbitrary retry display circuit (hereinafter referred to as RTB) at the time of system startup. A retry activation waiting time memory circuit (for example, made of non-volatile memory, hereinafter referred to as DLY) 9 that can set a activation waiting time, and a counter to which the output of DLY9 is set before retry activation. (hereinafter referred to as CNTR) 10 and C for each countdown request.
a subtracter 12 that counts down the value of NTRl0;
Manually combine the output of NTRl0 and the value rOJ CNTRl0
Comparison circuit 11 for detecting whether the value of becomes 0 or not
, the output of the OR circuit 5, the output of the RTB 8, the comparison circuit 11
The outputs of C and NT are respectively input, and the contents of DLY9 are C and NT.
It is comprised of a failure handling mechanism 13 that performs failure handling, which will be described later, by controlling cents to Rl0, sending a countdown request to the subtracter 12, determining the output of the operation 2 comparator 11, etc.

FIG. 2 is a flowchart of a processing example of the failure handling mechanism 13, and the operation of this embodiment will be explained below with reference to each figure.

When a certain hardware error is detected in CHKI, CHK2, the corresponding ErF3. The content of ErF4 becomes "1", the output of the OR circuit 5 becomes "1", and the fault handling mechanism 13 is activated.

When the failure processing mechanism 13 is activated, it stops the clock and temporarily logs out to a working storage section (not shown) in order to retrieve the internal state of the hardware to an external storage device (not shown) (process 100).

Next, the failure handling mechanism 13 resets the hardware to an error prior to retry activation (process 101).

As a result, the stopped clock is restarted, and initial settings are made except for program-visible information, system control information, and the like.

Next, the failure processing mechanism 13 determines the contents of the RTB 8 (
Process 102), the RTB 8 receives the execution start signal of each instruction.
1”, CHKI, CHK2゜ErF3.E
None of rF3 is "1" and is reset to "0" when the contents of the program module visible register are updated. Therefore, when RTB 8-“0”, that is, retry is not possible, failure handling when retry is not possible, for example, in a multiprocessor configuration, processing such as disconnecting the affected processor, aborting the job, and continuing processing is performed. Perform (Process 1
03).

On the other hand, when RTB8-“l”, retry is possible, and a retry activation waiting process is performed, that is, a process 104) is performed to transfer the contents of DLY9 to CNTRIG, for example, a countdown request is sent to the subtractor 12 every 1 microsecond. The value of CNTRl0 is subtracted by issuing 105), CN
Process 106) to determine whether the value of TR,10 has become O or not based on the output of the comparison circuit 11. If the value is 0, it is assumed that a predetermined retry activation waiting time has elapsed and a retry is activated. process 107), and if the value is still not O, the waiting is continued.

Next, it is determined whether the result of the retry is successful or not, and if it is successful, the process is continued (process 110), and if it is unsuccessful, failure processing is performed in case of failure, for example, if the configuration is a multiprocessor, the affected processor Processing is performed such as disconnecting the processor and retrying on the normal processor (processing 109).

In addition, in FIG. 1, EIF3. A program visible register write request is gated in an AND circuit 7 by the output of an OR circuit 5 which ORs the output of EIF4, and the output of a NOR circuit 6 which takes a NOR condition signal from each output of CHK1 and CHK2. This is a consideration to improve the retry rate.

〔Effect of the invention〕

As explained above, the present invention provides a retry startup waiting time storage means that can set a retry startup waiting time at the time of system startup, an error detection means for detecting an error occurring in the system, and the error detection means. a retry possibility display means for displaying whether or not a retry is possible according to error detection by the retry operation; Since we have provided a retry execution means that executes a retry after waiting for the time specified by the waiting time storage means, it is possible to set a retry start waiting time that is suitable for the system environment. This has the effect of improving the retry success rate when errors occur.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a flowchart of an example of processing by the fault handling mechanism 13. In the figure, 1.2...Error detection circuit (CHK), 3
．． 4...Error indicator (EIF), 5...
OR circuit, 6...NOR circuit, 7...AND circuit, 8
... Retry possibility display circuit (RTB), 9... Retry start waiting time memory circuit (DLY), 10... Counter, 11... Comparison circuit, 12... Subtractor, 13.
...Fault handling mechanism. Patent originator NEC Corporation

Claims (1)

[Scope of Claims] Retry startup waiting time storage means capable of setting a retry startup waiting time at system startup, error detection means for detecting errors occurring in the system, and error detection by the error detection means. a retry activation display means for displaying whether retry is possible or not according to the retry possibility display means; and when the retry possibility display means indicates that retry is possible, the retry start waiting time storage means 1. A retry control method comprising: retry execution means for executing a retry after waiting for a time specified by .