JP3320570B2 - How to recover from a system error - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a recovery method for recovering from an abnormal state when an abnormality occurs in a system such as a control device.

[0002]

2. Description of the Related Art When an abnormality occurs in a system such as a control device, the abnormality is detected and a system reset is performed to recover the system from an abnormal state. . And
In this configuration, a method of clearing the watchdog circuit within a predetermined period in a main loop is used. That is, when an abnormality occurs in the system, the watch loop is not cleared within a predetermined period because the main loop is not normally executed. Therefore, when the watchdog circuit is not cleared within a predetermined period, it is determined that an abnormality has occurred, and the system is reset from the abnormality by generating a system reset (referred to as Conventional Technique 1). As another conventional technique for recovering from a system abnormality, a system in which a control device and a peripheral device are connected to each other via a bus defined as an IDE bus sends a predetermined control signal to the peripheral device. Then, if a response signal is not transmitted from the peripheral device within a certain period, it is determined that the peripheral device is abnormal, and a method of resetting the peripheral device has been proposed (referred to as Conventional Technique 2).

[0003]

However, when the related art 1 is applied to a control device that performs a predetermined operation in a main loop and generates a timer interrupt at a constant time interval, the following problem occurs. That is, when disturbance such as external noise occurs, the setting of the timer becomes abnormal due to the disturbance, and the timer interrupt may not occur. However, even if the timer interrupt does not occur,
The watchdog circuit is cleared within a predetermined period in the main loop. For this reason, the watchdog circuit
This cannot be detected even though the timer interrupt has stopped. Therefore, the control device could not recover from the abnormal state. Prior art 2
In the case where is used, the following problems have occurred. That is, when a disturbance such as an external noise affects both the control device and the peripheral device, not only an abnormality occurs in the peripheral device, but also the control device is provided to perform an interface with the peripheral device. The setting of the interface IC may also be abnormal. Thus, Interface I
When the setting of C becomes abnormal, even if the peripheral device is reset to recover the abnormal state, the setting of the interface IC in the control device remains in the abnormal state. An error that occurred in communication with the device could not be recovered.

[0004] The present invention was been made to solve the above problems, an object of the invention of claim 1 wherein the peripheral
When an abnormal response of the device is detected, reset the peripheral device.
System reset and system reset
It is an object of the present invention to provide a method of recovering from a system abnormality that can recover from an abnormality in the system with a high probability.

[0005]

Means for Solving the Problems The method of restoration from an abnormal system according to the invention of claim 1, wherein for solving the above problems, Li when not cleared within a preset period
By sending the reset level to the set signal line
Watchdog circuit for system reset
Clear and reset the watchdog circuit
Has a control register to instruct level transmission
And a peripheral circuit, through the peripheral circuit and peripheral devices for performing a reset operation when said via a reset signal line reset level is applied with when the predetermined control signal is supplied and sends a predetermined response signal In a control device connected to a CPU, the control register
Whether the data read from is the same as the data at the time of setting
The read data differs from the data at the time of setting.
Resets the watchdog circuit if
Performing a system reset by instructing the transmission of a level, when transmitting the predetermined control signal to the peripheral device, when the peripheral device did not transmit the predetermined response signal within a preset period, A method of transmitting the reset level to the peripheral device via a reset signal line and performing a system reset to initialize the peripheral circuit.

[0006]

[0007]

[0008]

The operation of the first aspect of the invention will be described below. If a predetermined response signal is not transmitted from a peripheral device within a preset period after a predetermined control signal is transmitted to the peripheral device, an abnormality of the peripheral device or an abnormality of a peripheral circuit in the system has occurred. become. Therefore, when a predetermined response signal is not transmitted from a peripheral device within a preset period, a reset level is transmitted to the peripheral device via a reset signal line and a system reset is performed, thereby initializing the peripheral device. And initialization of the system. In addition, the data read from the control register
Even if the data differs from the data at the time of setting,
Peripheral circuit settings change depending on the
Operation is determined to have failed, and peripheral devices are initialized and system
System initialization.

[0009]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 5 shows the electrical configuration of an apparatus to which an embodiment of the method for recovering from a system abnormality according to the present invention is applied, and this apparatus is specifically a facsimile apparatus. This device can be roughly classified into a control device 1
And a FAX unit 1 which is a peripheral device connected to the control device 1
0, the control device 1 and the facsimile unit 1
0 is provided in the same frame.

The control device 1 is a block for controlling the operation as a facsimile device.
U3, ROM4, RAM5, watchdog circuit 6, and peripheral circuit 7 are provided. And each of these blocks 2
7 are connected to each other via a bus 9. Further, the bus 9 includes a reset signal line, and the reset signal line is also led to the FAX unit 10 via the peripheral circuit 7. The facsimile unit 10 is a block to which a telephone line 11 is connected, and executes various operations as a facsimile device under the control of the control device 1. When a predetermined control signal is transmitted from the control device 1, a predetermined response signal is transmitted to the control device 1 within a predetermined period. When a reset level is sent to the reset signal line, internal initialization is performed. Therefore, when the control device 1 performs a system reset, the FAX unit 10 is simultaneously reset.

The timer 2 is a programmable timer / counter circuit, and is a block for activating a timer interrupt at fixed time intervals. That is, at a time interval set by the CPU 3, an interrupt signal is transmitted to the interrupt terminal of the CPU 3. The CPU 3 temporarily stores data in the RAM 5 as necessary,
4 is a block for controlling the operation as a facsimile machine by executing the program stored in
FIG. 3 is a block for executing a method for recovering from a system abnormality according to the present invention. FIG.

The watchdog circuit 6 is a block for performing a system reset by sending a reset level to a reset signal line of the bus 9 when the watchdog circuit 6 is not cleared within a preset period. The peripheral circuit 7
A signal line that can be set as an input or an output is an input signal line or an output signal line corresponding to the setting of the control register 8 provided therein. Is set to
Two of the plurality of signal lines set as output signal lines are sent to the watchdog circuit 6. One of the two signal lines sent to the watchdog circuit 6 clears the watchdog circuit 6. The other signal line causes the watchdog circuit 6 to send a reset level.

[0013] Figures 1 and 2 is a flow chart illustrating one embodiment of a method of returning from the system abnormality.

When the initial setting after the power is turned on or after the system reset is completed and the main loop is operated,
The CPU 3 clears the watchdog circuit 6 (step S1). Next, the CPU 3 reads the data of the control register 8 provided in the peripheral circuit 7, and determines whether the read data is the same as the data at the time of setting (step S2). When the read data is different from the data at the time of setting, the setting of the peripheral circuit 7 is changed due to electric disturbance or the like, and it is determined that an abnormality has occurred in the operation of the system. The CP that has determined that an abnormality has occurred
U3 causes the watchdog circuit 6 to send out a reset level. That is, the watchdog circuit 6 is connected to the bus 9
The system is reset by sending a reset level to the reset signal line (step S6).

On the other hand, if it is determined in step S2 that the read data is the same as the data at the time of setting, it is determined that the operation of the system is normal, and the CPU 3
The count value of the time measurement counter set in the predetermined area of AM5 is updated (step S3). When the updating of the value of the time measurement counter is completed, the CPU 3 determines whether or not the count result of the updated time measurement counter is within a predetermined range (step S4). When the count result is within the predetermined range, it is determined that the timer interrupt is operating normally, and the operation as the facsimile machine is controlled (step S5). When the count result is out of the predetermined range, it is determined that an abnormality has occurred in the timer interrupt operation, the reset level is sent from the watchdog circuit 6, and the system is reset (step S
6).

When an interrupt signal is sent from the timer 2 during execution of the main loop, the CPU 3
An interrupt control process, such as sensing of various signals output from the AX unit 10, is set as an interrupt operation (step S7). Then, when the interrupt control processing is completed, the value of the time measurement counter set in the RAM 5 is set to an initial value.

That is, when the control device 1 is operating normally as a system, a timer interrupt is started at fixed time intervals. Therefore, the time measurement counter is set to an initial value by a timer interrupt before the count result after updating the value becomes a value outside the predetermined range. The watchdog circuit 6 is cleared before the set period elapses. For this reason, in the main loop, the loop operation of steps S1 to S5 is executed. In addition, a timer interrupt started at a fixed time interval causes step S7,
The operation of S8 is performed.

In this operating state, if an abnormality occurs in the setting of the timer 2 due to an electric disturbance or the like, an interrupt signal is generated.
It is no longer sent to PU3. Therefore, every time the operation in step S3 is performed, the value of the time measurement counter is continuously updated, and the count result eventually becomes a value outside the predetermined range. As a result, in the determination in step S4, the count result of the time measurement counter is out of the predetermined range. For this reason, the system reset of step S6 is executed, and the system is returned from the abnormal state. In addition, CP
When U3 goes out of control and the main loop of steps S1 to S5 is not executed normally, the watchdog circuit 6 is not cleared. For this reason, the watchdog circuit 6 performs a system reset to return the system from the abnormal state.

FIG. 3 shows another method of recovering from a system error .
Is a flowchart illustrating an embodiment.

In this embodiment, it is not determined in the main program whether the system is abnormal. The time interval of the timer interrupt is set shorter than the period until the cleared watchdog circuit 6 performs a system reset. Then, in the timer interrupt activated during the execution of the main program, the operations of steps S9 to S12 are executed.

That is, when a timer interrupt occurs, the CP
U3 performs a predetermined interrupt control process (step S9).
In addition, the watch dog circuit 6 is cleared (step S
10). Next, the data of the control register 8 provided in the peripheral circuit 7 is read, and it is determined whether the read data is the same as the data at the time of setting (step S1).
1). When the read data is different from the data at the time of setting, the setting of the peripheral circuit 7 is changed due to an electric disturbance or the like, and it is determined that an abnormality has occurred in the operation of the system.
For this reason, the reset level is sent from the watchdog circuit 6, and the system is reset (step S12).
On the other hand, if it is determined in step S11 that the read data is the same as the data at the time of setting, it is determined that the operation of the system is normal, and the operation as the timer interrupt is terminated.

During the continuation of the above operation, the setting of the timer 2 changes due to an electric disturbance or the like, or C
Since PU3 is prohibited from accepting the interrupt, when the timer interrupt is not activated, the watchdog circuit 6 is not cleared within a predetermined period. As a result, the watchdog circuit 6 sends a reset level to the reset signal line of the bus 9 to perform a system reset.

FIG. 4 shows the recovery from the system abnormality of the present invention.
5 is a flowchart illustrating an embodiment of a method .

In step S13, the CPU 3 reads data from the control register 8 provided in the peripheral circuit 7, and determines whether the read data is the same as the data at the time of setting. If the read data is different from the data at the time of setting, the setting of the peripheral circuit 7 is changed due to an electric disturbance or the like, and it is determined that an abnormality has occurred in the operation of the system. CPU3 that has determined that an abnormality has occurred
Causes the watchdog circuit 6 to send out a reset level to perform a system reset (step S19).

On the other hand, if it is determined in step S13 that the read data is the same as the data at the time of setting, it is determined that the operation of the system is normal. Next, a predetermined control signal is transmitted to the FAX unit 10 via the peripheral circuit 7 (step S14). Thereafter, the CPU 3 performs an initial setting for time measurement (step S15). By repeating the operations of steps S16 and S17, F
It is determined whether a predetermined response signal is transmitted from AX section 10 within a preset period. When a predetermined response signal is transmitted from the FAX unit 10 within the set time, it is determined that the system and the FAX unit 10 are operating normally.
The CPU 3 controls an operation determined as a facsimile machine (step S18). However, if the response signal is not sent from the FAX unit 10 within the set time, the CP
U3 determines that an abnormality has occurred in the peripheral circuit 7, the FAX unit 10, or the like, causes the watchdog circuit 6 to send a reset level, and performs a system reset (step S3).
19).

The present invention is not limited to the above embodiment, and the applicable device is a facsimile unit 10 which is a peripheral device.
Although the description has been made of the case where the control device 1 is connected to the control device 1, other devices such as a host computer to which a peripheral device such as a CD-ROM device is connected can be similarly applied.

[0027]

[0028]

[0029]

According to the method for recovering from a system abnormality according to the present invention, a predetermined response from a peripheral device within a preset period is provided.
If no signal is sent out,
Sends a reset level to peripheral devices and resets the system.
Initialization of peripheral devices and system
And read from the control register
If the data set differs from the data set,
Peripheral circuit settings change due to disturbance, etc.
Judge that an abnormality has occurred in the operation of the
Since it is configured to perform the initialization of the system, it is possible to return from abnormalities in the system with a high probability. "

[Brief description of the drawings]

1 is a flow chart illustrating one embodiment of a method of returning from the system abnormality.

2 is a flow chart illustrating one embodiment of a method of returning from the system abnormality.

3 is a flowchart showing another embodiment of a method of returning from the system abnormality.

FIG. 4 is a flowchart illustrating an embodiment of a method for recovering from a system abnormality according to the present invention.

FIG. 5 is a block diagram showing an electrical configuration of an apparatus to which an embodiment of a method for recovering from a system abnormality according to the present invention is applied;

[Explanation of symbols]

 Reference Signs List 1 control device 2 timer 6 watchdog circuit 7 peripheral circuit 8 control register 9 bus including reset signal line 10 peripheral device 11 telephone line

──────────────────────────────────────────────────続 き Continuing on the front page Judge Morizou Iseki, Chief Judge Judge Kazuyoshi Hotta Judge, Takashi Nagashima (56) References JP-A-2-36448 (JP, A) JP-A-6-175992 (JP, A) JP-A-5-151027 (JP, A) JP-A-58-197556 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 11/30

Claims (1)

(57) [Claims] 1. It is not cleared within a preset period
Sometimes a reset level is sent to the reset signal line.
Watchdog circuit that resets the system by
And clearing this watchdog circuit
Control register to instruct reset level transmission
The reset operation is performed when the reset level given through said Lise <br/> Tsu preparative signal line sends out a predetermined response signal when a peripheral circuit including a capacitor, a predetermined control signal is applied the control device connected to the CPU via peripherals said peripheral circuit, data read from the control register set
Makes a determination of whether the same as the time of the data, in the case where the read data is different from the set at the time of data before
Send the reset level to the watchdog circuit.
When the system control is instructed and the predetermined control signal is transmitted to the peripheral device, and when the peripheral device does not transmit the predetermined response signal within a preset period, the reset signal line is connected. Transmitting the reset level to the peripheral device via the peripheral device and performing a system reset to initialize the peripheral circuit.