JPH05282167A - Method for processing fault - Google Patents

Abstract

PURPOSE:To execute fault analyzing and fault recovering processing without stopping a system in a compact information processing system including an I/O control device in a processor. CONSTITUTION:The operating status of an I/O control device(IOC) 3 is monitored from a service processor(SVP) 2 through an IOC/SVP interface bus 200, an interruption is generated from an SVP interface control/interruption generating circuit 3a at the time of recognizing the disableness of the IOC 3, or detecting a fault by a fault detecting register 3f in the IOC 3, and in the case of reporting the fault to the SVP 2, a RAM 3b in the IOC 3 is read out from the SVP 2 to execute fault analysis. Then the IOC 3 is initialized and an IOC microprogram is loaded down through the bus 200 when necessary to restart the operation of the IOC 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a failure processing method for an information processing system, and more particularly to a failure processing method for an input / output control device via a service processor.

[0002]

2. Description of the Related Art Generally, an input / output control device controls input / output under the instruction from a processing device. On the other hand, also in failure processing related to input / output control, failure information and maintenance information are transmitted from the input / output control device to the processing device, and failure analysis is performed by the processing device and the program. In these failure processes, the system is stopped and failure analysis is performed. To avoid this system outage, for example,
The method described in JP-A-56-71149 is known. In this method, a maintenance command is issued from the processor to distinguish the maintenance mode from the normal mode, and maintenance and operation are performed without stopping the system.
No consideration is given to the disaster recovery process. Here, when considering failure recovery processing, it is common to attempt failure recovery by resetting the input / output system from the processing device or by programmatic reset from the processing device. In the former case, the system will be in a stopped state,
IMPL (Initial Micro Program Load) of the input / output controller or processor is required. Further, in the latter case, the program table of the input / output control device is reset because it is a programmatic reset, but hardware cannot be reset in many cases, and failure recovery may not always be achieved.

[0003]

In the above-mentioned prior art, the failure processing for the input / output control device is performed from the processing device, and therefore the failure analysis is performed with the system stopped. On the other hand, when the processing device is caused to perform the failure processing without stopping the system, it is necessary to operate the maintenance program on the processing device, and the failure analysis program is also required. In addition, a high load is applied to the processing device, and the performance of other input / output control devices is degraded. further,
When the input / output system is reset from the processing device as the failure recovery process, it is necessary to restart the system, which causes a problem that the system stop time becomes long. An object of the present invention is to provide a failure processing method that can improve such problems and can recover from a failure without stopping the system.

[0004]

In order to achieve the above object, a failure processing method according to the present invention is directed to a storage device, a processing device, an input / output control device for executing input / output in accordance with instructions from the storage device, system maintenance and In an information processing device including a service processor that controls monitoring, the input / output control device has means for interfacing with the service processor (IOC / SVP interface bus, SVP interface control circuit) and an interface register (fault detection register). And means for generating an interrupt to the service processor (interrupt generating circuit), and means for storing IOC / SVP interface information including an IOC microprogram stored flag, storage failure information, etc. (RAM)
And the service processor is provided with means (IOC / SVP interface bus, IOC interface control circuit) for interfacing with the input / output control device, and the input / output control device sets a processing request in the interface register. Then, the service processor generates an interrupt, and when the service processor detects the processing request, the service processor reads and analyzes the failure information accumulated in the input / output control device, and the analysis result shows that It is characterized in that only the input / output control device is set to the initial state and downloaded according to the storage state of the input / output control program.

[0005]

In the present invention, the service processor performs maintenance operations such as failure processing for the input / output control device,
Since the stored failure information stored in the input / output control device is analyzed, the maintenance program on the processing device is unnecessary. On the other hand, the input / output control unit holds the accumulated fault information and also has a fault detection register. By setting these, an interrupt to the service processor is generated, and the I / O control unit from the service processor. The stored failure information in is read out and analyzed. Also,
Upon analysis of the accumulated fault information, a reset signal is generated from the service processor as necessary, and the input / output control device is initialized. In this case, the I / O controller in the initial state is the IO in the IOC / SVP interface information.
The stored state of the input / output control program of its own can be known from the C microprogram stored flag, and the input / output control is restarted by downloading from the service processor as necessary. As a result, it is possible to perform failure recovery without stopping the system.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a configuration diagram of a failure processing system according to an embodiment of the present invention. In FIG. 1, 1 is a processing device, 2 is a service processor (SVP) that performs maintenance and monitoring of the entire system, and 3 is an input / output command from the IP 1b.
An input / output control device (IO that controls the input / output devices 4 and 5)
C), 4 is an output device (VDT), 5 is an input device (K
B) and 200 are IOC / SVP interface buses. The processing device 1 includes an IP (instruction processor) unit 1b that executes instructions and an input / output control device (I
IOP (input / output processor) section 1c for controlling OC) 3
And a main memory (MS) 1a. Also, SV
P2 is connected to the system bus 100, and IOC3 is
It is connected to the input / output devices 4 and 5. In addition, these are IO
It is connected by the C / SVP interface bus 200. As a result, accumulated failure information collected by IOC3,
Real-time fault information is transferred to the SVP2 via the IOC / SVP interface bus 200.

Next, the configuration and operation of the interface between the IOC 3 and the SVP 2 will be described in detail. Figure 2
FIG. 3 is a configuration diagram of an input / output control device and a service processor in one embodiment of the present invention, and FIG. 3 is a configuration diagram of a RAM in the input / output control device in one embodiment of the present invention. First, I
The configuration of OC3 will be described. In FIG. 2, 3a is
Circuit for controlling SVP interface, and SVP2
Is an SVP interface control / interrupt generation circuit composed of an interrupt generation circuit for making a processing request to the.
Further, 3d is an input / output interface control circuit for controlling the input / output devices 4 and 5, and 3e is an IOP interface control circuit for controlling the interface of the IOP 3. Further, the RAM 3b stores a microprogram of the IOC 3 and accumulated failure information. Besides this, RAM3
At the specific address of b, as shown in FIG. 3, the IOC microprogram storage flag 10 and the IOC / SVP interface information 20 (accumulation failure information storage start address 20
a, processing request 20b for SVP2, interrupt factor 20
c, fault content 20d) are stored. Also, ROM3
An initial hardware diagnostic program is stored in c, and the initial hardware diagnostic is executed immediately after the power is turned on. It also has a failure processing routine, and when a failure is detected by the failure detection register 3f during normal operation, it transfers control to the ROM 3c and executes failure processing. Further, it also controls to store the IOC microprogram in the RAM 3b.

Next, the operation will be described. In this embodiment, when the power of the system is turned on, the IOC microprogram is controlled by the IOP 1c under the control of the ROM 3c.
It is stored in the RAM 3b via the IOP interface control circuit 3e and the IOC memory bus 3h. When the storage is completed, the ROM 3c turns on the stored flag 10 at the specific address of the RAM 3b, transfers the control to the IOC microprogram, and starts the operation. When the operation is started in this way, the IOC 3 causes an interrupt to the SVP 2 via the IOC / SVP interface bus 200 at predetermined time intervals, and the SVP 2 monitors the inoperable state of the IOC 3. After that, when the IOC3 falls into an inoperable state during normal operation, the SVP3 recognizes this and without stopping the system, the IOC / SVP interface bus 200
A reset is issued via to initialize all the hardware registers of the IOC3 to the initial state. In this way, in the IOC3 in the initial state, the ROM 3c starts to operate and the SV
P3 continues to load IOC microprogram into RAM3
Download to b and perform failure recovery. The IOP interface control circuit 3e reports the busy state to the normal input / output instruction from the IOP 1c in the initial state and during downloading. Further, the download of the IOC microprogram from the SVP3 does not necessarily have to be unique and may be sufficiently recovered in the initial state of the hardware in the reset operation. The control as to whether or not the download is necessary can be performed by the ROM 3c. For example, after the initial state, the hardware is initially diagnosed and recognized as normal.
If the IOC microprogram stored flag 10 written in the specific address is ON, it is not necessary to download. By identifying the failure content in this way, the SV
The processing load in the P2 failure recovery processing can be reduced. The failure recovery process in the inoperable state has been described above.

Next, the recovery process for the intermittent failure will be described. The IOC 3 of the present embodiment stores an event related to the status information of the input / output control device in the RAM 3b as accumulated failure information. When a failure occurs, the failure detection register 3f is set, and the SVP interface / interrupt generation circuit 3a operates according to the contents of the failure detection register 3f. That is, a processing request is issued to the SVP2 depending on the content of the failure. Thus, when the interrupt generation circuit operates, an interrupt is generated to the processor 2c of the SVP2 via the IOC / SVP interface bus 200. As a result, the SVP2 causes the RAM3 in the IOC3 to pass through the IOC interface control circuit 2a.
Read the specific address of b. Furthermore, the obtained IOC / S
Based on the VP interface information 20, the stored fault information is read out and an analysis process is performed. Further, the processing request 20b of the IOC / SVP interface information 20 is set with a failure notification requesting reset, a failure notification not requesting reset, and the like, and the processing request 20b and the interrupt factor 2 are set.
0c determines the operation of SVP2. For example, in the case of a failure notification requesting a reset, the SVP 2 proceeds to the reset operation of the IOC 3 after acquiring the accumulated failure information. The reset IOC3 sets all the hardware registers of the IOC3 to the initial state and performs the same operation as the failure recovery process in the inoperable state described above.

[0010]

According to the present invention, the failure recovery process can be performed by surely initializing the input / output control device from the service processor without stopping the information processing system.

[0011]

[Brief description of drawings]

FIG. 1 is a configuration diagram of a failure processing system according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of an input / output control device and a service processor according to an embodiment of the present invention.

FIG. 3 is a configuration diagram of a RAM in the input / output control device according to the embodiment of the present invention.

[Explanation of symbols]

 1 Processor 1a Main Memory 1b Instruction Processor 1c Input / Output Processor 2 Service Processor 2a IOC Interface Control Circuit 2b RAM 2c Processor 2d System Bus Control Circuit 2e SVP Memory Bus 3 Input / Output Controller 3a SVP Interface Control / Interrupt Generation Circuit 3b RAM 3c ROM 3d I / O interface control circuit 3e IOP interface control circuit 3f Fault detection register 3g Processor 3h IOC memory bus 4 output device 5 input device 100 system bus 200 IOC / SVT interface bus

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Rikio Kuribayashi 1 Horiyamashita, Hadano City, Kanagawa Pref., Kanagawa Plant, Hitate Manufacturing Co., Ltd. (72) Terubun Danue 1 Horiyamashita, Hadano, Kanagawa Prefecture In Tate Computer Electronics (72) Inventor Tsutomu Yamazaki 1 Horiyamashita, Hadano City, Kanagawa Prefecture

Claims (1)

[Claims] 1. A failure processing method for an information processing apparatus comprising a processing device, a storage device, an input / output control device for executing input / output according to an instruction of the processing device, and a service processor for maintaining and monitoring the system. In the above, in the input / output control device, means for interfacing with the service processor, interface register, means for generating an interrupt to the service processor, interface information including storage state information of its own input / output control program and storage. And a means for interfacing with the input / output control device, the input / output control device sets a processing request in the interface register, and interrupts the service processor. And the service processor detects the processing request, A failure processing method characterized in that failure information accumulated in the input / output control device is read and analyzed, the input / output control device is initialized according to the analysis result, and downloaded according to the storage status of the input / output control program.