JPH0773076A - Trace information collection system - Google Patents

Abstract

PURPOSE:To selectively monitor an instruction which CPU executes, an address and a data content at the time of memory access, accumulating the selected address and data in a dedicated memory and to facilitate analysis at the time of a fault. CONSTITUTION:A CPU execution trace controller 4 is connected to a bus connecting CPU, a memory and an I/O device. The CPU execution trace controller 4 is provided with an instruction detection part 41, a memory access detection part 42, an I/O detection part 43, an interruption detection part 44, a trace collection part 45 and a control part 46 connected to the bus controlling the parts. The detection part designated by the control part 46 extracts the address and data from above the bus and accumulates them in the dedicated memory which is backed up by a battery through the trace collection part 45.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a trace information collecting method,
In particular, the present invention relates to a trace information collection method for tracing the execution contents of a CPU when an information processing device in which a CPU, a memory, and an I / O device are connected to a common bus fails.

[0002]

2. Description of the Related Art Conventionally, in this type of trace information collecting method, the OS of the CPU is provided with a function of collecting CPU execution contents and the information is stored in a memory, or a processing information collecting function is provided in each module of an application program. The information is stored and stored in a memory so that the information can be analyzed when a failure occurs.

[0003]

In the above-mentioned conventional trace information collecting method, since the information of the execution contents is collected and accumulated by the processing execution device itself, in the case of abnormal stop of the CPU, memory destruction, etc. It has a problem that it takes a lot of time to identify the cause of the failure.

[0004]

The trace information collecting method of the present invention collects data on a common bus connecting a CPU, a memory, and an I / O device, and performs trace information when a failure occurs. In the sampling method, an instruction detection signal connected to the bus for detecting an instruction fetch signal when the CPU fetches an instruction during execution of the instruction and extracting the address and contents at that time, and an instruction for the CPU to access the memory When the memory read / write is performed, the read / write signal is detected, and the memory access detection means connected to the bus for extracting the address and contents at that time and the I / O signal when the CPU performs the I / O I / O detection means connected to the bus for detecting and extracting the I / O address and contents at that time, and an interrupt when an interrupt occurs Interrupt detecting means connected to the bus for detecting the signal and extracting the content thereof, and trace information collecting means for writing the content extracted by each detecting means in a dedicated memory driven by an uninterruptible power supply. , A control means connected to the bus for receiving the control signal from the bus to activate / inactivate each of the detection units and to specify the extracted data length from the memory access detection means. It

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention.
In the embodiment shown in FIG. 1, a CPU execution trace controller 4 is connected to a common bus 1 for connecting a CPU 2, a memory 3 and an I / O device (not shown), and a dedicated memory 5 for tracing is provided in the CPU execution trace controller 4. Connected and configured.

FIG. 2 shows a CPU execution trace controller 4
In the configuration diagram of FIG. 3, an instruction detection unit 41, a memory access detection unit 42, an I / O detection unit 43, an interrupt detection unit 44 connected to the bus 1, and a trace connected to these detection units and the dedicated memory 5. The sampling unit 45, the bus 1, the four detection units 41 to 44, and the control unit 46 connected to the trace sampling unit 45 are included.

In the above configuration, the CPU execution trace controller 4 detects a signal on the bus 1 and stores related data in the dedicated memory 5. That is, the instruction detection unit 4
Reference numeral 1 detects a signal such as an instruction fetch or a memory fetch sent by the CPU 2 onto the bus 1 for executing an instruction. The instruction detection unit 41 passes the instruction fetch address and the fetched content from the detected signal to the trace collection unit 45.
The trace collection unit 45 first writes an ID indicating instruction execution into the dedicated memory 5, and then passes the passed data to the dedicated memory 5
Continue to write.

A memory access detection unit 42 detects a memory fetch signal sent on the bus 1 for the CPU 2 to access the memory. The memory access detection unit 42 passes the detected memory address and the fetched content to the trace collection unit 45. The trace collection unit 45 first writes an ID indicating a memory access to the dedicated memory 5, and subsequently writes the passed data to the dedicated memory 5. The amount of data to be written is, for example, 16 bytes or 256 bytes, and a predetermined fixed amount of data is written to the dedicated memory 5. If the amount of data to be collected is less than a certain amount, NUL data is written to a certain amount, and subsequently the actual data amount value is written to the dedicated memory 5. If the amount of data to be collected is just a certain amount or more, a certain amount is written in the dedicated memory 5 and the collected data amount value is written in the dedicated memory 5.

The I / O detection section 43 detects an I / O signal sent to the bus 1 by the CPU 2 to execute an I / O transfer. The I / O detection unit 43 passes the detected I / O address and contents to the trace collection unit 45. Trace collection unit 4
The dedicated memory 5 stores an ID indicating an I / O instruction.
Then, the ID indicating the IN / OUT of the I / O and the I / O data are continuously written into the dedicated memory 5.

The interrupt detector 44 detects an interrupt signal on the bus. The interrupt detection unit 44 passes the detected interrupt level to the trace collection unit 45. The trace collection unit 45
An ID indicating an interrupt is written in the dedicated memory 5, and then the interrupt level is written in the dedicated memory 5.

The trace collection unit 45 writes information in the dedicated memory 5, and the dedicated memory 5 is used cyclically. Therefore, after writing the information, the last address value at which the trace provided at the head of the dedicated memory 5 is written is updated. Furthermore, the trace collection unit 45 reads the dedicated memory 5 when dumping the dedicated memory 5.

The control unit 46 also controls the instruction detection unit 41, the memory access detection unit 42, the I / O detection unit 43, the interrupt detection unit 44, and the trace collection unit 45.

The control unit 46 controls activation / deactivation of the functions of the detection units 41 to 44, confirmation of detection in each detection unit, and activation / deactivation of information collection for the trace collection unit 45. , Has a function of initializing the information collection position, instructing reading from the dedicated memory 5 when the dedicated memory 5 is dumped, and receiving data from the trace collecting unit 45. Also CP
The control from the outside of the U execution trace controller 4 is performed by the I / O control command prepared by the control unit 46 in the I / O transfer.
Control by executing by instruction. For example,
When only the data of the memory access of the CPU 2 is to be traced, the instruction detecting unit 41, I / O
By issuing a deactivation instruction to the detection unit 43 and the interrupt detection unit 44 and an activation instruction to the memory access detection unit 42, C
Trace data can be collected only when PU2 makes a memory access. If all trace data is desired to be collected, all trace data can be collected by instructing activation of all detection units. Further, when it is desired to start trace collection at a specific time, the trace collection unit 45 is first instructed to deactivate the trace collection unit 45, and when the specific time comes, the control unit 46 causes the trace collection unit 45 to deactivate. The activation of the trace collection unit 45 may be instructed.

The dedicated memory 5 is backed up by a battery so that the trace data can be saved even in the case of a power failure.

[0016]

As described above, according to the present invention, the details of execution at the time of computer failure can be grasped, and by saving the trace memory, the analysis can be performed even after the failure occurs. In addition, by externally controlling the control unit, when a certain address is fetched, an interrupt is generated in the CPU, the contents of instruction execution at the time of memory destruction can be read, and the cause can be specified.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is a configuration diagram of a CPU execution trace controller of the embodiment of FIG.

[Explanation of symbols]

 1 bus 2 CPU 3 memory 4 CPU execution trace controller 5 dedicated memory 41 instruction detection unit 42 memory access detection unit 43 I / O detection unit 44 interrupt detection unit 45 trace collection unit 46 control unit

Claims (1)

[Claims] 1. A trace information collecting method for collecting data on a common bus connecting a CPU, a memory, and an I / O device and performing a trace at the time of a failure, in a CP
When U fetches an instruction during execution of the instruction, an instruction fetch signal is detected, and an instruction detection means connected to the bus for extracting the address and contents at that time and a memory read / write instruction by the CPU And a memory access detection means connected to the bus for detecting the read / write signal and extracting the address and contents at that time, and I / O when the CPU performs I / O.
I / O detection means connected to the bus for detecting the O signal and extracting the I / O address and contents at that time, and I / O detection means connected to the bus for detecting the interrupt signal and extracting the contents when an interrupt occurs. Interrupt detecting means, trace information collecting means for writing the contents extracted by each detecting means to a dedicated memory driven by an uninterruptible power supply, and a control signal from the bus A trace information collecting method, comprising: a control unit which is activated / inactivated and which is connected to a bus for designating an extracted data length from the memory access detection unit.