JPS5941210B2 - How to handle power failure - Google Patents
How to handle power failureInfo
- Publication number
- JPS5941210B2 JPS5941210B2 JP53117266A JP11726678A JPS5941210B2 JP S5941210 B2 JPS5941210 B2 JP S5941210B2 JP 53117266 A JP53117266 A JP 53117266A JP 11726678 A JP11726678 A JP 11726678A JP S5941210 B2 JPS5941210 B2 JP S5941210B2
- Authority
- JP
- Japan
- Prior art keywords
- control device
- power
- processing unit
- central processing
- message
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Power Sources (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
Description
【発明の詳細な説明】
本発明はコンピュータ、端末制御装置および端末装置か
らなるシステムにおける端末制御装置電源障害時の処理
方式に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a processing method when a power failure occurs in a terminal control device in a system including a computer, a terminal control device, and a terminal device.
コンピュータ(中央処理装置)、端末制御装置および端
末装置から構成される。It consists of a computer (central processing unit), a terminal control device, and a terminal device.
例えば投票券の発売、集計を行なうトータリゼータシス
テムにおいて、何らかの原因で前記端末制御装置が電源
断した場合に、この電源断をコンピュータにて認識でき
るけれども、復電したことの認識を人手を介さないで自
動的に行なうことは出来なかつた。従来、何らかの障害
で一亘電源断した制御装置は自動的に復旧を試みること
はせずに、一旦システムから切離してフオールバツクモ
ードで運用させている。しかしながらこのフオールバツ
クモードではシステムが二重障害を起した場合とか、引
き続いて障害が発生した場合には、正常に全システムが
稼動している場合に比べて極端に信頼度および稼動率が
低下し、システムの運用上致命的になる可能性もある。
本発明の目的は上記問題点を解決するもので、障害が発
生した制御装置は復電を通知し、自動的に復旧処理を試
みシステムに再組み込みを行なうことにより、自動的に
リカバリ処理を行ない平均復旧時間(MeanTlme
ToRepalr)MTTRの短縮化にともなうシステ
ムの信頼度および稼動率を向上するものである。For example, in a totalizer system that sells and tallies voting tickets, if the power to the terminal control device is cut off for some reason, this power cut can be recognized by a computer, but it is not possible to recognize that the power has been restored without human intervention. It couldn't be done automatically. Conventionally, a control device whose power has been temporarily cut off due to some kind of failure does not automatically attempt recovery, but is temporarily disconnected from the system and operated in fallback mode. However, in this fallback mode, if the system suffers a double failure or a series of failures occurs, the reliability and availability will drop significantly compared to when all systems are operating normally. However, it may be fatal to the operation of the system.
The purpose of the present invention is to solve the above-mentioned problems, and the control device in which a failure has occurred notifies power restoration, automatically attempts recovery processing, and reincorporates into the system, thereby automatically performing recovery processing. Mean recovery time
ToRepalr) This improves system reliability and operation rate as MTTR is shortened.
上記本発明の目的は多数の端末と、この端末を制御する
端末制御装置と、中央処理装置からなる情報処理システ
ムにおいて、前記制御装置が停電して、次に復電した時
に、制御装置から中央処理装置に対し復電メッセージを
送出し、中央処理装置は受信した復電メッセージにより
前記制御装置のリカバリ処理を自動的に行なうことによ
り達成される。The object of the present invention is to provide an information processing system consisting of a large number of terminals, a terminal control device that controls the terminals, and a central processing unit. This is achieved by sending a power restoration message to the processing device, and the central processing device automatically performing recovery processing for the control device based on the received power restoration message.
次に図面により本発明の詳細を説明する。Next, details of the present invention will be explained with reference to the drawings.
第1図は本発明の実施例による端末制御装置のブロック
図、第2図は本発明の実施例による制御装置とコンピュ
ータ間の処理シーケンスを示すタイムチャート、第3図
は処理フローチャートを示す。FIG. 1 is a block diagram of a terminal control device according to an embodiment of the present invention, FIG. 2 is a time chart showing a processing sequence between the control device and a computer according to an embodiment of the present invention, and FIG. 3 is a processing flowchart.
図において1はコンピータ、2は制御装置、3は端末装
置、4は伝送線、5は制御装置内CPU、6は停電検出
回路、7は復電検出回路、8はROM、9はレジスタ、
10はメツセージ送出制御回路を示す。In the figure, 1 is a computer, 2 is a control device, 3 is a terminal device, 4 is a transmission line, 5 is a CPU in the control device, 6 is a power failure detection circuit, 7 is a power recovery detection circuit, 8 is a ROM, 9 is a register,
10 indicates a message sending control circuit.
制御装置2が何らかの障害により電源断すると制御装置
2の停電検出回路6が動作して障害原因および停電のス
テータスをレジスタ類9(不揮発性)に記憶する。When the control device 2 is powered off due to some kind of failure, the power failure detection circuit 6 of the control device 2 operates and stores the cause of the failure and the status of the power failure in registers 9 (non-volatile).
その後制御装置が復電した場合には復電検出回路γが動
作してCPU5にレベル“O゛等高い優先順位の割込み
を行なう。After that, when the power is restored to the control device, the power restoration detection circuit γ operates to issue a high priority interrupt such as level "O" to the CPU 5.
CPU5はこの割込みを検出して、内蔵してあるROM
8のマイクロプログラムを起動する。制御装置2はRO
M8のマイクロプログラムが走ることにより、障害原因
のステータス、および復電した旨のメツセージをメツセ
ージ送出制御回路10を通してコンピユータ1に通知す
る。The CPU 5 detects this interrupt and writes it to the built-in ROM.
Start the microprogram No. 8. Control device 2 is RO
By running the microprogram of M8, the computer 1 is notified of the status of the cause of the failure and a message indicating that the power has been restored through the message sending control circuit 10.
コンピユータ1は制御装置2より障害原因のステータス
および復電した旨のメツセージを受け取ると、これを受
信した旨のメツセージを制御装置2に応答する。制御装
置2はコンピユータ1より、この受信した旨の応答が来
るまで、ある一定の周期で繰返し、障害原因のステータ
スおよび復電した旨のメツセージをコンピユータ1に送
り続ける。When the computer 1 receives the status of the cause of the failure and a message to the effect that the power has been restored from the control device 2, it responds to the control device 2 with a message to the effect that it has received this. The control device 2 continues to send the status of the cause of the failure and a message to the effect that the power has been restored to the computer 1 repeatedly at a certain period until a response is received from the computer 1 to the effect that the power has been restored.
コンピユータ1は制御装置2から受信した障害内容を解
析して、その内容に応じたプログラムを起動する。The computer 1 analyzes the details of the failure received from the control device 2 and starts a program according to the details.
コンピユータは障害の内容に応じて、制御装置2に対し
て復旧処理の指示を行なう。The computer instructs the control device 2 to perform recovery processing depending on the details of the failure.
この復旧処理の例として制御装置の障害内容(重要度)
に応じて1IPL(イニシヤル,プログラム,ロード)
を行ない全く最初の状態から開始する。As an example of this recovery process, the failure details (level of importance) of the control device
1 IPL (Initial, Program, Load) depending on
and start from the very beginning.
2障害の発生した部分を切離したフオールバツクモード
で再開する。2.Restart in fallback mode with the part where the failure occurred isolated.
3障害の発生した部分の診断をコンピユータ側から行な
う。3. Diagnose the part where the failure occurred from the computer side.
4電源断した直前の状態から再開する等の処理を行なう
。4 Performs processing such as restarting from the state immediately before the power was cut off.
以上の処理シーケンスおよび処理フローチヤートを第2
図および第3図に示す。The above processing sequence and processing flowchart are
As shown in FIG.
以上説明したように制御装置が何らかの障害により電源
断して、その後復電した場合コンピユータ側に対し、制
御装置より自動的に復電メツセージを通知して、コンピ
ユータに復電を認識させることを可能にしたものである
。As explained above, if the control device loses power due to some kind of failure and then returns, it is possible to automatically notify the computer side of a power recovery message from the control device, allowing the computer to recognize the power recovery. This is what I did.
これlこよつて制御装置からコンピユータへの復電通知
からコンピユータおよび制御装置のリカバリ処理までを
コンピユータと制御装置とがメツセージを交換すること
により自動的に行ないMTTRの短縮化がはかられ、シ
ステムとしての信頼件および稼動率が飛躍的に向上する
。As a result, the computer and control device automatically perform the process from power restoration notification to the computer to recovery processing of the computer and control device by exchanging messages, shortening the MTTR and improving the system. The reliability and operation rate of the system will be dramatically improved.
第1図は本発明の実施例による制御装置のプロツク図、
第2図は本発明の実施例による制御装置とコンピユータ
間の処理シーケンスを示すタイムチヤート、第3図は処
理フローチヤートを示す。FIG. 1 is a block diagram of a control device according to an embodiment of the present invention;
FIG. 2 is a time chart showing a processing sequence between a control device and a computer according to an embodiment of the present invention, and FIG. 3 is a processing flow chart.
Claims (1)
、中央処理装置からなる情報処理システムにおいて、前
記制御装置の停電時にそのステータスを不揮発性記憶手
段に記憶し、復電した時に、該制御装置から中央処理装
置に対し前記ステータスを含む復電メッセージを送出し
、中央処理装置は受信した復電メッセージを分析し、前
記制御装置のリカバリ処理を自動的に行なう事を特徴と
する電源障害時の処理方式。 2 制御装置に内蔵されているROMのマイクロプログ
ラムにより復電メッセージ送出の制御をする事を特徴と
する特許請求の範囲1項記載の電源障害時の処理方式。 3 中央処理装置で復電メッセージを受信した旨の応答
が制御装置へ送出されるまで所定のタイミングで繰返し
中央処理装置へ復電メッセージを送出することを特徴と
する特許請求の範囲1項または2項記載の電源障害時の
処理方式。[Scope of Claims] 1. In an information processing system consisting of a large number of terminals, a terminal control device that controls the terminals, and a central processing unit, when the control device has a power outage, its status is stored in a non-volatile storage means and the status is restored. When the power is restored, the control device sends a power recovery message including the status to the central processing unit, and the central processing unit analyzes the received power recovery message and automatically performs recovery processing for the control device. Features a processing method in the event of a power failure. 2. The processing method in the event of a power failure according to claim 1, characterized in that sending of a power recovery message is controlled by a microprogram in a ROM built into the control device. 3. Claim 1 or 2, characterized in that the power restoration message is repeatedly sent to the central processing unit at a predetermined timing until a response indicating that the power restoration message has been received by the central processing unit is sent to the control device. Processing method for power failure described in section.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP53117266A JPS5941210B2 (en) | 1978-09-22 | 1978-09-22 | How to handle power failure |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP53117266A JPS5941210B2 (en) | 1978-09-22 | 1978-09-22 | How to handle power failure |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5543687A JPS5543687A (en) | 1980-03-27 |
JPS5941210B2 true JPS5941210B2 (en) | 1984-10-05 |
Family
ID=14707495
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP53117266A Expired JPS5941210B2 (en) | 1978-09-22 | 1978-09-22 | How to handle power failure |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5941210B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6317962B2 (en) * | 1982-02-23 | 1988-04-15 | Sekisui Chemical Co Ltd |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62129636U (en) * | 1986-02-03 | 1987-08-17 | ||
JPH01133146A (en) * | 1987-11-19 | 1989-05-25 | Oki Electric Ind Co Ltd | Terminal equipment |
-
1978
- 1978-09-22 JP JP53117266A patent/JPS5941210B2/en not_active Expired
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6317962B2 (en) * | 1982-02-23 | 1988-04-15 | Sekisui Chemical Co Ltd |
Also Published As
Publication number | Publication date |
---|---|
JPS5543687A (en) | 1980-03-27 |
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