JP3042034B2 - Failure handling method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a failure processing system in a central processing system having a single structure such as an exchange. Generally, the system configuration is duplicated in a large-capacity exchange or the like, and if a failure occurs in the control system of the current exchange system, the system is immediately switched to a spare exchange system to prevent the system from going down. However, in a relatively small-capacity switchboard, for example, a PBX with about 50 to 200 lines, the central processing system is economically unitary, and in the event of a failure in the central processing system, the restart processing program is executed to operate the system. ing.

FIG. 4 shows a system configuration example of a central processing system such as a small-capacity exchange. In the figure, 31 is a central processing unit (CC), 32 is a main memory (MM), 33 is a communication channel control system (SP), 34 is an I / O control unit, 35 is a hard disk (HD), 36 is a maintenance console ( MC).

The central processing unit 31, the main memory 32, the communication path control system 33, and the I / O control unit 34 are connected by a system bus, and the operation program of a plurality of telephone lines connected to the communication path control system 33 Central control unit 31 and main memory 32
The I / O control unit 34 is connected to the maintenance console 36 and the hard disk 35, and controls the failure processing program and the operation program inserted as needed between the central processing unit 31 and the main memory 32. Running.

FIG. 5 shows a state transition diagram of the system operation of the central processing system such as the above exchange. Normally, if there is no abnormality such as a failure, program processing such as replacement operation is performed. If any failure occurs, the process proceeds to restart processing to collect failure information, and then emergency processing (redundancy) In the case of, perform system switchover and other hard disk H
D), and resume normal operation.

[0005]

2. Description of the Related Art FIG. 6 shows a block diagram of a conventional fault processing unit. In the figure, 21 is a voltage monitoring circuit, 22 is a restart control unit, 23 is a flip-flop, and 24 is an MPU. When the voltage drop becomes equal to or less than the reference value, the voltage monitoring circuit 21 sends out a power-on reset signal pulse to reset the power supply. The restart control unit 22 includes a timing circuit and an OR circuit. When a power-on reset signal and a memory error occurrence signal are input, the restart control unit 22 sends a reset signal to the MPU 24 at a certain timing. The flip-flop 23 is for displaying the power-on bit of the restart register, and sends a display signal to the MPU 24 via the data bus.

In the conventional method, a memory error occurrence signal is detected every time a memory error occurs, and a restart start is notified to the restart control unit 22. Restart control unit
22 is M after the timing when the memory error signal is received at P ₁
A reset signal is output to PU24. After the reset signal is turned off, the MPU 24 reads the restart register and executes the restart processing procedure.

FIG. 7 shows a flowchart of a conventional fault processing procedure. In the figure, (11) Power on the control system. (Pow-on) (12) IPL (loading of initial program) the operation program from the magnetic disk HD. (Execution of Pow-on IPL) (13) W. D. Reset T (watchdog timer for software runaway monitoring). (14) Execute exchange operation. (15) Check for failure. If there is no failure,
During this time, W. D. T. The replacement operation is performed while resetting at regular intervals. (16) If a failure occurs, D. Reset T. (17) Move to restart processing , analyze failure and collect failure information
I do. At this time, if a memory error (double-bit error, single-bit error) occurs fixedly in the area where the restart processing program is stored, (16)
A loop occurs on the route indicated by the dotted line between (17) and (17), and the system stops. (18) It is checked whether or not the restart processing has been completed, and if not completed, the procedure returns to (16), and W. D. T. Is repeated at a fixed cycle, and the restart processing is repeated. (19) When the restart processing is completed, hardware reset or reloading from the magnetic disk HD is performed.
Depending on the type of the fault, only the hardware of the central control unit CC is reset without changing the contents of the main memory MM. Alternatively, the program of the magnetic disk HD is reloaded into the main memory MM. Any one of the restart processes is performed, and the process returns to the exchange operation.

[0008]

In the case of a conventional system having a single configuration, when a memory error occurs during execution of the restart processing program, the above-mentioned flowcharts (16) and (1) are used.
As shown in 7), a loop is generated in a portion including the watchdog timer clear processing, and a problem such that the system is stopped occurs. In the case of a single system, it is impossible to transfer to another system by executing system switching, and the system may not be restored even by reloading from the magnetic disk HD.

SUMMARY OF THE INVENTION It is an object of the present invention to execute a restart procedure at the time of power-on when a failure occurs in a memory area, thereby executing a failure process for an exchange of a single system to prevent the system from being stopped.

[0010]

FIG. 1 is a block diagram showing the principle of a failure processing unit according to the present invention. In the figure, 1 is a voltage monitoring circuit that monitors a voltage drop and sends a power-on reset signal, 2 is a restart control unit that sends a reset signal to the MPU in response to a memory error occurrence signal and a power-on reset signal, Reference numeral 3 denotes a flip-flop for transmitting a power-on bit display signal of the restart register to the MPU via a data path. Reference numeral 4 denotes an MPU of a failure processing unit. A memory error measurement counter for transmitting a multi-memory error signal when the signal is turned on. Reference numerals 6 and 7 denote OR circuits for a power-on reset signal and a multi-memory error signal.

The circuit added to the conventional fault processing unit according to the present invention is a memory error measurement counter 5 indicated by a dotted line.
And an OR circuit 6 for inputting an OR output of the power-on reset signal and the multi-memory error signal to the flip-flop 3 and an OR circuit 7 for inputting to the restart control unit 2. The restart control unit 2 includes a timing circuit (long / short) and an OR circuit as in the conventional circuit.

[0012]

According to the present invention, a memory error measurement counter 5 is counted up by using a memory error occurrence signal detected every time a memory error occurs as a clock, and a multi-memory error signal output when a memory error occurs a predetermined number of times. In response to this, the restart control unit 2 receives the multi-memory error signal, outputs a reset signal to the MPU 4, and outputs a reset signal to the MPU 4 after the reset signal is turned off. Read the restart register and
Recognizing that the ON bit is ON, the procedure to be performed at power-on, that is, the operation program after memory clear,
Reload the operation data and execute the restart procedure .

As a result, a memory error is fixedly generated during the execution of the restart processing program, a loop is generated in a portion including the watchdog timer clear processing, and the system can be prevented from being stopped. Is restored (for example, a bit stack due to extraneous noise) other than the failure due to the breakage of.

[0014]

FIG. 2 shows a block diagram of an embodiment. In the figure, 11 is a voltage monitoring circuit, 12 is a restart control unit, 13
Flip-flop 14 MPU, 15 is a memory error measurement counter, 16, 17 OR circuit OR1, OR @ 2, 18, 19 is a timing circuit TM _0, TM _1, 20 denotes an OR circuit OR @ 3. 18,
Reference numerals 19 and 20 indicate the internal configuration of the restart control unit 12, the timing circuit 18 is a relatively long timer, and the timing circuit 19 is a relatively short timer.

In this embodiment, a memory error occurrence signal MER detected every time a memory error occurs is input to the CP terminal of the memory error measurement counter 15 as a clock, and Q ₀
To Q _X-1 and the multi-memory error signal MMER output when X occurrences occur with the OR circuit 16.
Input to one terminal of 17. On the other hand, the power-on reset signal P-on R from the voltage monitoring circuit 11 for monitoring the voltage drop
Is input to the other terminals of the OR circuits 16 and 17. Multi-memory error signal MMER and power-on reset signal P-
By the OR output of on R, the flip-flop 13 for turning on the restart register is operated, and the restart control unit 12 is notified of the start of the restart. The reset control unit 12 outputs a reset signal in response to the multi-memory error signal MMER,
Recognizes that the power-on bit P-on B is on, and performs a power-on restart procedure.

FIG. 3 shows a flowchart of the failure processing procedure of the embodiment. The figure illustrates the case where the setting of the memory error measurement counter 15 overflows n times. (1) Turn on the power to the control system. (Pow-on) (2) Initialize the operation program from the magnetic disk HD. (Pow-on IPL) (3) D. Reset T (watchdog timer for software runaway monitoring). (4) Execute the replacement operation. (5) Check for failure. If no failure occurs, W.D. D. T. The replacement operation is performed while resetting at regular intervals. (6) If a failure occurs, the memory error measurement counter is incremented, and the counter value n is checked. When the counter value reaches n, the process returns to the initial setting of the operation program again. (7) If the counter value does not reach n, W. D. T. (8) Move to the restart process, and perform failure analysis and failure information collection . (9) Determine whether or not the restart processing has ended, and
If not, return to (6). (10) When the restart processing is completed, hardware reset or reloading from the magnetic disk HD is performed.
Resume processing is performed in the same manner as in the conventional operation depending on the type of the failure, and the process returns to the execution of the exchange operation again.

The processing flow added in the present invention is a portion from (6) to (2) indicated by a bold line, and a conventional route from (6) to (8) indicated by a dotted line occurs due to the occurrence of a memory error. Also, the system can be prevented from being stopped by forcibly clearing the memory.

[0018]

According to the present invention, it is possible to prevent a fatal system stop due to a memory error occurring in a single system of a conventional exchange by forcibly executing a memory clear.

[Brief description of the drawings]

FIG. 1 is a diagram showing the principle configuration of the present invention.

FIG. 2 is a block diagram of an embodiment.

FIG. 3 is a processing flowchart of an embodiment.

FIG. 4 is a system configuration example of a central processing system.

FIG. 5 is a state transition diagram of the central processing system.

FIG. 6 is a block diagram of a conventional example.

FIG. 7 is a processing flowchart of a conventional example.

[Explanation of symbols]

 1, 11, 21 Voltage monitoring circuit 2, 12, 22 Restart control unit 3, 13, 23 Flip-flop 4, 14, 24 MPU 5, 15 Memory error measurement counter 6, 7, 16, 17, 20 OR circuit 18, 19 Timing circuit 31 Central processing unit 32 Main memory 33 Communication path control system 34 I / O control unit 35 Hard disk 36 Maintenance console

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-59-153249 (JP, A) JP-A-58-3493 (JP, A) JP-A-53-114326 (JP, A) JP-A 63-114 638 (JP, A) JP-A-1-181295 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04Q 3/545 G06F 11/14-11/14 310 H04M 3/22 H04Q 3/58 101-107

Claims (1)

(57) [Claims] A fault monitoring system for a centralized processing system having a single configuration such as an exchange, comprising: a voltage monitoring circuit for monitoring a voltage drop of the processing system and transmitting a power-on reset signal; a restart control part which, by on-reset signal to the MPU sends a reset signal, and the flip flop for delivering power-on-bit display signal of the restart <br/> register by the data bus to the MPU, the failure handling
A memory error occurrence signal is measured every time a memory error occurs,
And an OR circuit for inputting a memory error measuring counter for delivering a multi-memory error signals, the OR output of the power-on reset signal and the multi-memory error signal to flip <br/> flops upon reaching a certain number of times, Li Start control unit
An OR circuit is provided for inputting, and the memory error measurement counter is clocked by a memory error occurrence signal detected every time a memory error occurs.
The restart register is turned on and the start of the start to the restart control unit is notified by a multi-memory error signal output when a memory error has occurred a certain number of times. In response to this multi- memory error signal , a reset signal is output to the MPU. After the reset signal is turned off, the restart register is read by software to recognize that the power-on bit is on. From memory clear
A fault handling method characterized by executing a start procedure .