JPS6092178U - Test adjustment device - Google Patents
Test adjustment deviceInfo
- Publication number
- JPS6092178U JPS6092178U JP18471583U JP18471583U JPS6092178U JP S6092178 U JPS6092178 U JP S6092178U JP 18471583 U JP18471583 U JP 18471583U JP 18471583 U JP18471583 U JP 18471583U JP S6092178 U JPS6092178 U JP S6092178U
- Authority
- JP
- Japan
- Prior art keywords
- test
- board
- boards
- pin arrangement
- adjustment device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Tests Of Electronic Circuits (AREA)
- Measuring Leads Or Probes (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は従来から用いられている試験調整装置−の信号
の流れの一例を示すブロック図、第2図は実際にドータ
ボードをマザーボードに実装した状態を示した外観図、
第3図は従来の試験調整回路における信号処理回路のド
ータボードの内部構造の一例を示したブロック図、第4
図はこの考案における信号処理の流れの一実施例を示し
たブロック図、第5図はこの考案の特徴をなすコネクタ
のピン配列の一実施例を示す概念図、第6図は入力出力
ピンとをショートさせたドータボードの内部構造の一例
を示したブロック図であり、1はA/D変換回路、5は
D/A変換回路、2〜4は信号処理回路、7〜9はドー
タボード、11はマザーボード、12はコネクタである
。なお、図中同一あるいは相当部分には同一符号を付し
て示しである。Fig. 1 is a block diagram showing an example of the signal flow of a conventionally used test adjustment device; Fig. 2 is an external view showing the state in which the daughter board is actually mounted on the motherboard;
Figure 3 is a block diagram showing an example of the internal structure of the daughter board of the signal processing circuit in a conventional test adjustment circuit.
The figure is a block diagram showing one embodiment of the signal processing flow in this invention, FIG. It is a block diagram showing an example of the internal structure of a short-circuited daughter board, in which 1 is an A/D conversion circuit, 5 is a D/A conversion circuit, 2 to 4 are signal processing circuits, 7 to 9 are daughter boards, and 11 is a motherboard. , 12 are connectors. Note that the same or equivalent parts in the figures are indicated by the same reference numerals.
Claims (1)
タボードと、上記ドータボードと共通のピン配列を有し
、各々の入力端と出力端とを短絡した試験用ボードと、
同じく共通のピン配列を有し、入力信号を処理した上で
他の計測器、システム等に接続できるようにした試験用
ボードと、上記複数個のドータ、ボード及び試験用ボー
ドをコネクタを介して接続及び支持できるようにしたマ
ザーボードとからなる試験調整装置。a plurality of daughter boards having a common input/output pin arrangement of connectors; a test board having a common pin arrangement with the daughter board and having the input end and output end of each board short-circuited;
A test board that also has a common pin arrangement and can be connected to other measuring instruments, systems, etc. after processing the input signal, and the plurality of daughters, boards, and test boards mentioned above are connected via connectors. A test and conditioning device consisting of a motherboard capable of being connected and supported.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18471583U JPS6092178U (en) | 1983-11-30 | 1983-11-30 | Test adjustment device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18471583U JPS6092178U (en) | 1983-11-30 | 1983-11-30 | Test adjustment device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6092178U true JPS6092178U (en) | 1985-06-24 |
Family
ID=30399433
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP18471583U Pending JPS6092178U (en) | 1983-11-30 | 1983-11-30 | Test adjustment device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6092178U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS632686U (en) * | 1986-06-25 | 1988-01-09 |
-
1983
- 1983-11-30 JP JP18471583U patent/JPS6092178U/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS632686U (en) * | 1986-06-25 | 1988-01-09 |
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