JPS6289045U - - Google Patents
Info
- Publication number
- JPS6289045U JPS6289045U JP17833285U JP17833285U JPS6289045U JP S6289045 U JPS6289045 U JP S6289045U JP 17833285 U JP17833285 U JP 17833285U JP 17833285 U JP17833285 U JP 17833285U JP S6289045 U JPS6289045 U JP S6289045U
- Authority
- JP
- Japan
- Prior art keywords
- mode
- creating
- read
- memory
- address signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Calculators And Similar Devices (AREA)
Description
第１図は本考案の一実施例による要部回路図、
第２図はモード指定レジスタを示す図、第３図は
モード指定のフローチヤート、第４図はｎ進系統
によるモードのフローチヤート、第５図は従来例
を説明するフローチヤートである。
１……ＲＯＭ、２……ＲＡＭ、３―１〜３―４
……オアゲート、４……アドレスデコーダ、５―
１〜５―４……アンドゲート。
FIG. 1 is a circuit diagram of a main part according to an embodiment of the present invention,
FIG. 2 is a diagram showing a mode designation register, FIG. 3 is a flowchart of mode designation, FIG. 4 is a flowchart of modes based on the n-ary system, and FIG. 5 is a flowchart explaining a conventional example. 1...ROM, 2...RAM, 3-1 to 3-4
...Or gate, 4...Address decoder, 5-
1-5-4...and gate.
Claims (1)
から出力される次のアドレス信号に基づいて上記
リードオンリメモリのアドレスが指定され順次処
理を行うようにした小型電子式計算機において、
モードを指定する指定手段と、該モード指定手段
により指定されたモードに応じて二進数によるモ
ードデータを作成する作成手段と、該作成手段に
より作成されたモードデータを記憶する記憶手段
と、該記憶手段から出力されたモードデータと上
記リードオンリメモリから出力された次アドレス
信号とにより新たな次アドレス信号を作成する手
段とを具備したことを特徴とする小型電子式計算
機。 In a small electronic calculator, the address of the read-only memory is designated and sequential processing is performed based on the next address signal output from the read-only memory in which microinstructions are stored,
a specifying means for specifying a mode; a creating means for creating binary mode data according to the mode specified by the mode specifying means; a storage means for storing the mode data created by the creating means; A small electronic calculator characterized by comprising means for creating a new next address signal from the mode data outputted from the means and the next address signal outputted from the read-only memory.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17833285U JPS6289045U (en) | 1985-11-20 | 1985-11-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17833285U JPS6289045U (en) | 1985-11-20 | 1985-11-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6289045U true JPS6289045U (en) | 1987-06-06 |
Family
ID=31120362
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17833285U Pending JPS6289045U (en) | 1985-11-20 | 1985-11-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6289045U (en) |
-
1985
- 1985-11-20 JP JP17833285U patent/JPS6289045U/ja active Pending
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