JPS59104247U - Instruction code fetch circuit - Google Patents
Instruction code fetch circuitInfo
- Publication number
- JPS59104247U JPS59104247U JP19988382U JP19988382U JPS59104247U JP S59104247 U JPS59104247 U JP S59104247U JP 19988382 U JP19988382 U JP 19988382U JP 19988382 U JP19988382 U JP 19988382U JP S59104247 U JPS59104247 U JP S59104247U
- Authority
- JP
- Japan
- Prior art keywords
- instruction
- instruction code
- circuit
- code fetch
- fetch circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Detection And Correction Of Errors (AREA)
- Executing Machine-Instructions (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図はＣＰＵの基本動作を説明するためのタイミング
図、′第２図は本考案に係る命令コードフェッチ回路の
一実施例を示すブロック図、第３図は動作説明のための
タイミング図である。
１・・−ｃｐｕ、 ２・・・メモリ、３・・・パリティ
検定回路、４・・・命令変換回路（ＮＯＰ出力回路）。Figure 1 is a timing diagram for explaining the basic operation of the CPU, Figure 2 is a block diagram showing an embodiment of the instruction code fetch circuit according to the present invention, and Figure 3 is a timing diagram for explaining the operation. be. 1...-cpu, 2... memory, 3... parity verification circuit, 4... instruction conversion circuit (NOP output circuit).
Claims (1)
てＣＰＵに読込まれる命令コードのパリティ検定回路と
、このパリティ検定回路からパリティエラー検出出力を
受け、当該誤命令コードをＣＰＵにおいて誤命令をスキ
ップさせるＮＯＰ命令に強請的に変換する命令変換回路
とを備えてなる命令コードフェッチ回路。A parity verification circuit for instruction codes read into the CPU via the memory cara bus of a microcomputer system, and a parity error detection output from this parity verification circuit are received, and the erroneous instruction code is sent to the NOP instruction that skips the erroneous instruction in the CPU. An instruction code fetch circuit comprising: an instruction conversion circuit for converting instructions;
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19988382U JPS59104247U (en) | 1982-12-27 | 1982-12-27 | Instruction code fetch circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19988382U JPS59104247U (en) | 1982-12-27 | 1982-12-27 | Instruction code fetch circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59104247U true JPS59104247U (en) | 1984-07-13 |
Family
ID=30425408
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19988382U Pending JPS59104247U (en) | 1982-12-27 | 1982-12-27 | Instruction code fetch circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59104247U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6335136U (en) * | 1986-08-22 | 1988-03-07 |
-
1982
- 1982-12-27 JP JP19988382U patent/JPS59104247U/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6335136U (en) * | 1986-08-22 | 1988-03-07 |
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