JPS60174957U - Memory device function confirmation circuit - Google Patents
Memory device function confirmation circuitInfo
- Publication number
- JPS60174957U JPS60174957U JP6182584U JP6182584U JPS60174957U JP S60174957 U JPS60174957 U JP S60174957U JP 6182584 U JP6182584 U JP 6182584U JP 6182584 U JP6182584 U JP 6182584U JP S60174957 U JPS60174957 U JP S60174957U
- Authority
- JP
- Japan
- Prior art keywords
- data
- memory device
- read
- storage means
- code
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Detection And Correction Of Errors (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案の実施例の構成例を示すブロック図であ
る。
１・・・・・・双方向バッファ、２・・・・・・単方向
バッファ、３・・・・・・コントロール回路、４・・・
・・・エラー検 “出・訂正回路、５・・・・・
・メモリチップ、６・・・・・・出力 ′バッファ。
−FIG. 1 is a block diagram showing a configuration example of an embodiment of the present invention. 1... Bidirectional buffer, 2... Unidirectional buffer, 3... Control circuit, 4...
...Error detection "detection/correction circuit, 5..."
・Memory chip, 6...Output 'buffer. −
Claims (1)
を検出して訂正するための符号を付加して前記記憶手段
に書込み用のデータとして与え、前記記憶手段から読み
出されたデータから、前記の符号に基づいて、そのデー
タの誤りを判別、訂正し、正しい原データを抽出して出
力するエラー検出・訂正手段とを備え、該エラー検出・
訂正子゛段を介して前記記憶手段へのデータの書込み、
および読出しを行うようにしたメモリ装置において、試
験時に、前記記憶手段へのデータの書込み及び読出しを
、前記エラー検出・訂正手段を介して行うか否かを切換
える切換手段と、該切換手段によって切換えて書込みお
よび読出しを行づたデータに基づいて前記メモリ装置が
正常か否かを判定する判定手段とを備えることを特徴と
するメモリ装 置の機能確認回路。A readable/writable storage means, a code for detecting and correcting data errors is added to the original data, and the code is provided to the storage means as write data, and the data read from the storage means is read from the data read from the storage means. an error detection/correction means for determining and correcting errors in the data based on the code of the data, and extracting and outputting correct original data;
writing data to said storage means via a corrector stage;
and a memory device configured to read data, a switching means for switching whether or not data is written to and read from the storage means via the error detection/correction means during a test; 1. A function checking circuit for a memory device, comprising determining means for determining whether or not the memory device is normal based on data written and read by the memory device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6182584U JPS60174957U (en) | 1984-04-26 | 1984-04-26 | Memory device function confirmation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6182584U JPS60174957U (en) | 1984-04-26 | 1984-04-26 | Memory device function confirmation circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60174957U true JPS60174957U (en) | 1985-11-20 |
Family
ID=30590459
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6182584U Pending JPS60174957U (en) | 1984-04-26 | 1984-04-26 | Memory device function confirmation circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60174957U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05189998A (en) * | 1992-01-14 | 1993-07-30 | Victor Co Of Japan Ltd | Inspecting method for random access memory |
-
1984
- 1984-04-26 JP JP6182584U patent/JPS60174957U/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05189998A (en) * | 1992-01-14 | 1993-07-30 | Victor Co Of Japan Ltd | Inspecting method for random access memory |
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