JPS59147232U - Transfer data error detection circuit - Google Patents
Transfer data error detection circuitInfo
- Publication number
- JPS59147232U JPS59147232U JP4092383U JP4092383U JPS59147232U JP S59147232 U JPS59147232 U JP S59147232U JP 4092383 U JP4092383 U JP 4092383U JP 4092383 U JP4092383 U JP 4092383U JP S59147232 U JPS59147232 U JP S59147232U
- Authority
- JP
- Japan
- Prior art keywords
- data
- detection circuit
- guarantee period
- circuit
- transfer data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案−実施例の構成図、また第２図は同実施
例における信号タイムチャートを示し、第１図において
、３は保持回路、５１は排他的ＯＲ回路、５２はＡＮＤ
回路である。FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a signal time chart in the same embodiment. In FIG. 1, 3 is a holding circuit, 51 is an exclusive OR circuit, and 52 is an AND circuit.
It is a circuit.
Claims (2)
された複数ビットのデータを並列に転送するデータ転送
回路において、前記データ保証期間の始めに読取って得
られたデータを一時記憶する保持回路と、前記保持回路
が読取り対象としたデータを前記データ保証期間の終り
に読取って得られたデータと前記保持回路に記憶するデ
ータとの不一致を検出する検出回路とを備えることを特
徴とする転送データ誤り検出回路。(1) In a data transfer circuit that transfers multiple bits of data guaranteed by a tag signal that identifies a data guarantee period in parallel, a holding circuit that temporarily stores data read at the beginning of the data guarantee period; A transfer data error characterized by comprising: a detection circuit that detects a mismatch between the data obtained by reading the data targeted for reading by the holding circuit at the end of the data guarantee period and the data stored in the holding circuit. detection circuit.
一時記憶するデータは前記転送するデータの中のパリテ
ィピットであることを特徴とする実用新案登録請求の範
囲第１項記載の転送データ誤り検出回路。(2) A transfer data error according to claim 1 of the utility model registration claim, characterized in that the data read at the beginning of the data guarantee period and temporarily stored in the holding circuit is a parity pit in the data to be transferred. detection circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4092383U JPS59147232U (en) | 1983-03-22 | 1983-03-22 | Transfer data error detection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4092383U JPS59147232U (en) | 1983-03-22 | 1983-03-22 | Transfer data error detection circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59147232U true JPS59147232U (en) | 1984-10-02 |
Family
ID=30171525
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4092383U Pending JPS59147232U (en) | 1983-03-22 | 1983-03-22 | Transfer data error detection circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59147232U (en) |
-
1983
- 1983-03-22 JP JP4092383U patent/JPS59147232U/en active Pending
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