JPS638804A - Programmable controller - Google Patents

Abstract

PURPOSE:To shorten the scan time by providing two status memories, which can be accessed with the same address, and a means which controls read/write permission and inhibition of both status memories independently of each other. CONSTITUTION:In the normal state, the same contents are written in both status memories 41 and 42 because gates G2 and G4 are opened, but contents of a first status memory 41 are read out because a gate G1 is opened and a gate G3 is closed. At the time of latching, a signal D is set to '0' to close the gate G4, and therefore, the status at this time is fixed in a second status memory 42. At the time of monitor, a signal C is set to '1' and the other signals are set to '0' to read and display fixed contents of the second status memory 42. Data is latched or read out by only gate control, and the control is efficiently performed without extending the scan time.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an improvement of a programmable controller.
More specifically, the present invention proposes a programmable controller that can efficiently monitor the contents of a status memory.

[Prior art]

The programmable controller is equipped with a RAM (random read/write memory) for storing the status of components with specific functions, such as the status of inputs, outputs, or the on/off status of internal relays. It is called. Generally, this status memory allocates one bit to one component.

[Problem that the invention seeks to solve]

This status memory is stored at a certain moment while operating the programmable controller when performing Km adjustment of a system configured using a programmable controller, such as when a launch command is executed or when a latch command is received from a peripheral device. It is sometimes used to monitor the contents of α and investigate the cause of malfunctions. One possible way to achieve this is to transfer the status memory all at once to another memory at the moment the status memory is about to be launched. becomes significantly longer. This also applies to the case where the contents of the status memory at a certain moment are to be linked and transferred to another CPU.

The present invention has been made to solve these problems, and an object of the present invention is to provide a programmable controller that can launch the state to be stored in the status memory without increasing the scan time.

[Means for solving problems]

A programmable controller according to the present invention is a programmable controller equipped with a status memory that stores the state of a component related to a specific function, and has two status memories that can be accessed at the same address, and a programmable controller that has two status memories that can be accessed at the same address, and that both status memories can be accessed one after another. , and means for independently controlling permission/denial of writing.

[Effect]

With the above configuration, the first status memory controls writing and reading so as to store each state, and the second status memory is written in the same way as the first status memory during normal instruction execution, but when latched For example, writing and reading are controlled to prohibit writing when a launch command is executed or when a latch command is received from a peripheral device. This causes the contents of the second status memory to be fixed if latching is required.

〔Example〕

Hereinafter, the present invention will be explained in detail based on drawings showing embodiments thereof.

The drawing is a block diagram showing the main parts of the programmable controller of the present invention, and 1 is a CPU (central processing unit);
2 stores the system program that controls the basic control of this programmable controller.
3 is a RAM that stores a sequence program set by the user. This programmable controller is the first. It is equipped with a second status memory 4142 and also performs input/output of signals with the outside.
10 (input/output) ports 5, which are connected by an address bus 6 and a data bus 7 in a so-called common hash system.
and read permission signal RE are sent to the ROM 2. Provided to IIAM31 status memory 41,42 and I10 port 5.

The read permission signal RE is sent to the first status memory 41 via the gate G1 and the write permission signal WR is sent to the gate G2, and the read permission signal RE is sent to the second status memory 42 via the gate G2.
The write permission signal WR is applied through the gate) G3 and the write permission signal WR is supplied through the gate) G4. These gates Gl to G4 are CPt
11 provides signal A through I10 port 5.

Opening/closing is controlled by signals B, C, and D, and when these signals are 1, the gate is opened, and when these signals are 0, the gate is closed.

Next, the first aspect of the programmable controller of the present invention. The writing and successive output control of the second status memory 41 and 42 will be explained.

The table below shows the contents of the control signals A, B, C, and D that the I10 port 5 gives to the game consoles Gl-64, respectively.

In the normal state when the command is executed, G2. Since gate G4 is open, the same content is written to both status memories 41 and 42, but since gate Gl is open and gate G3 is closed, the same content is written to the first status memory 41 and 42.
The contents of are read out. That is, the first status memory 41 performs the same function as a conventional status memory.

Next, when latching, it changes to D@O and closes gate G4. As a result, the current state is fixed in the second status memory 42. Other writing and reading are done in Game 1-G2. This is carried out to the first status memory 41 via Gl without any hindrance.

Next, when monitoring the status using the programmable controller itself (done during the scan time), C=1 and otherwise set to 0. As a result, the fixed contents of the second status memory 42 are read out and displayed.

〔effect〕

In the case of the present invention as described above, data can be latched or read only by gate control, which is efficient without extending the scan time, and which does not interfere with control by the programmable controller.

Note that if a gate is provided in the part of the second status memory 42 connected to the address bus and the data bus so that the second status memory can be accessed from other CPt1, link transfer and instruction execution can be performed simultaneously. The present invention has excellent effects such as:

[Brief explanation of drawings]

The drawing is a block diagram of main parts of a programmable controller according to the present invention. 1...CPIJ 2...120M 3...
・RAM 41.42...Status memory 5・
...I10 boat Gl, G2. G3. G4...Gate patent Applicant Koyo Electronics Co., Ltd. Agent Patent attorney Noboru Kono), I)

Claims (1)

[Claims] 1. In a programmable controller equipped with a status memory that stores the status of components related to a specific function, there are two status memories that can be accessed at the same address, and read and write permissions for both status memories can be independently determined. A programmable controller characterized by comprising: means for controlling.