JPS602697B2 - Information processing system switching method - Google Patents

Information processing system switching method

Info

Publication number
JPS602697B2
JPS602697B2 JP55088681A JP8868180A JPS602697B2 JP S602697 B2 JPS602697 B2 JP S602697B2 JP 55088681 A JP55088681 A JP 55088681A JP 8868180 A JP8868180 A JP 8868180A JP S602697 B2 JPS602697 B2 JP S602697B2
Authority
JP
Japan
Prior art keywords
switching
systems
circuit
information processing
control circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55088681A
Other languages
Japanese (ja)
Other versions
JPS5714951A (en
Inventor
等 鈴木
清文 林
毅 上原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Dai Ichi Communications Software Ltd
Fujitsu Ltd
Original Assignee
Fujitsu Dai Ichi Communications Software Ltd
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Dai Ichi Communications Software Ltd, Fujitsu Ltd filed Critical Fujitsu Dai Ichi Communications Software Ltd
Priority to JP55088681A priority Critical patent/JPS602697B2/en
Publication of JPS5714951A publication Critical patent/JPS5714951A/en
Publication of JPS602697B2 publication Critical patent/JPS602697B2/en
Expired legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16Error detection or correction of the data by redundancy in hardware
    • G06F11/20Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Hardware Redundancy (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Description

【発明の詳細な説明】 本発明は現用系に障害が発生したとき或いは検査のため
同期運転回路を使用することなく予備系に短時間で切替
えることのできる情報処理システムの切替方式に関する
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a switching method for an information processing system that can switch to a standby system in a short time when a failure occurs in the active system or for inspection without using a synchronous operation circuit.

電子交換機等のオンライン・リアルタイム・システムに
おいては高い信頼性が要求されるため、同一システムを
2合同期して運転させていた。
Because online real-time systems such as electronic exchanges require high reliability, two identical systems were operated synchronously.

これはシステムのハードウェアに十分な信頼性がなかっ
たためで、一方のシステムの中央処理装置内に設けた照
合回路により、他方のシステムの動作と常に照合をとり
ながらの運転であるから早期障害検出は可能であるが、
高速処理は困難であった。最近になってハードウェアに
ついての信頼性が向上したため、前述のような照合回路
を持たずに、待機予備方式を採用している。これはシス
テムの一方を現用、他方を待機状態としておき、現用系
に障害が発生したとき、待機状態にある系に切替えるこ
とである。第1図はこの方式の説明図であって、システ
ム#0は中央処理装置CCOと主記憶菱贋MMOを有し
、システム#1はCCIとMMIを有し、それらの間に
同期運転回路SYCと緊急制御回路EMCとを設けてい
る。同期運転回路SYCは両系への同一クロツクの分配
、両系の動作の照合・割込の同期などを行なうように機
成されている。現用系に障害が発生したとき、或いは予
備系についての潜在的な障害を発見するためにシステム
切替を行なう場合には前述の同期運転回路SYCを使用
し両系の動作が一致することを緊急制御回路EMCが確
認し系切替回路SEXを動作させ予備系を現用系として
いた。この切替には当然処理中断時間を最小限に押さえ
て行なわれなければならない。従来の現用・予備切替方
式では予備系を現用系と同期運転状賄婆としてから現用
を切離すため若干の切替時間を要していた。また同期運
転回路が複雑となる欠点があった。本発明の目的は前述
の欠点を改善し同期運転回路を使用することなく、主記
憶装置の内容を一致させる緊急制御手段により予備系へ
切替える方式を提供することにある。
This was because the system hardware did not have sufficient reliability; one system's central processing unit had a verification circuit that constantly verified the operation of the other system, allowing for early failure detection. is possible, but
High-speed processing was difficult. Recently, the reliability of hardware has improved, so a standby system is used instead of the above-mentioned verification circuit. This is to keep one system in active use and the other in standby mode, and when a failure occurs in the active system, switch to the standby system. FIG. 1 is an explanatory diagram of this system, in which system #0 has a central processing unit CCO and a main memory MMO, and system #1 has a CCI and MMI, with a synchronous operation circuit SYC between them. and an emergency control circuit EMC. The synchronous operation circuit SYC is configured to distribute the same clock to both systems, compare the operations of both systems, and synchronize interrupts. When a failure occurs in the active system or when switching systems to discover a potential failure in the backup system, the above-mentioned synchronous operation circuit SYC is used to perform emergency control to ensure that the operations of both systems match. Circuit EMC confirmed this and activated the system switching circuit SEX, making the backup system the active system. Naturally, this switching must be performed while minimizing processing interruption time. In the conventional working/standby switching system, the standby system serves as a synchronous operating state cover with the working system, and then the working system is disconnected, which requires some switching time. Another drawback was that the synchronous operation circuit was complicated. SUMMARY OF THE INVENTION An object of the present invention is to improve the above-mentioned drawbacks and provide a system for switching to a standby system using emergency control means that matches the contents of the main memory without using a synchronous operation circuit.

以下図面により本発明の実施例について説明する。Embodiments of the present invention will be described below with reference to the drawings.

第2図は本発明の実施例の構成図を示し、SECは切替
順序制御回路、SSTは系間情報転送回路、GO0,G
O1,GI0,GIIはゲ−ト、CC0,CCIは処理
装置、MM0,MMIは主記憶装置、EMCは緊急制御
回路を示している。第3図は第2図装置の動作説明図を
示している。#0を現用系、#1を予備系として動作ご
せていて系切替が必要となったときは、処理装置CCO
における系切替順序制御回路SECの指令で系間情報転
送回路SSTが動作し、ゲートGIOを制御し予備系の
主記憶装置MMIに対しても書込みを行なわせる。即ち
現用系の処理装置CCOは現用系主記憶装置MMOへの
書込み命令実行により転送データを予備系主記憶装置M
MIにおけるMMOと同一番地に転送して両系主記憶菱
贋の内客を一致させる。そのとき緊急制御回賂EMCも
起動され、系切替回路SEXによって一旦両系の停止・
リセットを行ない次に#1の方に切替える。割込回路I
TPが動作し緊急処理プログラムを議出して制御を開始
する。緊急処理プログラムは予備系のMMI内における
固定番地以降に記憶されているからそれを実行して行く
。緊急処理プログラムの中で緊急制御回路SECのリセ
ット動作が指令され切替が終了する。なおゲートは系切
替動作のため主記憶装置・処理装置の障害発生個所によ
り適宜使用されるため所定ゲートを開くように制御され
る。
FIG. 2 shows a configuration diagram of an embodiment of the present invention, in which SEC is a switching order control circuit, SST is an intersystem information transfer circuit, GO0, G
O1, GI0, GII are gates, CC0, CCI are processing units, MM0, MMI are main storage units, and EMC is an emergency control circuit. FIG. 3 shows an explanatory diagram of the operation of the apparatus shown in FIG. If #0 is operating as the active system and #1 as the standby system and system switching is required, the processing unit CCO
The inter-system information transfer circuit SST operates in response to a command from the system switching order control circuit SEC, controls the gate GIO, and causes writing to be performed also in the spare main memory device MMI. That is, the active processing unit CCO transfers the transferred data to the backup main memory MMO by executing a write command to the active main memory MMO.
It is transferred to the same location as MMO in MI to match the internal customers of both main memory disks. At that time, the emergency control EMC is also activated, and the system switching circuit SEX temporarily stops both systems.
Perform a reset and then switch to #1. Interrupt circuit I
The TP operates, issues an emergency processing program, and starts control. Since the emergency processing program is stored at a fixed address in the standby MMI, it is executed. A reset operation of the emergency control circuit SEC is commanded in the emergency processing program, and the switching is completed. Note that the gates are controlled to open predetermined gates because they are used as appropriate depending on the location of failure in the main storage device/processing device for system switching operations.

このようにして本発明によると同期運転回路を使用せず
に系切替ができるため、複雑な回路を特に使用せず経済
的であり、また切替のための処理中断の時間はマイクロ
秒単位で終了するから、電話交換システムに使用すると
き特に有効である。
In this way, according to the present invention, system switching can be performed without using a synchronous operation circuit, so it is economical without using a particularly complicated circuit, and the processing interruption time for switching can be completed in microseconds. Therefore, it is particularly effective when used in telephone switching systems.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の待機予備方式を説明する図、第2図は本
発明の実施例の構成図、第3図は第2図の動作説明図で
ある。 CC0,CC1・・・・・・処理装置、MM0,MM1
・・・…主記憶装置、EMC・・・…緊急制御回路、S
EX・・・肌系切替回路、SEC……系切替順序制御回
勝、SST・・・・・・系間情報転送回路、GO0,G
O1,GI0,GI1・・…・ゲート、ITP…・・・
割込回路。 第1図第2図 第3図
FIG. 1 is a diagram illustrating a conventional standby system, FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. 3 is a diagram illustrating the operation of FIG. 2. CC0, CC1... Processing device, MM0, MM1
...Main memory, EMC...Emergency control circuit, S
EX...Skin system switching circuit, SEC...System switching order control victory, SST...Intersystem information transfer circuit, GO0, G
O1, GI0, GI1...Gate, ITP...
interrupt circuit. Figure 1 Figure 2 Figure 3

Claims (1)

【特許請求の範囲】[Claims] 1 各々主記憶装置と周辺装置を備えた2系統の処理装
置を現用系・予備系に切替えて使用する情報処理システ
ムの切替方式において、現用系処理装置から予備系処理
装置へ切替えるとき、両系を一旦停止・リセツトさせる
切替順序制御回路と、前記切替順序制御回路の出力を得
て予備系主記憶装置の固定番地から予備系がプログラム
を実行できるようにした緊急制御手段と、予備系の主記
憶装置に対して情報を書込み制御する系間情報転送手段
とを具備し、予備系へ切替えるとき前記系間情報転送手
段により両系主記憶装置の内容を一致させてから前記緊
急制御手段によって予備系へ切替えることを特徴とする
情報処理システムの切替え方式。
1 In the switching method of an information processing system in which two systems of processing units, each equipped with a main memory device and a peripheral device, are switched to the active system and standby system, when switching from the active system to the standby system, both systems a switching order control circuit that temporarily stops and resets the switching order control circuit; an emergency control means that obtains the output of the switching order control circuit and allows the spare system to execute a program from a fixed address in the main memory of the spare system; intersystem information transfer means for writing and controlling information to the storage device, and when switching to the backup system, the intersystem information transfer means makes the contents of the main storage devices of both systems match, and then the emergency control means transfers the contents to the backup system. A switching method for an information processing system characterized by switching to a system.
JP55088681A 1980-06-30 1980-06-30 Information processing system switching method Expired JPS602697B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55088681A JPS602697B2 (en) 1980-06-30 1980-06-30 Information processing system switching method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55088681A JPS602697B2 (en) 1980-06-30 1980-06-30 Information processing system switching method

Publications (2)

Publication Number Publication Date
JPS5714951A JPS5714951A (en) 1982-01-26
JPS602697B2 true JPS602697B2 (en) 1985-01-23

Family

ID=13949565

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55088681A Expired JPS602697B2 (en) 1980-06-30 1980-06-30 Information processing system switching method

Country Status (1)

Country Link
JP (1) JPS602697B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08314746A (en) * 1995-05-12 1996-11-29 Nec Corp Method and device for controlling system switching of duplex processor

Also Published As

Publication number Publication date
JPS5714951A (en) 1982-01-26

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