JPH05151109A - Main storage data assurance mechanism - Google Patents

Abstract

PURPOSE:To prevent the loss of the data stored in an internal main storage when the battery capacity held by a system is limited against the fault of a power supply and then shut down by preparing a special disk device in order to save the data stored the main storage to the disk device at occurrence of the fault of the power supply. CONSTITUTION:A CPU 1 is provided together with a main storage 2, a disk controller 3, an instruction controller 4, a disk device 5, a system 10, a data line 20 set between the storage 2 and the controller 5, an address line 50 set to the storage 2 from the controller 3, an instruction signal line 40 set between the controller 4 and the controller 5, and an interface signal line 30 set between the controller 5 and the device 5. In such a constitution, the time needed for saving the data can be quantititatively decided and it is possible to construct a system that never destroys the data at all in a power supply abnormal state.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system closing process caused by an abnormality in power supply, and more particularly to a method of ensuring main memory data.

[0002]

2. Description of the Related Art Conventionally, as a method of coping with an abnormality in power supply such as power interruption or power reduction, holding a battery device,
When the power supply is cut off, the power input of each device of the system is immediately switched to the power supply from the battery device, and the operating system of the system stores the contents of the main storage device in the disk device (before the power supply of the battery device is exhausted). A general method is to guarantee the data in the main memory by writing the data to the group) and ending the system close processing.

At this time, the writing means writes to each disk device via the system bus and the I / O bus.

[0004]

In this conventional system closing method, since the operating system performs the closing process for each file, the number of accesses to the main storage device and the disk device is large, and the writing speed to the disk is generally high. The transfer capacity of the I / O bus is limited, and no further transfer speed can be expected.

Further, the time required for system closing is affected by the amount of updated data in the main memory, which is different from the data content in the disk device, and it is impossible to quantitatively determine the time of system closing within a fixed time. . For this reason, whether or not the power capacity of a certain battery device is necessary and sufficient for the supply amount for the time required to close the system can be guaranteed only with a certain probability. That is, in order to realize a complete system close without data destruction when the power supply source is abnormal, it is excessively demanded to estimate the maximum time required for the system close and realize the corresponding battery power supply amount.

Therefore, when the power capacity supplied by the battery device is less than the amount of power required for the system closing, the power supply to the main storage device is stopped before the system closing is completed, The process data will be lost.

[0007]

A main memory data guarantee mechanism of the present invention is for saving a main memory data save path other than a system bus for reading data in the main memory device and for writing data on the save path to a disk device. A disk control device, a disk device connected to the disk control device, and a data save instruction control device for controlling an instruction to write data in the main storage device to the disk are provided.

[0008]

The present invention will be described in detail with reference to the drawings. FIG. 1 is a basic configuration diagram of a main memory data guarantee mechanism showing an embodiment of the present invention.

The main memory data guarantee mechanism has a central processing unit 1, a main memory unit 2, a disk unit 5, a disk control unit 3 for controlling this disk unit, and a data saving instruction for controlling the data saving of the main memory unit 2. The disk controller 3 is composed of the controller 4, and receives a data saving instruction through the instruction signal line 40. The disk controller 3 indicates the address of the data to be read by the address line 50. The data in the main storage device 2 is sent to the disk control device 3 by the data line 20, and the data is sent by the interface signal line 30 between the disk control device 3 and the disk device 5.

The instruction signal line 40, the address line 50, and the data line 20 form a main memory data save path.

Next, the operation in FIG. 1 will be described.
When a power supply abnormality is detected and the power supply source is not restored within a certain period of time, the operating system saves data by the system bus 10 so as to close the system before the battery capacity held in the system is exhausted. A power supply abnormality is transmitted to the instruction control device 4. The data evacuation instruction control device 4 which has recognized the power supply abnormality is instructed by the instruction signal line 4
When 0, a data save command is sent to the disk controller 3. Disk controller 3 that received the command
Outputs to the address line 50 while incrementing the address value from the start address of the main memory device 2, fetches the data in the main memory device into an internal buffer in a certain fixed storage block unit, and while synchronizing with the disk device 5, The address is written in the disk device 5. The write time at this time is determined only by the amount of physical storage in the main storage device 2, and a constant system close time is always guaranteed. When the writing is completed, the disk controller 3 transmits a data save signal to the data save instruction controller 4 via the instruction signal line 40. When the data save instruction control device 4 receives the end report from the disk control device 3, the system bus 1
The data saving end signal is sent to the central processing unit 1 by 0, the operating system recognizes the end of the data saving, and completes the system closing process for the main memory data.

After the power supply abnormality is recovered, the operating system gives a load instruction of the data in the disk device to the data save instruction control device 4 through the system bus 10.
After that, the data saving instruction control device 4 gives a data load command to the disk control device 3 through the instruction signal line 40, and receives the data load command.
Transfers the saved data in the disk device to the main storage device 2 and reports the end of data loading to the data save instruction control device 4 via the instruction signal line 40 when the transfer is completed. The data load end signal is transferred to the central processing unit 1 by the, and the operating system recognizes the end of the data load. After that, the operating system again closes the file of the process and returns to the initial phase of the system.

FIG. 2 shows an example of a configuration in which the main memory device is divided into physical block units, and four disk control devices and disk devices are assigned to each main memory block unit.

Main memory blocks 2-1, 2-2, 2-3, 2-4, which are each block of the divided main memory device, and a data save instruction for giving a data save instruction to each of these main memory blocks. The controller 4 and the disk devices 5-1, 5-2, 5-held corresponding to each main memory block unit
3, 5-4, and disk control devices 3-1, 3-2, 3-3, 3-4 for controlling the respective disk devices.
And each disk control device has an instruction signal line 4
A data save instruction is received from the data save instruction controller 4 by 0. Further, each disk control device has an address line 50-1 for the main memory block 2-1, an address line 50-2 for the main memory block 2-2, and an address line 50-2 for the main memory block 2-3. For the address line 50-3 and the main memory block 2-4, the data address to be read is designated by the address line 50-4.

The data in each main memory block is sent from the main memory block 2-1 to the disk controller 3-1 via the data line 20-1, and the data on the main memory device 2-2 is data line 20-2. To the disk controller 3-2 via
The data on the main memory 2-3 is sent to the disk controller 3-3 via the data line 20-3, and the data on the main memory 2-4 is sent to the disk controller 3 on the data line 20-4. -4. Data transfer between each disk controller and the disk device is performed by using an interface signal line as a signal line 30-1 between the disk controller 3-1 and the disk device 5-1 and a disk controller 3-2 and the disk device 5-.
Signal line 30-2 between the two, a signal line 30-3 between the disk control device 3-3 and the disk device 5-3, and a signal line 30-4 between the disk control device 3-4 and the disk device 5-4. Be seen.

Next, the operation of FIG. 2 will be described. As in the case of FIG. 1, when an abnormality in the power supply source is detected and it is determined that there is no prospect of restoration of the power supply source, the operating system of the system causes the central processing unit 1 to use the system bus 10 to execute the data save instruction control unit. Report the power failure to 4. Data evacuation instruction control device 4 that has recognized a power failure
Indicates the disk control devices 3-1 and 3 by the instruction signal line 40.
Send a main memory data save command to -2, 3-3, 3-4. Each disk control device 3-1, 3-2, 3
-3 and 3-4 are address lines 50-1 and 50-, respectively.
Addresses from the start address to the end address of each main memory block are sequentially output to 2, 50-3 and 50-4, and the main memory data is fetched. Then, while synchronizing with the disk device side, the data in the main storage device is written to each disk device. Since the writing time at this time is determined only by the physical storage amount in each storage block, the data saving speed can be expected to improve by the parallel degree due to the division. When the writing is completed, each disk controller notifies the data save instruction controller 4 of the data save completion through the instruction signal line 40. The data save instruction control device 4 transmits a data save end signal to the central processing unit through the system bus 10 when the end report is received from all the disk control devices, and the operating system recognizes the end of data save and saves the main memory data. Completes the system close processing for.

When the power supply abnormality is restored, the operating system sends a load instruction for the data in the disk device to the data save instruction controller 4 via the system bus 10. After that, the data save instruction control device 4 sends the instruction signal line 40 to each disk control device 3-1, 3-2, 3-3, 3-4.
Each of the disk control devices receiving the data load command transfers the saved data in the disk device to the corresponding main memory block, and when the transfer is completed, the data load end is indicated by the instruction signal line 40. It reports to the save instruction control device 4, the data save instruction control device 4 transfers a data load end signal to the central processing unit 1 through the system bus 10, and the operating system recognizes the end of the data load process.

FIG. 3 shows an example of a configuration in which the data saving instruction control device is included in the main memory block, in which the instruction control device 4 and the instruction signal line 40 are not provided, and the command signal line is provided between the disk control device and the main memory block. The configuration is the same as that of FIG.

A command signal line 50-1 and a main memory block 2 are provided between the main memory block 2-1 and the disk controller 3-1.
-2 and the disk controller 3-2 have a command signal line 50
-2, main memory block 2-3 and disk controller 3-3
A command signal line 50-3 is connected between the main memory block 2-4 and the disk controller 3-4 by a command signal line 50-4. A control unit corresponding to the instruction control device 4 of FIG. 2 is held in each main memory block, and each control unit receives a command from the operating system independently. In this case, for the end of data saving and data loading, it is necessary for the operating system side to count the end report from the main memory block that received the corresponding instruction. For example, the operating system determines that it is not necessary to save the main memory 2-2, and the main memory blocks 2-1 and 2-
When instructing 3 and 2-4 to save the data, it is necessary to recognize the end of the data saving when all the reports of the main storage blocks 2-1, 2-3 and 2-4 are completed.

[0020]

As described above, according to the present invention, the system bus and the I / O connected to the main memory device when the power supply source is abnormal.
By saving the main memory data as a physical quantity to the disk by burst transfer using a dedicated path for saving data other than the O bus, it is possible to quantitatively determine the time required for saving the data, and the battery power required for system closing. The supply amount can be determined, and the system holds the battery device having the required electric power amount, thereby enabling the system construction without causing the data destruction which occurs when the power supply source is abnormal.

Further, the main memory device is physically or logically divided into a plurality of parts, and a data save path and a disk device are respectively assigned to the divided main memory block units,
Data saving can be performed in parallel, the data saving time can be shortened, and the capacity of the battery device can be reduced.

Further, the data saving instruction control device is held in the main memory device or a divided main memory block, thereby eliminating the interface between the system bus and the instruction control device and reducing the load on the system bus. It becomes possible to take

[Brief description of drawings]

FIG. 1 is a basic configuration diagram showing an embodiment of the present invention,

FIG. 2 is a block diagram when the main memory device is divided into four as one application example of FIG.

FIG. 3 is a configuration diagram in which a data save instruction control device is divided and accommodated in the main memory block of FIG. 2 as another application example.

[Explanation of symbols]

1 central processing unit 2 main storage unit 3 disk control unit 4 data save instruction control unit 5 disk unit 10 system bus 20 data line between main storage unit and disk control unit 30 interface signal line between disk control unit and disk unit 40 instruction Signal line 50 Address line

Claims (1)

[Claims] 1. An information processing apparatus having a form in which a central processing unit and a main memory are connected to a system bus, and a main memory data saving path provided for reading data in the main memory other than the system bus. A disk controller for writing data on the save path to the disk device, and a disk device connected to the disk controller,
A main memory data guarantee mechanism, which holds a data save instruction controller for controlling an instruction to write the contents of the main memory to the disk.