KR20010015489A - Processor duplication system - Google Patents

Abstract

PURPOSE: A processor duplication system is provided to store all the data, processed in a processor currently in operation, at a memory of a spare processor so that it can reduce a downloading time at a switching mode. CONSTITUTION: The system comprises a first unit, a second unit and a common memory(200). The first unit is connected to the 2n unit via a common bus. The first unit has the same components with the second unit. The first or second unit includes a processor(20a,20b), a ROM(21a,21b), a storage(22a), a buffer(23a,23b) for the common memory(200), and a buffer controller(26a,26b). The buffer controller(26a,26b) controls a write operation of a RAM(24a,24b) and an IO operation of a local bus buffer(25a,25b). The buffer controller(26a,26b) includes a first flipflop, a second flipflop, an OR gate, and a multiplexor. The OR gate performs an OR operation on an output signal of the first flipflop and a state control signal, and then generates a selection signal. The multiplexor selects a local chip select signal or a remote chip select signal as a chip select signal.

Description

Processor Redundancy System {PROCESSOR DUPLICATION SYSTEM}

The present invention relates to a redundancy system, and more particularly, to a processor redundancy system that improves the switching time from a currently operating system to a standby standby system.

In general, a redundant system has two identical systems in the unit, so that if there is a problem with a system that is currently operating, the processing is automatically carried out to the other waiting. Such a redundancy system is to improve the reliability of the system, and is particularly applied to a system requiring real-time processing such as an online system of a bank or a communication exchange system.

1 is a configuration diagram of a conventional redundancy system, and the redundancy system is largely composed of an operation unit and a spare unit. The operating unit and the spare unit are connected to each other by a common bus 17. The common memory 100 constructs a database for shared use by the operation unit and the spare unit, and is located on the boundary line of the two units and connected to the common bus 17.

The operating unit includes a first processor 10a, a first read only memory (ROM) 12a, a first random access memory (RAM) 14a, and a first processor 10a, each connected to a common bus 17. It consists of one buffer 16a. The first processor 10a is responsible for data processing and data input / output control of peripheral devices on the operation unit side. The first ROM 12a stores a program of the first processor 10a. The first RAM 14a receives and records various variables and data necessary for program operation from the first ROM 12a, reads the corresponding variables and data, and provides them to the first processor 10a or the common memory 100. do. The first buffer 16a passes or blocks the input / output data via the common bus 17 between the operation unit side and the common memory 100.

The spare unit includes a second processor 10b, a second ROM 12b, a second RAM 14b, and a second buffer 16b, which are each connected to the common bus 17. Since the peripheral devices of the spare unit have the same structure and perform the same function as the corresponding devices in the operating unit, the following description is omitted.

Now, the operation of the conventional redundancy system in Figure 1 is as follows.

In the normal state of the apparatus, the operating unit side becomes the active state, and the spare unit side becomes the standby state. As the first processor 10a loads a program from the first ROM 12a in the operation unit to start operation, various variables and data on the program are stored in the first RAM 14a. The first processor 10a controls to modify and change variables and data of the first RAM 14a while operating a program according to an external input / output condition. In addition, the first processor 10a controls the input / output direction of the first buffer 16a and stores all the databases on the operation unit side in the common memory 100.

On the other hand, the operating unit side is stopped by the switching conditions such as a failure of the operating unit side, and the spare unit side enters the active state. On the spare unit side, the second processor 10b controls the input / output direction of the second buffer 16b to load all the databases stored in the common memory 100 and to operate the program according to the program stored in the second ROM 12b. Continue on.

However, on the operating unit side before the switching point, the storage time to the common memory 100 is the amount of data to be recorded exceeds the capacity of the first RAM 14a, or is stored in the first RAM 14a at regular intervals. Is loaded into the common memory 100, the contents stored in the first RAM 14a immediately before switching may not be loaded into the common memory 100.

Accordingly, since the second processor 10b on the spare unit side does not download the contents of the first RAM 14a on the operating unit side, the second processor 10b cannot operate in the operation state just before switching, of course, the first RAM. There is a problem that the service interruption state can be maintained for a long time while downloading the content of 14a.

Accordingly, the present invention has been invented to solve the above problems, and the present invention allows all the data processed by the currently running processor to be stored in the memory of the preliminary system in real time, thereby improving the data downloading time when a conversion occurs. The purpose is to provide a processor redundancy system.

The present invention for achieving the above object, the first unit and the second unit performing the operation state and the standby state alternately to store and use the data processed during the operation in a common memory via a common bus (COMMON BUS) In the redundant system, the first unit includes a first processor for controlling peripheral devices of the first unit and processing data, a first memory for storing a program of the first processor, and a control signal of the first processor. The first data storage unit records data of the first unit in an operating state, and records data of the second unit in a standby state, and the common memory or the controller through a common bus under control of the first processor. A first common bus buffer for controlling data input and output with the second unit; The second unit may include a second processor that controls a peripheral device in the second unit and processes data, a second memory that stores a program of the second processor, and an operating state according to a control signal of the second processor. A second data storage unit for recording data of a second unit and recording data of the first unit in a standby state; and data with the common memory or the first unit through a common bus under control of the second processor; And a second common bus buffer for controlling input and output.

1 is a configuration diagram for a conventional redundant system,

2 is a block diagram of a redundancy system according to the present invention;

3 is a detailed circuit diagram illustrating a buffer controller of a storage unit of FIG. 2;

4A is a control signal state diagram for describing an operation of a buffer controller of FIG. 3 when switching from an operating state to a standby state;

4B is a control signal state diagram for describing an operation of the buffer controller of FIG. 3 when switching from a standby state to an operating state.

Explanation of symbols on the main parts of the drawings

20a, 20b: Processor 21a, 21b: ROM

22a, 22b: storage unit 23a, 23b: buffer for common bus

24a, 24b, 500: RAM 25a, 25b, 400: Buffer for Local Bus

26a, 26b, 300: buffer controller 200: common memory

31, 32: flip-flop 33: OR gate

34: Multiplexer

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a configuration diagram of a redundancy system according to the present invention. The system includes a first unit and a second unit connected to each other through a common bus, and a first unit and a second unit transferred through a common bus. It includes a common memory 200 for storing the processing data of. The first unit and the second unit are composed of the same elements as shown in FIG. 2 and have the same function.

The first unit may control a peripheral device in the first unit, and may include a first processor 20a for processing data, a first ROM 21a for storing a program of the first processor, variables and processing data during program operation, and the like. And a first storage section 22a for recording and storing, and a first common bus buffer 23a for controlling input and output of data loaded on the common bus between the common memory 200 and the first unit side. In this case, the first storage unit 22a includes a first RAM 24a, a first local bus buffer 25a, and a first buffer control unit 26a. The first RAM 24a is for recording and updating various variables and data necessary for program operation. The first local bus buffer 25a controls the input / output of data loaded on the local bus LOCAL BUS connecting the common bus and the second RAM 24a. The first buffer controller 26a controls the input / output of the first local bus buffer 25a in accordance with a control signal to control the write operation of the first RAM 24a.

The second unit controls a second processor 20b for controlling peripheral devices in the second unit and processing data, a second ROM 21b for storing a program of the second processor, variables and processing data during program operation, and the like. And a second storage section 22b for recording and storing, and a second common bus buffer 23b for controlling input and output of data loaded on the common bus between the common memory 200 and the second unit side. Here, the second storage section 22b is composed of a second RAM 24b, a second local bus buffer 25b, and a second buffer control section 26b. The second RAM 24b is for recording and updating various variables and data necessary for program operation. The second local bus buffer 25b controls the input / output of data loaded on the local bus LOCAL BUS connecting the common bus and the second RAM 24b. The second buffer controller 26b controls the input / output of the second local bus buffer 25b in accordance with a control signal to control the write operation of the second RAM 24b.

It is a feature of the present invention to record and store in real time the data of the unit side in the current operating state from the unit side in the standby state of the two units. That is, in FIG. 2, when the first unit is in the operating state and the second unit is in the standby state, write data recorded in the first RAM 24a of the first unit is simultaneously written to the second RAM 24b of the second unit. To record. In this way, when the running first unit is dismounted or any switching condition occurs, the standby second unit uses the data stored in the second RAM 24b to maintain the operating state immediately before switching, without interruption. It can be operated.

3 is a detailed circuit diagram illustrating a buffer controller of a storage unit of FIG. 2. The buffer controller 300 includes two flip-flops 31 and 32, an OR gate 33, and a 2-1 multiplexer 34.

The first flip-flop 31 has a reset terminal RESET and receives a power reset signal PW_RST as a clock to output a 'H' (high) level signal. The second flip-flop 32 receives an initialization signal INIT_COM as an input signal and a write control signal WR_CTL as a clock. The output of the second flip-flop 32 is provided to the reset terminal of the first flip-flop 31. The OR gate 33 is an output signal and a state control signal of the first flip-flop 31. ) Is received and provided as a select signal SEL_SIN of the multiplexer 34. The multiplexer 34 selects one of a local chip select signal (LCS) provided from the local station unit and a remote chip select signal (RCS) provided from the remote unit according to the selection signal SEL_SIN. Outputs the chip select signal (CHIP_SEL). The local chip select signal LCS is a chip select signal for the RAM of the own station unit, and the remote chip select signal RCS is a chip select signal for the RAM of the remote unit.

The chip select signal CHIP_SEL of the buffer controller 300 is provided to the enable terminal EN of the output buffer 400 among the local bus buffers 25a and 25b of FIG. 2. The buffer 400 is enabled by the chip select signal CHIP_SEL and receives an address, data, and write control signal (from the motherboard) to receive the corresponding local bus in address bus (ADDR_BUS), data bus (DATA_BUS), and control signal bus. Output via (WR_CTL) respectively. The RAM 500 stores write data input through a local bus.

As a result, the buffer controller 300 accesses the address, data, and write signals loaded on the common bus according to the state control signal and the write control signal of the operation unit, via its own bus, via the remote bus. It controls whether or not to access RAM.

Hereinafter, the operation and effect of the present embodiment will be described with reference to FIGS. 2 to 3.

This embodiment sets the first unit as the operation unit and the second unit as the spare unit when the initial power is turned on.

① First unit (operation unit)

Referring to FIG. 3, when the first power is turned on, the first unit includes a state control signal ( ) To 'H' to indicate that you are operating. In addition, in order to operate as an operation unit, the first processor 20a is driven to load a program from the first ROM 21a to start operation, and store and store variables and data necessary for operation in the RAM 24a to perform initialization. do. After the initialization is completed, the operation state is entered, and the processor 20a controls to read and update the data of the first RAM 24a while advancing the program according to the external input / output condition. The first processor 20a controls the input / output direction of the first common bus buffer 23a to store and use all the databases generated during operation in the common memory 200.

As shown in FIG. 3, the first buffer controller 26a uses the 'H' level state control signal ( The local chip selection signal LCS is selected through the multiplexer 34 according to the " As a result, all the variables and data generated by the processor 20a on the operation unit side are accessed to the first RAM 24a of the local station.

Now, referring to FIG. 4A, a process of switching the first unit to the initialization state-> operation state-> standby state will be described. 4A is a control signal state diagram of the buffer control unit of the first unit.

(a) is a power reset signal (PW_RST), (b) is an initialization signal (INIT_COM) signal, the transition from 'L' to 'H' at the time when the initialization state is completed after the power is turned on.

(c) state control signal ( ), 'H' in the initialization and operation state section, and transitions to 'L' in the standby state section. (d) is the write control signal WR_CTL.

(e) is the selection control signal SEL_SIN of the multiplexer, which is 'H' in the initialization and operation state sections, and has a phase opposite to the (d) signal in the standby state sections.

(f) is a chip select signal (CHIP_SEL). In the initialization and operation state according to the (e) signal, a local chip select (LCS) signal is output and the data generated by the processor 20a of the host unit in operation is stored in RAM ( Store in 24a). On the other hand, in the standby state, whenever a write operation occurs in the RAM 24b of the remote unit in operation according to the signal (e), the remote chip select (RCS) signal is output to generate data generated by the processor 20b of the other station in operation. Is stored in the RAM 24a.

② Second unit (spare unit)

In the buffer control unit 22b of the second unit, referring to FIG. 3, the output of the first flip-flop 31 is activated to 'H' by the power reset signal PWM_RST at the time of initial power-on, and the state control signal ( ) To 'L' to indicate that you are a spare unit. At this time, the OR gate 33 performs an OR operation on the output 'H' and the state control signal 'L' of the first flip-flop 31 and outputs the selection signal 'H'. LCS).

As the local chip select signal LCS is selected, the second unit enters an initialization state for operating as a spare unit. In the initialization state, the processor 20b is driven to start operation by loading a program from the ROM 21b, and initialization is performed by storing variables and data necessary for operation in the RAM 24b of the host (see FIG. 2). .

The second unit enters the standby state according to the initialization signal INIT_COM indicating that the initialization is completed. That is, the initialization signal is activated at 'H' upon completion of initialization and is input to the second flip-flop 32. The second flip-flop WR_CTL receives the write control signal WR_CTL as a clock signal and provides an output to the reset terminal RESET of the first flip-flop 31. Then, whenever a write operation occurs in the operating unit side RAM (RAM 24a of the first unit), the first flip-flop 31 of the buffer control unit 26b on the spare unit side outputs an 'L' signal, The multiplexer 34 outputs the remote chip select signal RCS provided from the operating unit side.

As the remote chip selection signal RCS is output from the buffer controller 26b, the processor 20b cannot access the RAM 24b of the host unit. On the other hand, the common bus buffer 23a of the first unit in operation and the common bus buffer 23b of the second unit are activated so that the processor 20a of the first unit writes to the RAM 24a through the common bus. Each time the access is made, the RAM 24b of the second unit also writes and accesses data loaded on the common bus.

On the other hand, when switching occurs due to a switch or a switch on the operating unit (first unit) side, the processor 20b of the second unit in the standby state downloads the data stored in the common memory 200 for operation. Complete the preparation work. Subsequently, the second unit operates as an operation unit and continues operation while accessing the RAM 24b of the local station that stores data that has occurred just before switching.

Now, a process of switching the second unit to the initialization state-> standby state-> operation state will be described with reference to FIG. 4B. 4B is a control signal state diagram of the buffer control unit of the second unit.

(a) is a power reset signal (PW_RST), (b) is an initialization signal (INIT_COM) signal, the transition from 'L' to 'H' at the time when the initialization state is completed after the power is turned on.

(c) state control signal ( ), 'L' in the initialization and standby state section, and transitions to 'H' in the operation state section. (d) is the write control signal WR_CTL.

(e) is the multiplexer's selection control signal SEL_SIN, which is 'H' in the initialization state section, has a phase opposite to the (d) signal in the standby state section, and is 'H' in the operating state section.

(f) is a chip select signal (CHIP_SEL), which outputs a local chip select (LCS) signal in the initialization state section according to the (e) signal, and stores initial data in the RAM 24b by the processor 20b of the local station. do. When the standby state is entered after the initialization is completed, the remote chip select signal RCS is output whenever a write operation occurs in the RAM 24a of the other station in operation. The remote chip select signal RSC receives data generated by the first processor 20a through the common bus buffer 23a of the first unit and the common bus buffer 23b of the second unit. 2 is stored in the RAM 24b. When switching from the standby state to the operating state, data generated by the second processor 20b of the local station is stored in the second RAM 24b of the local station by the local chip selection signal LCS.

As described above, in the related art, the data being processed in the operating unit is stored only in the RAM of the own station and is not shared with the spare unit, so a service interruption may occur while the spare unit is converted to the operating unit and the data is reloaded. there was. According to the present invention, data stored in the RAM of the operating unit is simultaneously stored in the RAM of the spare unit, so that it is not necessary to download the data of the RAM of the operating unit at the time of switching, so that the program can be operated without interruption. In addition, the present invention can be applied to a real-time system such as a communication service that has a significant effect on the service during the switching time.

Claims (4)

In the redundancy system in which the first unit and the second unit performing the operation state and the standby state alternately store and use data processed during operation in a common memory through a common bus. The first unit, A first processor controlling a peripheral device of the first unit and processing data; A first memory for storing a program of the first processor; A first data storage unit configured to record data of the first unit in an operating state according to a control signal of the first processor, and to record data of the second unit in a standby state; And A first common bus buffer controlling data input / output with the common memory or the second unit through a common bus under control of the first processor; The second unit, A second processor for controlling peripherals in the second unit and processing data; A second memory for storing a program of the second processor; A second data storage unit configured to record data of the second unit in an operating state according to a control signal of the second processor, and to record data of the first unit in a standby state; And And a second common bus buffer controlling data input / output with the common memory or the first unit through a common bus under the control of the second processor. The method of claim 1, wherein each of the first data storage unit or the second data storage unit, RAM for recording and updating various variables and data necessary for the program operation; A local bus buffer for controlling input / output of data loaded on a local bus connecting the common bus and the RAM; And And a buffer controller to control the write operation of the RAM by controlling input / output of the local bus buffer according to a control signal. The method of claim 2, wherein the buffer control unit A first flip-flop having a reset terminal RESET and activated by a power reset signal PWM_RST; A second flip-flop which receives the initialization signal INIT_COM by a write control signal WR_CTL and provides it as a reset terminal of the first flip-flop; An output signal and a state control signal of the first flip-flop OR gate to receive OR and output the select signal SEL_SIN; And According to the selection signal SEL_SIN, any one of a local chip select signal (LCS) provided from a local station unit and a remote chip select signal (RCS) provided from a remote unit may be selected. And a multiplexer for outputting to CHIP_SEL). The buffer of claim 2, wherein the local bus buffer includes: And the address, data, and write control signals are received through the local bus by the chip select signal (CHIP_SEL) and stored in the RAM.