JPS6236268B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an error control method in a main memory of an information processing device, and particularly to an error control method in a main memory connected to a plurality of central processing units. In general, when error control methods read failure information from one of multiple central processing units, if the central processing unit that requested the readout is the same as the central processing unit that was accessing the failure information, the failure information is stored. The storage of the current fault information is finished and new fault information can be stored. This will be explained in detail based on the block diagram of FIG. As shown in FIG. 1, two central processing units 1 and 2 are connected to the main storage device A, and request signals instructing the start of operations from each central processing unit are sent via request signal lines 12 and 1.
3, the main memory control unit 9, error reporting unit 5,
6. Input to terminal 51 of error storage control unit 11,
A command signal that instructs the operation content is input to the command signal switching unit 3 via command signal lines 14, 15, and a command signal line 20, which is the output of the command signal switching unit 3, is connected to the command error detection unit 7 and main memory control. address signal lines 16 and 17.
is input to the address signal switching unit 4, the address signal line 22 which is the output of the address signal switching unit 4 is input to the address error detection unit 8 and the storage unit 10, and the command which is the output signal line of each error detection unit 7, 8 is input to the address error detection unit 8 and the storage unit 10. The error signal line 21 and the address error signal line 23 are input to the terminals 50 of the reporting sections 5 and 6 and the error storage control section 11. Error report signal lines 18 and 19, which are the outputs of the respective error report sections 5 and 6, are connected to the respective central processing units 1 and 2.

Next, to explain the operation of the block diagram in FIG. 1, when a request comes from either the central processing unit 1 or 2, a command signal and an address signal are sent to the central processing unit from which the request signal was sent at each switching unit 3 or 4. For example, after being switched to the central processing unit 1 side, it is input to the command error detection section 7 and the address error detection section 8, and errors are detected. If a command or address error is detected at this time, these error signals are input to the error storage control unit 11, and if the request is the central processing unit 1, it is input to the error reporting unit 5, and this error report is sent. An error report is sent from the unit 5 to the central processing unit 1 that issued the request via the error report signal line 18. (If the request is from the central processing unit 2, the error signal is sent to the error reporting unit 6,
An error report is made to the central processing unit 2 via the error report signal line 19. ) This error report is made in the form of aggregating various errors detected in the main memory, so even if a command error and an address error occur at the same time, the central processing unit will not be notified that some kind of error has occurred. Detailed information such as whether it is a command error, address error, one error or multiple errors is not reported. This detailed error information is temporarily stored in the error storage control unit 11 in the main memory A, and the central processing unit that receives the error report later reads out the stored detailed error information. After reading, it can be reset or updated.

In the conventional error control method, after the central processing unit that received the error report, that is, the central processing unit that was accessing it when the failure occurred, reads out the error information, this central processing unit issues a command to reset the error information. I was trying to reset it by issuing a .

In order to explain the conventional error control method regarding the error storage control section 11 that controls this, a detailed explanation will be given based on the block diagram shown in FIG.
As shown in FIG. 2, an error signal line 103 (first
(corresponding to the command error signal line 21 and address error signal line 23 in the figure); and a signal line 4 for identifying the central processing unit input to the storage means 101 (corresponding to the request signal lines 12 and 13 in FIG. 1); A storage means 101 for storing these error information, an error signal line 105 (corresponding to 24 in FIG. 1) that supplies the error information read from the storage means 101 to an error readout circuit (not shown), and a central A signal line 106 (corresponding to 25 in FIG. 1) for identifying the processing device, a reset signal 107 (corresponding to reset signal 26 in FIG. 1) input to the storage control means 102, and a signal line for controlling the storage means 101. It consisted of a storage control means 102 and a control signal line 108 which is an output of the storage control means 102 and is input to the storage means 101. Next, to explain the operation shown in FIG. 2, when various errors such as a command error or an address error occur in the main memory device A, the storage control means 102 sends an error signal to the storage means 101 based on the error signal as well as an error signal to the central processing unit. After storing the identification signal (corresponding to the request signal in FIG. 1), the contents of the storage means are held until an error reset instruction is received from the central processing unit. On the other hand, when the central processing unit, which is the access source when an error occurs, receives an error report from the main storage device A, it reads detailed error information from the storage means 101,
Thereafter, an error reset instruction was issued to the main storage device A to reset the storage means 101.

An example of the operation of the error control method in this case is shown in the third section.
This will be explained with reference to the figures.

The time chart of the operation example shown in FIG. 3 is a normal R/W access error a from the central processing unit 1.
This is a case where no error occurs after that. When error a occurs, this error a is stored in the storage means and is also stored in the central processing unit 1.
An error report is issued. As a result, the central processing unit 1 performs error reading at the time of the next access, but if the central processing unit 2 performs an access before this access, the error a is retained for the time being. When the access reaches the central processing unit 1, the access causes the central processing unit 1 to read out the error a from the storage means.
This makes it possible for the central processing unit 1 to reset the error a, so that the next access by the central processing unit 1, that is, the access (assuming that the access occurs immediately), will reset the error. In response to this, the storage means resets the error a. After that, access by the central processing unit 2,
The data is then accessed by the central processing unit 1. Note that even if error b occurs in the above-mentioned access, the error b is only reported to the central processing unit 2 and the storage means is not reset, so that error b is not stored. Further, even if an error is read from the central processing unit 2 prior to reading and resetting the error a from the central processing unit 1, the system will not be reset. In this way, conventional error control methods require memory cycles for error reset, and in order for the central processing unit to reset the error, it is necessary to avoid conflict with memory accesses of other central processing units. Since the error reset is delayed in order for other central processing units to access the data, there is a drawback that even if an error occurs, the period during which it is not stored increases.

The purpose of the present invention is to store and maintain error information in a main memory connected to a plurality of central processing units;
The objective is to provide an error control method that allows automatic updates.

Another object of the present invention is to provide an error control method that reduces memory cycles required for memory access to main storage.

Furthermore, another object of the present invention is to provide an error control method in which the period during which error information cannot be stored is short.

The error control method of the present invention supplies identification information indicating the accessed central processing unit together with access information when accessing a main storage connected to a plurality of central processing units, and detects a failure while accessing the main storage. A central processing unit that stores fault information and supplied identification information in the fault storage means when the fault occurs, and reads and accesses the stored fault information when the access information indicates reading of the stored fault information. At the same time, the comparison means compares the stored identification information with the supplied identification information, and when they match, controls the storage control means to a state where the fault storage means can store new fault information. consists of things.

In the error control system of the present invention, when the central processing unit receives the error report and reads out the error information, it immediately resets the error information without issuing an error information reset command from the central processing unit. The error storage control section 11 that controls this will be explained with reference to the block diagram of one embodiment shown in FIG.

A storage means 101, an error signal line 103 input to the storage control means 102 (corresponding to the command error signal line 21 and address error signal line 23 in FIG. 1), and an identification line for supplying an identification signal from the central processing unit. A signal line 104 (corresponding to the request signal lines 12 and 13 in FIG. 1), a storage means 101 that receives these signal lines as input, and an output signal of the storage means 101 that is sent to an error readout circuit (not shown). Error signal line 105 (2 in FIG.
4), an identification signal line 106 (corresponding to 25 in FIG. 1) for supplying the identification information stored in the storage means 101, and an identification signal line 104 and an identification signal line 106. Comparison means 109;
A signal line 111 input to the storage control means 102 from the output of the comparison means 109, and an error read designation signal line 110 (first
(corresponding to the error read designation signal line 26 in the figure), a storage control means 102, and a control signal line 108 which inputs the output of the storage control means 102 to the storage means 101.

Next, the operation will be explained below. Address errors, command errors (Figure 1 shows two errors, but other errors that can be detected in the main memory, such as write data errors, read data errors, etc.) When various errors such as "good" are detected, the storage control means 102 enables the storage means 101 to store the various error information and the identification information of the central processing unit of the access source based on the error signal line 103. It can be stored. The stored error information can be read out using an error read command instructed by the central processing unit. The identification information at the time of error occurrence stored in the means 101 is inputted via the signal line 106,
A determination is made as to whether or not the accesses are from the same central processing unit, and the result is supplied to the storage control means 102 via the signal line 111. Based on the error read command and the above-mentioned judgment result, the storage control means 102 continues to hold the contents of the storage means 101 even after the error read operation is completed, unless the error read operation is from the same central processing unit. In the case of an error read operation from the central processing unit, the contents of the storage means 101 can be reset at the same time as the error read operation is completed, so that new error information and identification information of the central processing unit can be stored. can.

The operation of the error control system of the present invention will be explained with reference to FIG.

In FIG. 5, similar to FIG. 3, an error a occurs upon access from the central processing unit 1, but no error occurs thereafter. In addition,
If error b occurs in the subsequent access from the central processing unit 2, an error report is also made to the central processing unit 2, so that an error read operation is also received from the central processing unit 2. However, error b is not stored. Even if the error read operation from the central processing unit 2 comes earlier than the error read operation from the central processing unit 1, the error a is stored until the error read operation from the central processing unit 1 arrives, so the central processing unit 1 makes it possible to read error a. After the central processing unit reads the error information that occurred due to its own access, the error is automatically reset in the main memory after reading the error without instructing the main memory to reset the error. The central processing unit does not need to be involved in resetting the error, but only needs to read out the error, so no memory cycles are required for resetting the error. Although the above-described embodiment shows the case where the error read designation signal 110 is supplied to the storage control means 102, it is clear that the same effect can be expected by supplying it to the comparison means 109.

As explained above, the present invention reduces the error reset operation cycle when a main memory error occurs by automatically resetting or updating the error after the error read operation based on the identification information of the central processing unit. This has the effect of making memory access control of the central processing unit easier.

[Brief explanation of the drawing]

FIG. 1 is a block diagram for explaining the present invention and a conventional error control method, FIG. 2 is a block diagram showing an example of an error storage control section for explaining a conventional error control method, and FIG. 3 is a conventional error control method. 4 is a block diagram showing an embodiment of the error storage control unit for explaining the error control method of the present invention. FIG. 5 is a time chart of the operation according to the error control method of the present invention. This is a time chart. In the figure, A...main storage device, 1 and 2...
...Central processing unit, 3...Command signal switching section, 4
...Address signal switching unit, 5 and 6...Error reporting unit, 7...Command error detection unit, 8...Address error detection unit, 9...Main memory control unit, 10
... Storage section, 11 ... Error storage control section, 12 and 13 ... Request signal line, 14 and 15
... Command signal line, 16 and 17 ... Address signal line, 18 and 19 ... Error report signal line, 20 ... Command signal line, 21 ... Command error signal line, 22 ... Address signal line, 23 ...
...Address error signal line, 24...Error signal line which is an output signal, 25...Central processing unit identification signal line which is an output signal, 26...Reset signal line or error read designation signal line, 101...Storage means, 102... Storage control means, 103... Error signal line, 104... Central processing unit identification signal line,
105...Error signal line which is an output signal line, 10
6...Central processing unit identification signal line which is an output signal,
107...Reset signal line, 108...Control signal line, 109...Comparison means, 110...Error read designation signal, 111...Output signal line of comparison means.

Claims (1)

[Scope of Claims] 1. When accessing a main storage connected to a plurality of central processing units, identification information indicating the accessed central processing unit is provided together with access information, and a failure occurs during access to the main storage unit. when the fault information and the supplied identification information are stored in the fault storage means, and when the access information indicates reading of the stored fault information, the stored fault information is read and accessed by the central processing unit. At the same time, the comparison means compares the stored identification information with the supplied identification information, and when they match, controls the storage control means to a state in which the fault storage means can store new fault information. error control method.