JPH06103056A - Address controller - Google Patents

Abstract

PURPOSE:To perform the correction/updating of a software without being limited with a replacing part of software or the number of piece of software by directly exchanging data and to save a time for program processing by preventing program execution speed from being lowered. CONSTITUTION:At the time of correcting/updating the program code or fixed data of a read only memory(ROM) 1, information showing the presence of fault is previously written at the correspondent address of a fault storage device 9, and replacing information is written at the correspondent address of a replacement storage device 7. Next, when a CPU 2 requests read through an address bus 3 to the ROM 1, the fault storage device 9 and the device 7 are accessed as well. Concerning this request, a register 11 of a selector 5 performs the logical operation based on a previously set logic value and fault information, when the fault information shows the absence of the fault, the ROM 1 is selected and when the information shows the presence of the fault, the replacement storage device 7 is selected, and the CPU 2 reads these selected data through a data bus 13.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an address control device for an information processing device, and more particularly to an address control device for correcting / changing a program code and fixed data stored in a read-only device.

[0002]

2. Description of the Related Art Software is always accompanied by obstacles, and the program code and fixed data are often modified or changed by changing or improving specifications.

However, the program code and fixed data on the ROM, which is a read-only storage device (hereinafter referred to as ROM), cannot be easily changed due to economic reasons or time problems.

For this reason, the modified or changed alternative program code or fixed data is stored in the secondary storage area and is expanded and used on a RAM which is a read / write storage device (hereinafter referred to as RAM). Alternative measures are needed.

Such alternative measures include "software hook" and "hardware break" as conventional techniques.

The "software hook" is a technique for inserting an instruction for transferring control in advance in a RAM program into a ROM program to substitute it.

In this case, the correction on the ROM program
Since it is not possible to determine whether or not there is a need at that time even in a place where there is no change, an instruction to transfer control to the RAM is written.

The "hardware break" is provided with a register storing an address to which a patch is applied in the device, compares the contents of the register when fetching program data or a fixed code, and if they match, controls the program on the RAM. It is a transfer technology.

[0009]

However, in the "software hook" of the conventional address control device, there is a limitation in the place where the software can be modified / changed, the execution speed is reduced, and the data is adapted to the data. Is difficult.

Further, in the "hardware break" of the conventional address control device, if the addresses are compared sequentially, the execution speed is reduced, and if the addresses are compared in parallel, the comparators for the number of comparisons are required and the circuit scale becomes large. Therefore, there is a problem that the number of alternatives is limited due to economic reasons.

Therefore, an object of the present invention is that there is no limitation on the place or number of software that can be modified or changed, and that data can be directly replaced. It is to provide an address control device capable of saving

[0012]

In order to achieve the above-mentioned object, the address control device of the first invention is a CPU and a read-only memory device in which a program code and fixed data are read by a command of this CPU. And a failure storage device that is activated at the same time corresponding to the program code and the fixed data, and stores failure-presence and non-failure data in advance, and at the same time that is activated corresponding to the above-mentioned program code and the fixed data and is recorded beforehand. The alternative storage device storing the alternative program code and the fixed data, and the reading of the read-only storage device is stopped only when the faulty data is read from the failure storage device, and the alternative program code of the alternative storage device and And a selector for reading and selecting fixed data.

The address control device of the second invention is the above alternative storage device constituted by a single storage device that outputs the same code in response to a plurality of read requests of different addresses.

The address controller of the third invention is the above-mentioned C.
A selector that includes at least a register writable by PU, performs a logical operation of the output of the fault memory device and the contents of the register, and selects the output of the read-only memory device and the output of the alternative memory device based on the result. Is characterized in that.

An address control device according to a fourth aspect of the present invention is the selector for selecting an upper address for identifying a chip of a plurality of read-only storage devices according to the presence / absence of a fault output from the fault storage device. And

[0016]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a functional block diagram showing an embodiment of the address control device of the present invention.

FIG. 2 is an example in which the alternative program code of FIG. 1 is longer than the original program code.

In FIG. 1, the read-only storage device 1 is, for example, a ROM, and a read request from the CPU 2 is designated by a lower address from the address bus 3, and its output is connected to the input terminal of the selector 5.

In this embodiment, two read-only storage devices 1 are used.
However, more than one is possible.

The alternative storage device 7 is, for example, a RAM, and is designated by a lower address similarly to the read-only storage device 1, and its output is connected to the input terminal of the selector 5.

In this embodiment, there is one alternative storage device 7, but it is also possible to use a plurality of storage devices.

The failure storage device 9 is, for example, a RAM, and C
A read request from the PU 2 is designated by the address bus 3, and its output is connected to the select terminal SEL of the selector 5 as the upper bit of the bit string having the upper bit of the address bus 3 as the lower bit.

Since the fault information stored in the fault memory device 9 may be, for example, 1 bit of "0" without fault and "1" with fault, the number of memory cells is significantly smaller than that of the read-only memory device 1.

The selector 5 is composed of an arithmetic element and the like, has a register 11 inside, and has an input terminal IN.
The read-only storage device 1 connected to B and C or the alternative storage device 7 connected to the input terminal INA, the information stored in the register 11 and the failure storage device 9 connected to the select terminal SEL. It is selected by a signal generated from the upper address, and the program code and fixed data are sent from the output terminal OUT of the selector 5 to the CPU 2 via the data bus 13.

The register 11 is constructed so that it can be read and written by the CPU 2. (Not shown) Further, in this embodiment,
Although the register 11 is inside the selector 5,
And may be outside independently.

In the address control device of the present invention thus constructed, for example, when the program code stored in the read-only storage device 1 has a bug and needs to be corrected,
Prior to the execution of the program, the faulty information "1" is stored in the memory cell of the fault memory device 9 corresponding to the address of the program code that needs to be corrected.

Of course, it is necessary to store information "0" indicating no failure in the memory cell corresponding to the address having no failure.

Further, the alternative program code for correcting the bug is stored in the alternative storage device 7 corresponding to the address of the program code that needs to be corrected.

In this case, the alternative program codes for the plurality of read-only storage devices 1 can be stored in one alternative storage device 7 as long as the lower addresses are different.

Even if the lower addresses overlap,
It is also possible to judge which alternative program should be used by referring to the actually accessed address value and perform the branching process.

Next, when executing the program code, an alternative process is performed as follows.

When the CPU refers to the program code stored in the read-only memory device 1, it designates an address through the address bus 3 to designate a certain memory cell of the memory device.

Therefore, the fault memory device 9, the read-only memory device 1 of the address having the same lower address portion as the designated address, and the alternative memory device 7 respectively output.

Fault information output from the fault storage device 9,
A select signal to be input to the selector 5 is created with the upper address of the designated address.

If the address designated by the CPU 2 is an address having no fault, the fault storage device 9 outputs information "0" indicating no fault.

Therefore, the selector 5 outputs one of the outputs of the read-only storage device 1 according to the input selector signal and sends the program code to the CPU 2 through the data bus 13.

This has the same function as addressing, in which the upper address is decoded to generate a chip select signal, and the lower address identifies a memory cell in the read-only memory device 1.

On the contrary, if the address designated by the CPU 2 is a faulty address, the fault storage device 9 outputs the fault information "1".

Therefore, the selector 5 outputs the output of the alternative storage device 7 to the data bus 13 according to the input selector signal.
To send the program code to the CPU 2.

At this time, as shown in FIG. 2, when the program code to be replaced is longer than the original program code, the register 11 in the selector 5 is set to force the output of the alternative storage device 7. Can be adopted.

That is, at the beginning of the alternative program code,
The register 11 may be set, and at the end of the processing of the alternative program, the register 11 may be cleared to return to the original program.

[0043]

As described above, according to the present invention, since the area corresponding to the capacity of the faulty storage device can be freely replaced, there is no limitation on the place or number of alternatives and it is economical.

Further, since it is not necessary to embed a special program code in advance, it is possible to save the time for modification / change and to prevent the execution speed from being lowered because the sequential determination by the address is not performed.

Further, in response to a reference request from the CPU,
Since the replacement is realized by switching the output signal, the data can be directly replaced.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an address control device of the present invention.

FIG. 2 is an example in which the alternative program code of FIG. 1 is longer than the original program code.

[Explanation of symbols]

 1 Read Only Storage Device 2 CPU 3 CPU (Address Bus) 5 Selector 7 Alternate Storage Device 9 Fault Storage Device 11 Register 13 CPU (Data Bus)

Claims (4)

[Claims] 1. A CPU, a read-only storage device from which a program code and fixed data are read by an instruction of the CPU, and a simultaneous start-up corresponding to the program code and fixed data, with and without fault data in advance. A failure storage device in which is stored, an alternative storage device that is activated at the same time in response to the program code and fixed data, and stores a prerecorded alternative program code and fixed data; and faulty data from the failure storage device. Reading is stopped only when is read,
An address control device comprising: a selector for reading and selecting an alternative program code and fixed data of the alternative storage device. 2. The address control device according to claim 1, wherein the alternative storage device comprises a single storage device that outputs the same code in response to a plurality of read requests of different addresses. 3. A register which is at least writable by the CPU, which performs a logical operation of the output of the fault memory device and the contents of the register, and based on the result, the output of the read-only memory device and the alternative memory device. The address control device according to claim 1, wherein the address control device is the selector for selecting an output. 4. The address according to claim 1, wherein the selector is a selector for selecting an upper address for identifying a chip of a plurality of read-only storage devices according to the presence / absence of a fault output from the fault storage device. Control device.