JPS61131049A - System for preserving contents in storage device from being swept out - Google Patents

System for preserving contents in storage device from being swept out

Info

Publication number
JPS61131049A
JPS61131049A JP59252383A JP25238384A JPS61131049A JP S61131049 A JPS61131049 A JP S61131049A JP 59252383 A JP59252383 A JP 59252383A JP 25238384 A JP25238384 A JP 25238384A JP S61131049 A JPS61131049 A JP S61131049A
Authority
JP
Japan
Prior art keywords
memory
memory bank
time
storage device
bank
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59252383A
Other languages
Japanese (ja)
Inventor
Hajime Miyazawa
宮沢 元
Kazuhisa Makihata
巻幡 和久
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
NEC Engineering Ltd
Original Assignee
NEC Corp
NEC Engineering Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, NEC Engineering Ltd filed Critical NEC Corp
Priority to JP59252383A priority Critical patent/JPS61131049A/en
Publication of JPS61131049A publication Critical patent/JPS61131049A/en
Pending legal-status Critical Current

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  • Techniques For Improving Reliability Of Storages (AREA)
  • Debugging And Monitoring (AREA)

Abstract

PURPOSE:To quickly perform the trial operations of resisting while preserving fault information even when a state where the saving to an external device cannot be made occurs, by continuously operating a primary storage device as a storage device while preserving its content. CONSTITUTION:A condition where a CPU 11 can make access to a memory 67 and another memory 8 memory bank 1) is considered as an example. When a trigger input I1 is turned on against a control circuit 1 under such a condition, the control circuit 1 reads out the time of a clock 4 and writes the time in a time register 2 corresponding to the memory bank 1 and, at the same time, a trigger factor in a register 3. In addition, the control circuit 1 switches a switching circuit 5 from the memory bank 1 to another memory bank 2 (memory 9). As a result, the CPU 11 can make access to the memories 9 and 6. Since the trigger factor, the switched time, and the content of the memory when the factor I1 occurs are preserved in the memory bank 1 in such a way, the resising can be performed quickly by using the memory bank 2.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、記憶装置の制御方式に関し、特に障害発生時
等における記憶内容保存方式に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a control method for a storage device, and more particularly to a storage content preservation method when a failure occurs.

〔従来の技術〕[Conventional technology]

従来、機器故障対策として磁気ディスク装置等の外部記
憶装置へのメモリ内容を必要部分について退避する方式
をとっていた。
Conventionally, as a countermeasure against equipment failure, a method has been adopted in which necessary portions of memory contents are saved in an external storage device such as a magnetic disk device.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

これは通常は確実な方法であるが、外部記憶装置を使用
するために退避に時間がかかり、機器の再立上げ直前の
内容を退避する場合、故障発生から再立上げ完了までの
時間を多く要した。また退避にCPUが関与するために
、基本ソフトウェアにダメージがあった場合にメモリ内
容の保存ができない場合があった。
This is usually a reliable method, but it takes time to save because it uses an external storage device, and when saving the contents immediately before restarting the device, it takes a long time from the time a failure occurs until the restart is completed. It took. Furthermore, since the CPU is involved in saving, there are cases where the memory contents cannot be saved if the basic software is damaged.

本発明は、上記欠点を解決し、外部記憶装置への退避が
できない状況が生じた場合、もしくは、外部記憶装置の
ない装置の故障が発生したときの情報保存を行い、再立
上げ試行を迅速に行うことを可能とした装置を提供する
ものである。
The present invention solves the above-mentioned drawbacks and saves information when a situation occurs where it is impossible to save data to an external storage device, or when a failure occurs in a device without an external storage device, so that restart attempts can be made quickly. The purpose of this invention is to provide a device that makes it possible to perform the following tasks.

〔問題点を解決するだめの手段〕[Failure to solve the problem]

本発明はバッテリーバックアップ等により不揮発化し、
記憶装置内の特定の領域に関して同一の記憶領域に対し
てn(n≧2)面のメモリバンクと、CPUが該メモリ
バンクのいずれか1面をアクセス可能とする記憶バンク
の切替回路と、すべてのメモリバンクの内容を読出す読
取シ回路と、メモリバンク対応の状態保持用レジスタと
、時刻を示す時計と、状態保持用レジスタ及び時計を制
御する制御回路とを有し、該制御回路は、トリガ入力に
よってそのトリガの種類及び時刻を状態保持用レジスタ
に書込み、切替回路を起動し、記憶バンクを切替える動
作を可能としたことを特徴とする記憶装置内容の掃出し
保存方式である。
The present invention is made non-volatile by battery backup etc.
Regarding a specific area in a storage device, n (n≧2) memory banks for the same storage area, a memory bank switching circuit that allows the CPU to access any one of the memory banks, and all A read circuit for reading the contents of the memory bank, a state holding register corresponding to the memory bank, a clock indicating the time, and a control circuit for controlling the state holding register and the clock, and the control circuit includes: This is a method for purging and saving the contents of a storage device, which is characterized in that the type and time of the trigger are written in a state holding register by a trigger input, a switching circuit is activated, and the storage bank can be switched.

〔実施例〕 次一本発明の実施例について図面を参照して説明する。〔Example〕 Next, an embodiment of the present invention will be described with reference to the drawings.

第1図において、本発明装置は切替トリガ入力■1〜X
4を持つ制御回路1と、時計4、トリガ入力の時刻を保
持するメモリバンクに対応する3組の時刻レジスタ2と
、トリガ入カニ1〜r4のいずれかの入力があったかを
示すトリガ要因レジスタ3と、メモリバンクを切替える
切替回路5と、メモリアクセスのバンクを選択するバン
ク選択回路7と、3面のメモリバンク8.9.10.と
、切替機能のないメモリ6と、時刻レジスタ2、トリガ
要因レジスタ3、及び8.9.10の内容を読出す読出
し回路12とからなる。ここで、CPUIIからはメモ
リ6及びメモIJ 8.9.10の3面のうち1面がア
クセス可能である。
In FIG. 1, the device of the present invention has switching trigger inputs ■1 to X.
4, a clock 4, three sets of time registers 2 corresponding to memory banks that hold the time of trigger input, and a trigger factor register 3 that indicates whether any one of trigger input crabs 1 to r4 has been input. , a switching circuit 5 for switching memory banks, a bank selection circuit 7 for selecting a bank for memory access, and three memory banks 8.9.10. , a memory 6 without a switching function, and a readout circuit 12 for reading out the contents of the time register 2, trigger factor register 3, and 8.9.10. Here, one of the three sides of the memory 6 and the memo IJ 8.9.10 can be accessed from the CPU II.

次に実施例の動作を説明する。Next, the operation of the embodiment will be explained.

現在、メモリ6及びメモリ8(バンク1)が、CPUI
Iからアクセス可能とする。この状態で、制   制御
回路1に対しトリガ入カニ1がONとなった場合、制御
回路1は、時計4から時刻を読出し、バンク1対応の時
刻レジスタ2へ時刻を書込む。またバンク1対応のトリ
ガ要因レジスタ3にトリガ入力r1があったことを表示
する。
Currently, memory 6 and memory 8 (bank 1) are
It can be accessed from I. In this state, when the trigger input crab 1 is turned on for the control circuit 1, the control circuit 1 reads the time from the clock 4 and writes the time to the time register 2 corresponding to bank 1. Also, it is displayed that there is a trigger input r1 in the trigger cause register 3 corresponding to bank 1.

制御回路1は同時に切替回路5に対しメモリバンク1か
らメモリバンク2への切替を指示する。切替回路5はメ
モリバンク1を非使用中とし、メモリバンク2を使用中
とする。これによって、CPU11はメモリ(バンク2
)9とメモリ6についてアクセス可能となる。CPUI
Iから見たとき、メモリのアドレス空間についてメモリ
バンク1とメモリバンク2とは同一アドレス空間である
At the same time, control circuit 1 instructs switching circuit 5 to switch from memory bank 1 to memory bank 2. The switching circuit 5 makes the memory bank 1 not in use and makes the memory bank 2 in use. As a result, the CPU 11 uses the memory (bank 2).
)9 and memory 6 become accessible. C.P.U.I.
When viewed from I, memory bank 1 and memory bank 2 have the same address space of the memory.

以上の動作によって、メモリのバンク1からバ/り2へ
切替った要因工1の表示、切替った時刻の表示及び切替
の要因工1が発生したときのメモリのバンク1の内容の
保存が可能となる。そしてメモリのバンク2を使って再
立上げを行うことを可能とする。トリガ入力11〜I4
を障害要因に割当てることにより、障害時の回復と障害
解析がともに容易になる。
Through the above operations, the cause of switching from memory bank 1 to bank 2 is displayed, the time of switching is displayed, and the contents of memory bank 1 are saved when the cause of switching 1 occurs. It becomes possible. Then, it is possible to restart using memory bank 2. Trigger input 11-I4
By assigning failure factors to failure causes, both recovery and failure analysis become easier.

〔発明の効果〕〔Effect of the invention〕

本発明は以上説明−したように、1次記憶装置の内容を
保存しながら、装置としての動作の継続を可能とするこ
とによシ、障害の早期回復、発見を行なうことができる
効果を有するものである。
As explained above, the present invention has the effect of enabling early recovery and discovery of failures by allowing the device to continue operating while preserving the contents of the primary storage device. It is something.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の実施例をブロック図で示した回路図で
ある。
FIG. 1 is a circuit diagram showing an embodiment of the present invention in a block diagram.

Claims (1)

【特許請求の範囲】[Claims] (1)記憶装置内に少なくとも2面のバッテリーバック
アップ等により不揮発化したメモリバンクと、CPUか
ら常時いずれか1面のメモリバンクをアクセス可能にし
、またこのCPUからアクセス可能な記憶バンクを切替
える切替回路と、メモリバンクの内容を随時読取り可能
とする読取り回路と、時刻を示す時計と、状態保持用の
レジスタと、該時計及びレジスタを制御する制御回路と
を有し、該制御回路は外部からのトリガまたはCPUに
よるトリガ等の入力により切替回路を動作させ、メモリ
バンクをローテーションして切替えるとともに、切替え
た時刻と入力したトリガの要因を記憶バンクに対応した
状態保持用のレジスタに記録し、記憶バンクが切替った
時刻、その要因およびCPUから切離し内容を保存して
いる記憶バンクの内容を後で読取ることを可能としたこ
とを特徴とする記憶装置内容の掃出し保存方式。
(1) A switching circuit that allows at least two memory banks in the storage device to be made nonvolatile by battery backup, etc., and one memory bank that is always accessible from the CPU, and also switches the memory bank that can be accessed from this CPU. , a reading circuit that can read the contents of the memory bank at any time, a clock that shows the time, a register for holding the state, and a control circuit that controls the clock and the register. The switching circuit is operated by a trigger or an input such as a trigger from the CPU, rotates and switches the memory bank, records the switching time and input trigger factor in the state holding register corresponding to the memory bank, and then switches the memory bank. 1. A system for purging and saving the contents of a storage device, characterized in that it is possible to later read the time when the switching occurred, the cause thereof, and the contents of a storage bank that is separated from a CPU and stores the contents.
JP59252383A 1984-11-29 1984-11-29 System for preserving contents in storage device from being swept out Pending JPS61131049A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59252383A JPS61131049A (en) 1984-11-29 1984-11-29 System for preserving contents in storage device from being swept out

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59252383A JPS61131049A (en) 1984-11-29 1984-11-29 System for preserving contents in storage device from being swept out

Publications (1)

Publication Number Publication Date
JPS61131049A true JPS61131049A (en) 1986-06-18

Family

ID=17236551

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59252383A Pending JPS61131049A (en) 1984-11-29 1984-11-29 System for preserving contents in storage device from being swept out

Country Status (1)

Country Link
JP (1) JPS61131049A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0339148U (en) * 1989-08-25 1991-04-16
JPH0339147U (en) * 1989-08-25 1991-04-16

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0339148U (en) * 1989-08-25 1991-04-16
JPH0339147U (en) * 1989-08-25 1991-04-16

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