JPH10133918A - Computer system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To construct a computer system easily and sufficiently reliably realizing a memory damp by using a memory of overlapped address space so as to switch to a normal using time and an initializing time for using. SOLUTION: A condition signal for address decoding corresponding to the normal using time and an initialization executing time by address control circuits 16 and 18 through the use of first RAMs 13 and 14 and second RAM 15 and at the time of pressing a reset switch 17, a part of a memory address space in normally used first RAMs 13 and 14 is assigned to a memory address space in second RAM 15 and the pertinent area of first RAM assigned at the time of normal use is assigned to another area in a memory address space in first RAM when the memory damp is started, only second RAM 15 is used for operation and contents in first RAMs 13 and 14 at the point of the time when the switch 17 is depressed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer system capable of collecting failure information such as a memory dump with high reliability, and particularly suitable for a relatively small system such as a personal computer.

[0002]

2. Description of the Related Art In a computer system, when a software or hardware failure occurs and the system must be stopped, it is necessary to collect and analyze failure information such as a memory dump. Generally, the contents of the memory are read out and written to the external storage by forcibly shifting the processing of the CPU to a specific routine in the memory by a key operation from a switch or a keyboard provided in the system in advance. Take the method of implementation.

In a relatively small-scale computer system such as a personal computer, the NMI (Non-Maskable Interrupt), which is an interrupt requiring the highest priority processing, is implemented in order to inexpensively shift the CPU processing forcibly.
In addition to activating a memory dump processing routine using "upt; non-maskable interrupt", a reset signal generated by pressing a reset switch provided in the system is often used.

[0004]

However, according to the prior art described above, according to the method using the NMI interrupt, the dump processing routine itself in the memory is destroyed due to a failure, or the external storage including the bus lock is used. It cannot be handled in the event of a file I / O failure. On the other hand, when the method of activating the CPU reset by the reset switch uses a part of the memory before starting the dump processing routine, the contents of the part of the memory may be destroyed to initialize the part. .

[0005] The present invention has been made in view of the above circumstances,
It is an object of the present invention to provide a computer system which can realize a memory dump easily and with sufficient reliability by using a memory having an overlapping address space and switching between a normal use and an initialization. And

[0006]

According to the computer system of the present invention, a ROM in which a program for initializing the system is stored, and a program stored in an external storage are called as needed, and the contents are written. A first RAM used as a work area, and a second RAM used only when the initialization is performed, with a part of the address space of the first RAM being overlapped and assigned.
And an address control circuit for generating a condition signal for address decoding corresponding to the normal use or the initialization, and the first control which is normally used by the output of the address control circuit during the initialization. Of the memory address space of the second RAM is allocated to the memory address space of the second RAM, and the first R
An address decoder for generating a signal for allocating a corresponding area of the AM to another area of the memory address space of the first RAM; and the first and second RAMs according to the ROM output
And an initialization control circuit for performing system initialization using Further, a ROM in which a program for initializing the system is stored, and a program stored in an external storage are called as needed,
The first RAM in which the contents are written and also used as a work area, and the second RAM in which a part of the address space of the first RAM is allocated and used in an overlapping manner
And a second RAM having an overlapping address space is selected in addition to the first RAM at the time of data writing, and only a normally used first RAM is selected at the time of data reading. An address control circuit that generates a condition signal for address decoding corresponding to each of normal use or initialization execution, and an initialization control based on the condition signal output from the address control circuit according to the ROM output at the time of initialization execution. By selecting only the area where the address of the first RAM overlaps and initializing using this area, the contents written in the area where the addresses of the second RAM and the first RAM do not overlap are stored. And an initialization control circuit for holding.

As a result, the CPU is reset by a switch provided in the system, so that initialization is performed in an arbitrary state, and all memory contents at the time when the switch is pressed are retained. All contents can be stored in the external storage without destroying the memory contents.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, reference numeral 11 denotes a CPU serving as a control center of the system. A ROM 12 stores a program for executing system initialization. 13 and 14 are R
In addition to an operating system (OS), the memory is an AM and is a main memory used as a working area of a program being executed or a program, and an upper area H and a lower area L of an address are indicated by broken lines, respectively. Are indicated by. Hereinafter, description will be made simply by referring to the RAMs 14 and 15. Reference numeral 15 denotes a RAM ′,
In the embodiment of the present invention, a part of the address space overlaps with the address space of the RAM 13 which is a lower part corresponding to the address.
It may be used as an alternative to AM13. 16 is an address decoder. The address decoder 16 uses the CP
Decodes the address generated by U11 to RAM
13, 14, and 15 are provided. Reference numeral 17 denotes a switch which is used to activate a memory dump program. Reference numeral 18 denotes a control circuit which, when the switch 17 is pressed, sends a reset signal (RS
T) and a decode switching signal (DSEL) to the address decoder 16. Reference numeral 19 denotes a floppy disk device (FDD) which stores a memory dump program and is loaded into the main storage devices 13 and 14 for use when necessary. 20 is a hard disk drive (H
DD), which stores an operating system (OS) and is loaded into the main storage devices 13 and 14 for use when necessary. Reference numeral 21 denotes an external storage including an extended memory used for saving memory data at the time of memory dump. In the embodiment of the present invention, the external storage 20 is shown independently for the purpose of understanding the explanation, but the FDD device 18 or the H
The area may be allocated in the DD device 19. Reference numeral 22 denotes a system bus to which the above-mentioned blocks are commonly connected, a plurality of lines for address, data, and control are formed, and a data exchange path between the blocks is provided.

FIG. 2 is a diagram showing an address map of a memory of the computer system shown in FIG. 1 expanded on the memory. In the figure, the left block shows the address map when the decode switching signal is “false”, and the right block shows the address map when the decode switch signal is “true”.

FIG. 3 is a flowchart showing an initialization procedure of the computer system shown in FIG.

The operation of the computer system shown in FIG. 1 will be described below in detail with reference to FIGS.

The decode switching signal (DSEL) is normally "false", and the address viewed from the CPU 11 by the signal output through the address decoder 16 is assigned as shown in the left block of FIG.
The OS stored in 0 operates on the RAM 13 and the RAM 14.

When the switch 17 is pressed, the control circuit 1
8 generates a reset signal (RST).
1 is initialized and an instruction is read from a specific address of the ROM 12 and executed. On the other hand, the decode switching signal (DSEL) becomes “true” by the control circuit 18 and the signal output from the address decoder 16 causes C
The memory address as seen from the PU 11 is as shown in the right block of FIG. The initialization is performed according to the flowchart shown in FIG. 3. Here, since the decode switching signal (DSEL) is “true”, the CPU 11
Only the initialization of '15 is performed, and it operates only on the RAM '15. The contents of the RAMs 13 and 14 constituting the main memory are held as they are when the switch 17 is pressed. The memory dump program is started from the FDD device 19 and
It operates by using only AM'15, and RAM13, RAM
14 is saved in the external storage device 21.

When the switch 17 is pressed, the CPU 11 is reset, and the initialization program is executed from a specific address on the ROM 12. Here, the decode switching signal (DSEL) is checked, and if DSEL is “true”, initialization of the RAM 15 is executed,
4 is retained. In the case of "false", the RAM 13, 1
4 is executed. RAM 13, 14 or R
After the initialization of AM'15, the input / output device is further initialized, an operating system (OS) is loaded from the FDD device 19 or the HDD device 20 into the RAMs 13 and 14, and thereafter, the OS or the OS loaded into the RAMs 13 and 14 or Control transfers to the application. According to the computer system described above, since the CPU 11 is reset by the switch 17, the initialization is performed in an arbitrary state, and all the memory contents at the time when the switch 17 is pressed are held. All contents can be stored in the external storage 21 without destroying the contents.
Can be stored in

FIG. 4 is a diagram showing a memory address map of another embodiment of the computer system shown in FIG. 1 expanded on a memory. In the figure, the left block shows the address map when the decode switching signal is “false”, and the right block shows the address map when the decode switch signal is “true”. As can be seen from the figure, the RAM 13 and the RAM '15 are arranged on the same memory address, and when writing data from the CPU 11,
3, both RAM'15 are selected, and only RAM 13 is selected at the time of data reading.

FIG. 5 is a flowchart showing the initialization procedure of the computer system shown in FIG. 1 when the address map shown in FIG. 4 is adopted.

Hereinafter, the operation of the computer system shown in FIG. 1 will be described in detail with reference to FIGS.

Normally, a decode switching signal (DSEL)
Is “false”, and the address decoder 16
The memory address seen from 1 is configured as shown in the left block of FIG. The RAM 13 and the RAM 15 are arranged on the same memory address. The control circuit 18 decodes the data so that both the RAM 13 and the RAM 15 are selected when writing data from the CPU 11 and only the RAM 13 is selected when reading data. The address decoder 16 is designed to generate signals (DSEL) and select each of them.

When the switch 17 is pressed, the control circuit 1
8 generates a reset signal (RST).
1 is initialized, and the instruction is executed from a specific address of the ROM 12. On the other hand, by the control circuit 18,
The decode switching signal (DSEL) becomes “true”, and the memory address viewed from the CPU 11 by the address decoder 16 is as shown in the right block of FIG.

Initialization operates according to the flowchart shown in FIG. 5. However, since the decode switching signal (DSEL) is "true", the CPU 11 only initializes the RAM 13, operates only on the RAM 13, and operates the RAMs 15 and The contents of the RAM 14 are held as they are when the switch 17 is pressed. The memory dump program is started by the FDD device 19, operates using only the RAM 13, and saves the contents of the RAM'15 and the RAM 14 to the external storage 21.

When the switch 17 is pressed, the CPU 11 is reset, and the initialization program is executed from a specific address on the ROM 12. Here, the decode switching signal (DSEL) is checked, and when this DSEL is “true”, the initialization of the RAM 13 is executed, and the RAM′15,
14 is retained. In the case of "false", the RAM 13,
Then, initialization of the RAM'15 is executed. RA
After the initialization of the M13 or the RAMs 13 and 14 and the RAM'15, the input / output device is further initialized, and the operating system (OS) is loaded from the FDD device 19 or the HDD device 20 into the RAM'15 and the RAM14. '15, O loaded into RAM 14
Control moves to S or application.

According to the computer system described above,
Since the CPU 11 is reset by the switch 17,
Since the initialization is executed in an arbitrary state and all the memory contents at the time when the switch 17 is pressed are held, all the contents can be stored in the external storage 21 without destroying the memory contents. .

[0024]

As described above, the present invention employs a configuration in which a memory having an overlapping address space is used and switching between normal use and initialization is performed, and a CPU is standardly provided in the system. Since the reset is performed by the switch, initialization is performed in an arbitrary state, and since all the memory contents at the time when the switch is pressed are retained, the contents of the external storage device are not destroyed without being destroyed. Data can be saved. Therefore, collection and analysis of fault information such as a memory dump can be easily realized, which also contributes to high reliability of the system.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing an address map of a memory of the computer system shown in FIG. 1 expanded on the memory;

FIG. 3 is a flowchart showing an initialization procedure of the computer system shown in FIG. 1;

FIG. 4 is a diagram showing an address map, which is another embodiment of the memory of the computer system shown in FIG. 1, expanded on the memory;

5 is a flowchart showing an initialization procedure of the computer system shown in FIG. 1 when the address map shown in FIG. 4 is adopted.

[Explanation of symbols]

11 CPU, 12 ROM, 13 first RAM (lower), 14 first RAM (higher), 15 first RA
M, 16 ... address decoder, 17 ... switch, 18 ...
Control circuit, 19: floppy disk drive (FDD),
20: Hard disk drive (HDD), 21: External storage device, 22: System bus.

Claims (8)

[Claims] 1. A ROM for storing a program for initializing a system and a program stored in an external storage device are called up as necessary, and their contents are written and used as a work area. The first RA
M, a part of the address space of the first RAM is overlapped and assigned, and the second RAM is used only at the time of initialization. An address control circuit for generating a condition signal for decoding, and a part of the memory address space of the first RAM, which is normally used, is stored in the memory address of the second RAM by the output of the address control circuit at the time of initialization. An address decoder for generating a signal for allocating a corresponding area of the first RAM allocated to the space and allocated to the other area of the memory address space of the first RAM during normal use, and the first decoder according to the ROM output. , Second
And an initialization control circuit for performing system initialization using the RAM. 2. The computer system according to claim 1, wherein a reset switch provided in the system is used to instruct an address control circuit for generating a condition signal to switch memory selection. 3. When a reset switch is pressed, initialization is started from a specific address of a ROM.
The first RAM or the second RAM is selected by checking the output of the address control circuit, and either of them is initialized by the initialization control circuit. 3. The computer system according to claim 2, wherein an operating system is read and control is transferred to the operating system. 4. When the memory dump is activated, the second
4. The computer system according to claim 3, wherein the computer system operates only using the RAM, and saves the contents of the first RAM to an external storage device when the switch is pressed. 5. A ROM in which a program for initializing the system is stored, and a program stored in an external storage are called up as necessary, and the contents thereof are written and used as a work area. 1 RAM
And a second RAM in which part of the address space of the first RAM is allocated and used in an overlapping manner, and a second RAM having an overlapping address space in addition to the first RAM when writing data. Address control for generating a condition signal for address decoding corresponding to normal use or initialization execution so that only the first RAM normally used is selected at the time of data reading. When the circuit and the initialization are executed, only the area where the address of the first RAM overlaps is selected based on the condition signal output from the address control circuit according to the ROM output, and initialization is performed using this area. A second RAM and an initialization control circuit for holding contents written in an area where addresses of the first RAM do not overlap with each other. Computer system that. 6. The computer system according to claim 5, wherein a reset switch provided in the system is used to instruct an address control circuit for generating a condition signal to switch memory selection. 7. When a reset switch is pressed, initialization is started from a specific address of a ROM,
By checking the output of the address control circuit, the first RAM and the second RAM, or only the area where the address of the first RAM overlaps, is selected, and after initialization by the initialization control circuit, 7. The computer system according to claim 6, wherein input / output initialization is performed, an operating system is read from an external storage, and control is transferred to the operating system. 8. When the memory dump is activated, the first
Operates only using the area where the address of the RAM of the second RAM overlaps, and the second RAM at the time when the switch is pressed.
8. The computer system according to claim 7, wherein the contents written in an area where the address of the first RAM and the first RAM do not overlap are saved in an external storage device.