JPS59121557A - History information storage system in information processor - Google Patents

Abstract

PURPOSE:To collect much history information without remarkable circuits increase by using a part or all of buffer memories as a history memory. CONSTITUTION:When 0 is set to a register 14, a memory 9 of level 3 is used as a buffer memory. A write data is written in a storage element of the address of the register 9. When 1 is set to the register 14, the memory 9 of level 3 is used as a history memory. A control circuit 15 transmits a control signal representing a timing to write history information selected by the selector 19 to the storage element of the selected address by a selector 20 to the memory 9. The history information written in the storage element of the designated address at each timing when the control signal is transmitted is frozen so as not to be rewritten into new history information if any error occurs in an information processor.

Description

DETAILED DESCRIPTION OF THE INVENTION a. Technical Field of the Invention The present invention relates to a method for storing history information in an information processing apparatus, which is used when a failure occurs in the information processing apparatus.

b. Prior Art and Problems In an information processing device, history information indicating the status of device content points is stored in a memory called a history memory at each timing.

If some kind of failure occurs within the device, storage is prohibited. If the state of the device content point is stored in this way, when a fault occurs in the device, the cause of the fault can be easily analyzed.

By the way, as described above, this history memory is used to store history information for analyzing the causes of failures, so it is not possible to reduce the number of circuits to this history memory Kl. Therefore, the information stored in the history memory is also limited. Historical information such as data and addresses with large pit widths tended to be omitted. .

C. Purpose of the Invention Therefore, the present invention provides a method for collecting a large amount of history information without significantly increasing the number of circuits by using part or all of a set-unchangeable buffer memory as a history memory. It is something to do.

d.Accomplishment of the Invention Therefore, in the present invention, in an information processing apparatus equipped with a buffer memory having an associative level of numbers, switching is made to at least one 1 μ level data input section and address input section of the buffer memory. When installing a circuit (
, an address counter that is incremented in a predetermined cycle M, and a mode indicating circuit are provided, and when the mode indicating circuit indicates the normal mode, the switching circuit switches between tJ, When address input and data input are selected and the previous mode instruction circuit indicates the diagnostic mode, H2 selects the contents of the address counter as the address input, and also selects the contents of the address counter as the data input, and also selects the contents of the address counter as the data input. !
A feature is that π information is selected.

e. Embodiment of the Invention FIG. 1 is an example of a buffer memory in an information processing apparatus to which an embodiment of the present invention can be applied. This buffer memory is set-associative and has 1024 sets and 4 linkage levels.

/ The entry includes an address field, data storage, etc. In FIG. 1, 1 is an address register, 2 is a set address holding register, 3 is a write data register, 4 is a selector, 5 is a read data register, 6 is a level O memory, 7 is a level 1 memory, 8 is level 2 memory, 9 is level 3 (7)l memory, 1(It
~13 indicate the ordinary circuits, respectively.

To record the data and block address in register 3 in four levels of memories 6 to 9,
A set address is given to memories 6 to 9 from register 2. Then, a certain algorithm (for example,
The stored data, and 0... are stored in one memory element selected from the memory element 9 with the oldest block address.
And insert the block address. When reading out memory, data, and programs, a set address is input to memories 6 to 9 out of a certain block address and set address in register IK.

7 (Sends the data stored in the storage element of each memory corresponding to the nocent address to the selector 4, and sends the forward and quad addresses to circuits 10 to 13.Circuit) In 0 to 13, memories 6 to 9 The block address extracted from 6 elements is compared with the block address in register 1.

If there is a match among both block addresses compared in circuits 10 to 13, the selector 4 (the block address and the memo extracted from tii-c of that block address) is y') and the read data are selected and sent to the register 5.

FIG. 2 shows an embodiment of the present invention applied to level 30 memory 9 of the buffer memory of FIG. Zunahachi memory 9 is used as a history memory (14 is a mode instruction register, 1
5 is a control circuit, 16 is a history stop register,
17 is a history address register, 18 is an adder circuit, and 19.20 is a selector.

When the register 14 is set to 10'', the level 3 memory 9 is used as a buffer memory.

The circuit 15 instructs the selector 19 to select the write data sent from the register 3, and the selector 20 to select the address sent from the register 2. The write data is then written to the storage element of the register 9 at that address.

When "Town" is set in the register 14, the level 3 memory 9 is conveniently used as a history memory.

ll! Jlj3 ] 5 if, the selector 19 is instructed to select the address sent from the circuit 17 to the Ii'7 history information sound information receiver 20 at each point in the 5 devices, respectively. Further, the circuit 15 sends a control signal to the memory 9 indicating the timing at which the history information selected by the selector 19 is damaged, to the memory element at the address selected by the selector 20.

Further, each time a control signal indicating the timing of filling is sent from the circuit engineer 5, the circuit 18' adds 1 to the address in the register 17 and stores it in the register 17 again. The history information written in the storage element of the designated address at each timing when the control signal is sent is frozen so that it will not be rewritten with new history information if some kind of failure occurs in the information processing device. At the same time, circuit 1
A control signal from 5 to memory 9 inhibits the addition operation of circuit 18. When reading history information from the frozen memory 9, a circuit 15 sends an open side j signal to the selector 4 indicating the timing to read the history information from the memory 9 to the register 5. Also, each timing (c, register 1
7 K g Self 1 is the address 'J't (assumed to be n)
Then, while sequentially adding 1, the history information in the numerator of the address in the memory 9 is read out.

When n becomes 1023, without adding 1 to 1 again from O, o -1 工 ('HIIIEJ mon fa 'a
: IT/C"7-uJ 3.

If the history information of the register 3 is to be obtained, the register 16 may be omitted. Furthermore, if two memories are used as history memories, it is possible to obtain twice as much history information.

f Effects of the Invention According to the present invention, although the amount of information stored in the buffer memory is reduced, when the amount of information stored in the buffer memory may be reduced to some extent, for example, when trying to operate the information processing device on a trial basis, In such cases, a history memory capable of storing a large amount of history information can be provided by simply adding a small number of circuits.

[Brief explanation of the drawing]

FIG. 1 shows an example of a backup memory in an information processing device to which an embodiment of the present invention can be applied. ] is an address register, 2 is a seven-node address holding register, 3 is a write data register, and 4 is a selector. , 5 is a read data register, 5 to 9 are memories, and JO-13 is a comparison circuit. FIG. 2 shows an example of the present invention applied to the level 30 memory 9 of the battery 7 memory shown in FIG.
14 is an instruction register, 15 is a control 1141 circuit, 16
The history memory register 17 is a history address register, 18 is an addition 1 path, and 1.9.20 is a selector.

Claims (1)

[Claims] In an information processing device equipped with a buffer memory having a plurality of associative levels, a switching circuit is provided in a data input section and an address input section of at least one associative level of the buffer memory, and the switching circuit is incremented at a predetermined period. An address counter and a mode instruction circuit are provided, and the switching circuit selects an address input and data input common to other associative levels when the mode instruction circuit indicates the normal mode; A method for storing history information in an information processing apparatus, characterized in that when indicating a diagnostic mode, the contents of the address counter are selected as an address input, and status information to be acquired as a history is selected as a data input.