JPS6180342A - Memory control device - Google Patents

Abstract

PURPOSE:To prevent a memory control device from accessing to a failed memory part by storing the accumulated value of chip size values in respective words of a readable table memory on the basis of the high-order address of an output from an adder and adding the output of the memory to an input address signal by the adder. CONSTITUTION:Reading data from the table memory 1 is added to the input address signal from a central processor by the adder 3 to form and output a real memory address and the high-order address of the output is decoded by a decoder 2 to select the corresponding work from the memory 1. The accumulated value of the chip size values is stored in respective words of the memory 1 in every detection of an error from the diagnosis result in each chip size of the central processor is stored in respective words of the memory, so that the memory can be accessed by jumping a chip memory range including the failed position.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a memory control device, and in particular, when a defective chip portion of a memory is detected, the defective portion can be automatically controlled not to be accessed. The present invention relates to a memory control device.

Prior Art Conventionally, when a central control unit checks the memory for each chip size and detects a defect, it simply displays the defective chip. Since conventional memory control devices only access memory designated by input address signals, defective chips must be replaced. In order to replace a defective chip, the memory package containing the defective chip must be replaced and repaired, and this replacement work takes a considerable amount of time, and the system must not be operated until the repair is completed. I can't. In general, there is a considerable amount of memory capacity, and it is often possible to operate the system sufficiently even with the memory capacity excluding the failed part, but even in such cases, the above-mentioned replacement work is required to remove the failed memory chip. Therefore, there are disadvantages in that memory cannot be used effectively and the system must be stopped for a long time.

OBJECTS OF THE INVENTION It is an object of the present invention to solve the above-mentioned conventional drawbacks, and to provide a memory control device that can automatically control access to a memory failure portion when a memory failure is detected, thereby improving the effective use of memory. The objective is to reduce system down time.

Structure of the Invention The memory control device of the present invention includes, in a central processing unit capable of diagnosing all memories for each chip size, an adder that adds an output value of a table memory described later to an input address signal and outputs a real memory address; a table memory that can be read by the upper address outputted from the adder, and each word of the table memory is provided with information about the chip size each time an error is detected from the diagnosis result for each chip size of the central processing unit. It is characterized by storing cumulative values.

Embodiments of the Invention Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

That is, a table memory 1, a decoder 2 for reading table memory 1, and 1 an addition circuit that adds read data from table memory 1 to an address signal input from a central processing unit (not shown) to create and output a real memory address. It is equipped with a container 3. The decoder 2 decodes the upper address of the real memory address output from the adder 3 and selects the corresponding word in the table memory 1.

Therefore, the address signal input from the central processing unit is
The data value read from the table memory 1 is converted into an added real memory address by the upper address outputted by the adder 3, and then output.

FIG. 2 is a diagram showing the total memory having three defective memory ranges, each of which has addresses X1 to XI.
+a −1, X2~X2 + cx−1.

It is in the range of X3 to X3+α-1. The memory consists of a set of n chips each having 1 chip and α bits to form an α to 1/1 chip memory size with a width of 1 word and n bits.
The chip memory size constitutes a memory of M (an integral multiple of α) words in total. Address X1,X
, and x3 are the start addresses of a 1-chip memory size each having a defective location, and their lower addresses are all 0°.

FIG. 3 is a diagram showing details of table memory l, and M
/α word capacity, each word having a capacity of ” of said memory.
It can be specified by a second address. That is, one word corresponds to one chip memory size of the memory. Now, assuming that words X1 +
1, “O゛”, word x, ~x2-1, α,
2α is stored in words x2 to X3-1, and 3α is stored in words after word X3. For example, when the central processing unit detects the first defect when diagnosing each chip memory size with the initial diagnosis program, the starting address
Table memory 1 corresponds to the defective chip indicated by 1.
α is stored in word X1 of Then, 2α is stored in word x2 of table memory 1, and 2α is sequentially stored in each subsequent word. When a defective chip is detected next, 3α is stored in word x3 of table memory 1. Store and from then on (7) ry
-F Set each word of table memory 1 by storing all 3α.

It is easy to make each word position of the table memory above correspond to the upper address of the address for the memory, and in this embodiment, the addresses x, , x2
, Xa, etc. and word position X1 + X2
+x3 are the same value.

Next, the operation of this embodiment will be explained. I when the address signal input from the central processing unit has a value less than X1
f. Since the data value read from the table memory 1 in FIG. 1 is "O", the adder 3 outputs the input address signal as it is as a real memory address. Next, for example, when address x1 is input, decoder 2
By decoding the first address outputted by adder 3, the value α stored in word x1 of table memory l is read out, and adder 3 reads input address X! To,
The value α read from the table memory l is added and output as a real memory address x1+α. Therefore, the chip memory range including the fault location is skipped and the next fault-free chip memory is accessed. When the real memory address output by the adder 3 is less than x2, the above is the same, but when the input address from the processing device becomes X2 - α, the real memory address becomes X2, and 2α is output from the table memory l. The input address X from the processing device is read out.
2α is added to 1−α, X2 +α is output as a real memory address, and the defective memory range from X2 to X2 +α−1 is skipped. Thereafter, if the real memory address output by the adder 3 is less than x3, access is similarly made using the real memory address obtained by adding 2α to the input address. Then, when the input address from the processing device becomes x3-2α, the output of the adder 3 becomes x3, and 3α is read from the table memory 1 and added to the input address x3-2α. Therefore, the real memory address at this time is X3+α
Therefore, the defective memory range of addresses x3 to X3+α-1 is skipped and accessed. Input addresses X3-2α and higher are similarly accessed using real memory addresses obtained by adding 3α to the input address value.

That is, in this embodiment, the memory can be accessed using a real memory address that automatically skips the defective range without being aware of the defective range of the memory. That is,
It is possible to automatically (logically) remove defective parts of memory, and as long as the overall memory capacity is not insufficient, there is no need to replace defective parts of memory. This has the effect of quickly recovering from a knockdown.

Effects of the Invention As described above, the present invention includes a table memory storing data values to be added to the input address according to the diagnosis result for each l-chip memory size, and writes 112 to the input address signal. Since the configuration is configured so that the value obtained by adding the data values read from the table memory is output as the real memory address, the memory defect range is automatically (logically)
It is possible to remove it. Therefore, it is possible to save the trouble of replacing defective parts of the memory, to make effective use of the memory, and to reduce system down time.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. FIG. 2 is a diagram showing an example of a memory including a defective portion, and FIG. 3 is a diagram showing details of the table memory of the above embodiment. In the figure, 1: table memory, 2: decoder, 3:
Adder, α: 1 chip memory size, x, , x2 , x
3: Start address of defective memory chip・X+
+X2, X3: Each word of table memory. Figure 2.1 Kanme-kana Liatlus

Claims (1)

[Claims] In a central processing unit capable of diagnosing all memories for each chip size, an adder that adds an output value of a table memory described later to an input address signal and outputs a real memory address;
a table memory that can be read by the upper address outputted from the adder, and each word of the table memory is stored with a chip size information each time an error is detected from the diagnostic results for each chip size of the central processing unit. A memory control device characterized in that a cumulative value of values is stored.