JPH06131897A - Cache memory - Google Patents

Abstract

PURPOSE:To provide a cache memory device which can replace a faulty circuit with a stand-by circuit without cutting these circuits by a polysilicon fuse or a laser. CONSTITUTION:A defective entry that is diagnosed by a test for shipment of products is previously stored in a programmable ROM 23 and then written in an entry register 14 in a reset period. Then the accesses are switched between a redundant memory and a regular memory by the reference given to the register 14. Thus a satisfactory memory test is carried out and a faulty circuit can be replaced with a stand-by circuit in a short reset period. Furthermore the contents of the register 14 undergoe the comparison cuncurrently with the decoding of an address so that the time is never wasted even if an access is given to the stand-by circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache memory, and more particularly to a cache memory including a redundant circuit.

[0002]

2. Description of the Related Art In recent years, a cache memory that helps a data processing device to access at high speed has been built into the data processing device.
Moreover, the built-in cache memory tends to have a large capacity. On the other hand, as the technology advances, the area of the memory cell is reduced, so that a larger memory capacity can be obtained in the same area and the above tendency is met, but there is a problem that the yield is reduced.

In order to prevent such a decrease in yield in an LSI, a technique has already been proposed in which a redundant memory circuit is built in a cache memory as a spare circuit. This is to replace the faulty circuit with a spare circuit by cutting the wiring with a polysilicon fuse or a laser.

However, in this case, a step is required for diagnosing in the manufacturing process and replacing a circuit judged to be defective with a spare circuit. This requires time for diagnosis and a device for diagnosis and replacement. In the case of a small amount of product such as a cache memory, there is a problem that the time and the device lead to cost increase.

In order to avoid this, for example, Japanese Patent Laid-Open No. 3-1
62798 (Invention title "nonvolatile semiconductor memory device")
There is proposed a technique of a non-volatile memory in which the address of the spare circuit is written in another non-volatile spare circuit, and when the spare circuit is selected, access is performed according to the address written in the other spare circuit.

Further, for example, unpublished Japanese Patent Application No. 3-1976.
88 (invention title "memory device and data processing device using the same") has a built-in memory device that replaces a defective circuit with a spare circuit after self-test during a reset period without cutting with a polysilicon fuse or a laser. Data processor technology has been proposed.

The conventional technique will be described with reference to the drawings. Figure 6
FIG. 3 is an internal configuration diagram of a cache memory when using a conventional technique. The memory mapping method of this cache memory is direct mapping, and the main memory updating method is write through. The block size is 4 words, and when a read miss occurs, 4 words including the data of the requested address are read from the main memory.

The 32-bit external address 1 input from the outside is a tag address 1a, an entry address 1b,
It can be divided into word addresses 1c. The tag address 1a is input to the tag memory 2 and the tag address comparator 3 via the first multiplexer 18. Further, the entry address 1b is input to the entry decoder 4 and the entry address comparator 5 via the second multiplexer 19. Then, the word address 1c is input to the word selector 6.

The tag memory 2 has a size of 20 bits × 256 entries, and the valid bit 7 is assigned to each entry of the tag memory 2 one bit at a time.
Therefore, its size is 1 bit × 256 entries.
Further, the data memory 10 stores 4 words (4.times.32 bits) per entry, and this also has 256 entries. Therefore, its storage capacity is 128 bits ×
There are 256 entries.

The tag address comparator 3 outputs a hit signal 8. The output of the first multiplexer is compared with the tag address obtained from the tag memory 2, and if they match, the hit signal 8 is activated. If they do not match, the hit signal 8 is made inactive.

The disable bit 9 is assigned to each entry in the entry decoder 4 one bit at a time. Therefore, its size is 1 bit × 256 entries.

Based on the result decoded by the entry decoder 4, a specific entry is selected from the tag memory 2 and the data memory 10. The valid bit 7 indicates whether or not the data of the corresponding entry is valid. “1” indicates valid, and “0” indicates invalid. Data memory 10
Of the data stored in the corresponding entry, the word selector 1 selects a specific word by the word address 1c.

One entry is a 20-bit tag memory 2,
It is composed of 1-bit valid bit 7 and 128-bit data memory 10. These memories are collectively called a normal memory as opposed to a redundant memory.

The redundant memory has two entries (two lines) only in the line direction by taking advantage of the characteristics of the cache memory. The one entry (line) is a 20-bit redundant tag memory 11, a 1-bit redundant valid bit 12, 12
It consists of an 8-bit redundant data memory 13, an 8-bit entry register 14, and a 1-bit used bit 15.

Each line of the entry register 14 stores the entry address of the data stored in the redundant tag memory 11 and the redundant data memory 13. The redundant valid bit 12 indicates whether or not the data of the corresponding line of the redundant memory is valid. When the redundant valid bit 12 is “1”, it is valid, and when the data is “0”, it is invalid.

The entry address comparator 5 outputs an entry hit signal 16. The entry address comparator 5 is provided for each line of the redundant memory and compares the output of the second multiplexer with the entry address obtained from the entry register 14, respectively. The comparison result is output as the entry hit signal 16, and the redundant tag memory 1
1, a redundant valid bit 12, and a specific line of the redundant data memory 13 are designated.

The cache memory also includes a self-test circuit 17 for performing a self-test during the reset period.
Equipped with. The self-test circuit 17 inputs the tag address, the entry address, the data, etc. into the regular memory via the first to third multiplexers 18 to 20, and the tag memory 2
The data output from the memory and the data output from the data memory 10 are diagnosed.

The cache memory configured as described above operates as follows.

(A-1) Registration in redundant memory In a system including a cache memory and an MPU, all devices are reset when the power is turned on. When this reset period starts, the valid bit 7, the disable bit 9, the redundant valid bit 12, and the used bit 15 are all reset to "0". Then, during the reset period, the self-test circuit 17 self-tests the cache memory.

When the reset signal 21 becomes active,
The self-test circuit 17 inputs the entry address to the entry decoder 4 via the second multiplexer 19. Then, the memory test is performed by writing / reading data to / from each entry in the tag memory 2 via the first multiplexer 18 and in the data memory 10 via the third multiplexer 20.

That is, when writing to the tag memory 2 and the data memory 10 in the self test, the tag address and the data of 4 words are written to the entry specified by the entry address input to the entry decoder 4. Further, when reading, the tag address is read from the tag memory 2 and the 4-word data from the data memory 10 is read to the self-test circuit 17 with the entry specified by the entry address input to the entry decoder 4.

When a defect is found in the tag memory 2 or the data memory 10 as a result of the self-test, the entry address of the defective entry is written in the entry register 14 and the use bit 15 is set to "1". When a plurality of defects are found, one of the two lines is appropriately selected and the entry address is written. On the other hand, regarding the normal memory, the disable bit 9 of the defective entry is set to "1".

When the self-test ends, the cache memory starts a normal operation (read miss, read hit, etc.).

(A-2) Hit judgment When the external address 1 is input, the cache memory makes a hit judgment regardless of a read request or a write request, that is, whether the data requested from the outside exists in the cache memory. Is determined.

When the external address 1 is input, the entry address 1b is given to the entry decoder 4 via the second multiplexer 19 and is decoded there to select a specific entry.

On the other hand, the entry address comparator 5 compares each entry address of the entry register 14 with the entry address 1b. And used bit 15
Is "1" and the two entry addresses match, the entry hit signal 16 is activated. In other cases, including the case where the content of the entry register 14 is not input because the used bit 15 is "0",
If the two entry addresses do not match, they are made inactive.

When the disable bit 9 of the selected entry is "0", it corresponds to an entry which has not failed in the self test during the reset period. Therefore, the data of the memory 2 is read by the selected entry.

In this case, the tag address comparator 3 compares the tag address read from the tag memory 2 with the tag address 1a input from the outside and arriving via the first multiplexer 18. When the valid bit 7 of the selected entry is "1" and the two tag addresses match, the tag address comparator 3 activates the hit signal 8. In other cases, that is, when the two tag addresses do not match, including the case where the valid bit 7 of the selected entry is "0" and the contents of the tag memory 2 are not input, the hit signal 8 is output. Make it inactive.

When the disable bit 9 of the selected entry is "1", it corresponds to a defective entry that failed in the self-test in the reset period. In this case, one of the entry hit signals 16 is always active. Then, the data of the entry corresponding to the active entry hit signal 16 in the redundant tag memory 11 is read.

In this case, the tag address comparator 3 compares the tag address from the redundant tag memory 11 with the tag address 1a input from the outside via the first multiplexer 18. When the redundant valid bit 12 of the corresponding entry is "1" and the two tag addresses match, the tag address comparator 3 activates the hit signal 8. In other cases, that is, when the content of the redundant tag memory 11 is not input because the redundant valid bit 12 of the corresponding entry is "0",
If the two tag addresses do not match, the hit signal 8 is made inactive.

(A-3) Read hit When there is a read request from the outside and the hit signal 8 is active, that is, when the data requested from the outside exists in the cache memory, it is called a read hit and is called from the outside. Output the requested data from the cache memory.

When the disable bit 9 of a particular entry selected by the entry address 1b given from the outside via the second multiplexer 19 is "0", 4 from the selected entry in the data memory 10 are selected. The word data is read by the word selector 6 via the third multiplexer 20, and one word selected by the word address 1c is output to the outside.

When the disable bit 9 of the selected entry is "1", two entry hit signals 1
One of the six is active. Then, in the redundant data memory 13, data of 4 words from the entry specified by the entry hit signal 16 is transferred to the third multiplexer 2
It is output to the word selector 6 through 0. The word selector 6 outputs the word selected by the word address 1c to the outside.

(A-4) Read miss When there is a read request from the outside and the hit signal 8 is not active, that is, when the data requested from the outside does not exist in the cache memory, it is called a read miss and the cache memory is 4 words of data are newly input from the main memory).

When the disable bit 9 of the specific entry selected by the entry address 1b given from the outside via the second multiplexer 19 is "0",
The newly read 4-word data is stored in the selected entry of the data memory 10 via the third multiplexer 20. On the other hand, the tag address 1a obtained from the outside via the first multiplexer 18 is stored in the selected entry of the tag memory 2, and the valid bit 7 of the selected entry is set to "1".

If the disable bit 9 of the selected entry is "1", the two entry hit signals 16
One of these is active. Then, in the redundant data memory 13, the entry of which the entry hit signal 16 is active stores the newly read 4-word data via the third multiplexer 20. On the other hand, the tag address 1a obtained from the outside via the second multiplexer 18 is stored in the entry of the redundant tag memory 11 where the entry hit signal 16 is active, and the redundant valid bit 12 is set to "1".

(A-5) Write hit When there is a write request from the outside and the hit signal 8 is active, that is, when the requested data exists in the cache memory, it is called a write hit, and the cache memory is external. It is overwritten using the data given by.

When the disable bit 9 of the specific entry selected by the entry address 1b obtained from the outside through the second multiplexer 19 is "0",
The data of 1 word input from the outside is transferred to the data memory 1 via the word selector 6 and the third multiplexer 20.
It is written to the selected entry of 0.

When the disable bit 9 of the selected entry is "1", one of the two entry hit signals 16 is active. Then, one word of data input from the outside via the word selector 6 and the third multiplexer 20 is written into the entry designated by the entry hit signal 16 of the redundant data memory 13.

(A-6) Write Miss When there is a write request from the outside and the hit signal 8 is not active, that is, when the requested data does not exist in the cache memory, it is called a write miss. Since the write-through method is adopted, the cache memory does nothing.

[0041]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention As described above,
The method of performing the self-test during the reset period to replace the faulty circuit with the spare circuit has a problem that the reset period is shorter than the capacity of the cache memory and the self-test cannot be performed on all entries.

Further, in the method of storing the address of the spare circuit in the non-volatile memory and referencing the non-volatile memory every time the spare circuit is accessed, it is easy to sufficiently increase the speed of the internal operation of the cache memory. There was a problem that was not.

Further, in order to repair a plurality of faulty circuits, at least as many spare circuits as the number of faulty circuits are required,
If there are not enough spare circuits, the problem remains that the product cannot be shipped as a good product.

The present invention has been made in view of the above circumstances, and replaces a defective circuit with a spare circuit to improve the manufacturing yield without cutting the circuit by a polysilicon fuse or a laser, thereby reducing the manufacturing cost. An object of the present invention is to provide a cache memory that can be lowered and can be sufficiently replaced.

[0045]

A cache memory according to the present invention stores a tag address which is a part of an address,
A tag memory for storing an entry address, which is another part of the address, and a data memory for storing data corresponding to the entry address;
Of the redundant tag memory corresponding to one entry, the redundant data memory corresponding to the redundant tag memory, and the entry address, which is determined to be defective in the tag memory or the data memory as a result of being previously checked. Defective entry storage means for storing the entry address.

In the first invention, the entry address storage means corresponding to the redundant tag memory for reading the defective entry address from the defective entry storage means at the time of start-up and the external address which is an address given from the outside. Comparing an external entry address corresponding to the entry address with the defective entry address obtained from the entry address storage means,
It further comprises an entry address comparing means corresponding to the redundant tag memory and the redundant data memory, which accesses the redundant tag memory and the redundant data memory when both match.

Further, in the second invention, the tag memory and the data memory of the entry provided corresponding to each of the entry addresses and corresponding to the defective entry address stored in the defective entry storage means are provided. And a bad entry prohibiting means for making the access inaccessible.

Further, in the third invention, the tag memory and the data memory of the entry provided corresponding to each of the entry addresses and corresponding to the defective entry address stored in the defective entry storage means are provided. When the external entry address corresponding to the entry address among the external addresses given from the outside is the defective entry address, the defective entry prohibiting means for disabling access is referred to. A redundant entry memory which is accessed together with the redundant tag memory and is provided corresponding to the redundant tag memory.

[0049]

The redundant tag memory and the redundant data memory serve as spare circuits, and are replaced by defective circuits of the tag memory and the data memory.

In the first aspect of the invention, the defective entry address previously stored in the defective entry storage means is written in the entry address storage means at the time of startup. After that, the redundant tag memory and the redundant data memory are accessed by referring to the comparison result of the entry address comparator.

In the second invention, the defective entry address stored in advance in the defective entry storage means is written in the defective entry prohibiting means. After that, the defective entry prohibiting means is referred to prohibit the access to the tag memory or the data memory when decoding the entry address.

In the third invention, the defective entry address stored in advance in the defective entry storage means is written in the defective entry prohibiting means. After that, the defective entry prohibiting means is referred to prohibit access to the tag memory and the data memory at the time of decoding the entry address, and access the redundant tag memory and the redundant entry memory.

[0053]

【Example】

(B) Example 1. FIG. 1 shows an internal configuration diagram of a cache memory which is an embodiment of the first invention and the second invention. The memory mapping method of this cache memory is direct mapping, and the main memory updating method is write through. Further, the block size is 4 words, and when a read miss occurs, the block size including the data of the requested address is 4
The word is read from main memory.

The 32-bit external address 1 input from the outside is the tag address 1a, the entry address 1b,
It can be divided into word addresses 1c. The tag address 1a is input to the tag memory 2 and the tag address comparator 3. Further, the entry address 1b is input to the entry decoder 4 and the entry address comparator 5. Then, the word address 1c is input to the word selector 6.

The tag memory 2 has a size of 20 bits × 256 entries, and the valid bit 7 is assigned to each entry of the tag memory 2 by 1 bit.
Therefore, its size is 1 bit × 256 entries.
Further, the data memory 10 stores 4 words (4.times.32 bits) per entry, and this also has 256 entries. Therefore, its storage capacity is 128 bits ×
There are 256 entries.

The tag address comparator 3 outputs a hit signal 8. The output of the first multiplexer is compared with the tag address obtained from the tag memory 2, and if they match, the hit signal 8 is activated. If they do not match, the hit signal 8 is made inactive.

The disable bit 9 is assigned to each entry in the entry decoder 4 one bit at a time. Therefore, its size is 1 bit × 256 entries.

A specific entry in the tag memory 2 and the data memory 10 is selected from the result decoded by the entry decoder 4. The valid bit 7 indicates whether the data of the corresponding entry is valid, and if "1", it is valid,
If "0", it indicates invalid.

Of the data stored in the corresponding entry in the data memory 10, the word selector 1 selects a specific word by the word address 1c.

One entry (line) is composed of a tag memory 2 of 20 bits, a valid bit 7 of 1 bit, and a data memory 10 of 128 bits, and these memories are collectively called a normal memory as opposed to a redundant memory.

The redundant memory has two entries (two lines) in the line direction only, taking advantage of the characteristics of the cache memory. One entry (line) is composed of a 20-bit redundant tag memory 11, a 1-bit redundant valid bit 12, a 128-bit redundant data memory 13, an 8-bit entry register 14, and a 1-bit used bit 15.

Each line of the entry register 14 stores the entry address of the data stored in the redundant tag memory 11 and the redundant data memory 13. The redundant valid bit 12 indicates whether or not the data of the corresponding line of the redundant memory is valid. When the redundant valid bit 12 is “1”, it is valid, and when the data is “0”, it is invalid.

The use bit 15 stores "1" when the corresponding line of the redundant memory is used as the redundant memory and "0" when it is not used.

The entry address comparator 5 outputs the entry hit signal 16. The entry address comparator 5 is
It is provided for each line of the entry register 14, and compares the entry address 1b with the entry address obtained from the entry register 14, respectively. The comparison result is
Output as the entry hit signal 16, the redundant tag memory 11, the redundant valid bit 12, the redundant data memory 1
Specify 3 specific lines.

Further, this cache memory is provided with a redundant memory control circuit 22, and an entry (defective entry) for switching from the test result at the time of product shipment to the redundant memory is stored in the programmable ROM 23 in the redundant memory control circuit 22.

The cache memory thus configured does not use a fuse or the like for switching to the redundant memory. Programmable ROM 23 which is a non-volatile memory
The defective entry stored in advance is written in the disable bit 9 inside the entry register 14 and the entry decoder 4 during the reset period. Then, in normal operation, referring to them, the access to the normal memory and the redundant memory is switched. Therefore, this cache memory operates so that it cannot be judged from the outside whether or not the redundant memory is used (similar to a completely non-defective product). Specifically, it operates as follows.

(B-1) Registration in Redundant Memory The defective entry detected in the test before shipping the product is stored in the programmable ROM 23 in advance.

When the reset signal 21 becomes active,
The cache memory sets all of the valid bit 7, the disable bit 9, the redundant valid bit 12, and the used bit 15 to "0". After that, the redundant memory control circuit 2
Under the control of 2, the contents of the programmable ROM 23 are written in the entry register 14, and the use bit 15 and the disable bit 9 of the corresponding entry become "1". When the reset period ends, the cache memory starts normal operation (read miss, read hit, etc.).

(B-2) Hit Determination When the external address 1 is input, the cache memory makes a hit determination regardless of a read request or a write request.

When the external address 1 is input, the entry address 1b is given to the entry decoder 4 where it is decoded and a specific entry is selected.

On the other hand, the entry address comparator 5 compares each entry address of the entry register 14 with the entry address 1b. Used bit 15 is "1"
If the two entry addresses match, the entry hit signal 16 is activated. Otherwise,
That is, when the two entry addresses do not match, including the case where the contents of the entry register 14 are not input because the used bit 15 is "0", the non-active state is made.

When the disable bit 9 of the selected entry is "0", it corresponds to the entry which has not failed in the test before shipping the product. Therefore, the data of the memory 2 is read by the selected entry.

In this case, the tag address comparator 3 compares the tag address read from the tag memory 2 with the tag address 1a input from the outside. When the valid bit 7 of the selected entry is "1" and the two tag addresses match, the tag address comparator 3 activates the hit signal 8. In other cases, that is, in the case where the contents of the tag memory 2 are not input because the valid bit 7 is "0", the hit signal 8 is made inactive when the two tag addresses do not match.

When the disable bit 9 of the selected entry is "1", it corresponds to a defective entry that failed in the test before shipping the product. In this case, one of the entry hit signals 16 is always active. Then, the data of the entry corresponding to the active entry hit signal 16 in the redundant tag memory 11 is read.

In this case, the tag address comparator 3 compares the tag address from the redundant tag memory 11 with the tag address 1a input from the outside. When the redundant valid bit 12 of the corresponding entry is "1" and the two tag addresses match, the tag address comparator 3 activates the hit signal 8. In other cases, that is, in the case where the two tag addresses do not match, including the case where the content of the redundant tag memory 11 is not input because the redundant valid bit 12 of the corresponding entry is “0”, the hit signal 8 is not set. Activate.

(B-3) Read hit When there is a read request from the outside and the hit signal 8 is active, that is, when the data requested from the outside exists in the cache memory, it is called a read hit and is called from the outside. Output the requested data from the cache memory.

Entry address 1b given from the outside
Disable bit 9 for the specific entry selected by
Is “0”, the 4-word data from the selected entry in the data memory 10 is the word selector 6
1 read out to and selected by word address 1c
The word is output to the outside.

When the disable bit 9 of the selected entry is "1", two entry hit signals 1
One of the six is active. Then, 4-word data is output to the word selector 6 from the entry designated by the entry hit signal 16 in the redundant data memory 13. In the word selector 6, the word address 1c
One word selected by is output to the outside.

(B-4) Read miss When there is a read request from the outside and the hit signal 8 is not active, that is, when the data requested from the outside does not exist in the cache memory, it is called a read miss and the cache memory is 4 words of data are newly input from the main memory).

Entry address 1b given from the outside
Disable bit 9 for the specific entry selected by
Is 0, the newly read 4-word data is stored in the selected entry of the data memory 10. On the other hand, the tag address 1a obtained from the outside
Is stored in the selected entry of the tag memory 2,
The valid bit 7 of the selected entry is set to "1".

If the disable bit 9 of the selected entry is "1", two entry hit signals 16
One of these is active. Then, in the redundant data memory 13, the entry of which the entry hit signal 16 is active stores the newly read 4-word data via the word selector 6. On the other hand, the tag address 1a obtained from the outside via the second multiplexer 18 is stored in the entry of the redundant tag memory 11 where the entry hit signal 16 is active, and the redundant valid bit 12 is set to "1".

(B-5) Write hit When there is a write request from the outside and the hit signal 8 is active, that is, when the requested data exists in the cache memory, it is called a write hit, and the cache memory is external. Is overwritten using the data shown in.

When the disable bit 9 of the specific entry selected by the entry address 1b obtained from the outside is “0”, one word of data inputted from the outside is passed through the word selector 6 to the data memory 10. Of the selected entries.

When the disable bit 9 of the selected entry is "1", one of the two entry hit signals 16 is active. Then, one word of data input from the outside via the word selector 6 is written in the entry designated by the entry hit signal 16 of the redundant data memory 13.

(B-6) Write Miss When there is a write request from the outside and the hit signal 8 is not active, that is, when the requested data does not exist in the cache memory, it is called a write miss. Since the write-through method is adopted, the cache memory does nothing.

(B-7) Since the cache memory of the first embodiment operates as described above, the circuit is not cut off by the polysilicon fuse or the laser. Further, since the defective entry is known in advance, it can be easily replaced with the redundant memory. Further, when decoding the entry address, access to the normal memory is prohibited by the disable bit 9, so that extra power is not consumed.

(C) Example 2. FIG. 2 shows an internal configuration diagram of a cache memory which is another embodiment of the first invention and the second invention. The memory mapping method and the main memory updating method of this cache memory are the same as those in the first embodiment. Also, the block size is 4 words as in the first embodiment,
When a read miss occurs, 4 words including the data of the requested address are read from the main memory.

The external address 1 can be divided into a tag address 1a, an entry address 1b and a word address 1c as in the first embodiment. The input destination of these addresses is the same as in the first embodiment. The sizes of the tag memory 2, the valid bit 7, and the data memory 10 are also the same as those in the first embodiment.

Similarly to the first embodiment, the tag address comparator 3 also compares the tag address 1a input from the outside with the tag address from the tag memory 2 and outputs the hit signal 8 as active or non-active. The meaning indicated by the valid bit 7 is also the same as in the first embodiment.

In the entry decoder 4, the decision logic circuit 24 is used instead of the disable bit 9 shown in the first embodiment.
Is provided. The decision logic circuit 24 outputs the O of the two entry hit signals 16 output from the first OR circuit 25.
R entry is judged and specific entry (bad entry)
I can not choose. Specifically, as shown in FIG. 3, a pair of an inverter and an AND circuit is provided corresponding to each entry.

The redundant memory has two lines (for two entries) only in the line direction. The structure of one entry is the same as that of the first embodiment.
Is the same as. Further, similarly to the first embodiment, each line of the entry register 14 stores the entry address of the data stored in the redundant tag memory 11 and the redundant data memory 13. The meanings of the redundant valid bit 12 and the used bit 15 are the same as in the first embodiment.

The entry address comparator 5 outputs the entry hit signal 16 and designates a specific line of the redundant tag memory 11, the redundant valid bit 12, and the redundant data memory 13 as in the first embodiment.

Further, this cache memory has a redundant memory control circuit 22 and a programmable ROM as in the first embodiment.
23 is provided.

The cache memory thus constructed does not use a fuse or the like for switching to the redundant memory. Programmable ROM 23 which is a non-volatile memory
The defective entry stored in advance is written in the entry register 14 during the reset period. Then, in the normal operation, the contents of the entry register 14 are referred to and the access to the normal memory and the redundant memory is switched. For this reason,
This cache memory operates so that it cannot be judged from the outside whether or not the redundant memory is used (similar to a perfect product). Specifically, it operates as follows.

(C-1) Registration in Redundant Memory In a test at the time of product shipment in advance, a defective entry is detected as a programmable ROM in the redundant memory control circuit 22.
It is stored in 23.

When the reset signal 21 becomes active,
In the cache memory, the valid bit 7, the redundant valid bit 12, and the used bit 15 are all set to "0". After that, under the control of the redundant memory control circuit 22, the contents of the programmable ROM 23 are written in the entry register 14, and the used bit 15 becomes "1". When the reset period ends, the cache memory operates normally (read miss,
Lead hit, etc.).

(C-2) Hit Determination When the external address 1 is input, the cache memory makes a hit determination regardless of a read request or a write request.

When the external address 1 is input, the entry address 1b is given to the entry decoder 4 where it is decoded and a specific entry is selected.

On the other hand, the entry address comparator 5 compares each entry address of the entry register 14 with the entry address 1b. And used bit 15
Is "1" and the two entry addresses match, the entry hit signal 16 is activated.
In other cases, that is, in the case where the two entry addresses do not match, including the case where the contents of the entry register 14 are not input because the used bit 15 is "0", they are made non-active.

When the judgment logic circuit 24 of the selected entry is active, that is, when the operation result of the entry hit signal 16 by the first OR circuit 25 is not active (that is, when the entry is not registered in the redundant memory). Corresponds to an entry that has not failed the test during product shipment. Therefore, the data of the memory 2 is read by the selected entry.

In this case, the tag address comparator 3 compares the tag address read from the tag memory 2 with the tag address 1a input from the outside. When the valid bit 7 of the selected entry is "1" and the two tag addresses match, the tag address comparator 3 activates the hit signal 8. In other cases, including the case where the contents of the tag memory 2 are not input because the valid bit 7 of the selected entry is "0", the hit signal 8 is made non-active when the two tag addresses do not match. To

When the decision logic circuit 24 of the selected entry is non-active, that is, when the OR of the entry hit signal 16 calculated by the first OR circuit 25 is not active (that is, the entry is not registered in the redundant memory). In the case), it corresponds to a defective entry that failed in the test before shipping the product. In this case, tag memory 2
No data is read from. Then, one of the two entry hit signals 16 is always active. Therefore, the data of the entry corresponding to the active entry hit signal 16 in the redundant tag memory 11 is read.

In this case, the tag address comparator 3 compares the tag address from the redundant tag memory 11 with the tag address 1a input from the outside. When the redundant valid bit 12 of the corresponding entry is "1" and the two tag addresses match, the tag address comparator 3 activates the hit signal 8. In other cases, that is, in the case where the two tag addresses do not match, including the case where the content of the redundant tag memory 11 is not input because the redundant valid bit 12 of the corresponding entry is "1", the hit signal 8 is not set. Activate.

(C-3) Read hit When there is a read request from the outside and the hit signal 8 is active, that is, when the data requested from the outside exists in the cache memory, it is called a read hit and is called from the outside. Output the requested data from the cache memory.

Entry address 1b given from the outside
When the output of the decision logic circuit 24 of the particular entry selected by
Data of 4 words is read from the selected entry to the word selector 6, and 1 word selected by the word address 1c is output to the outside.

When the output of the decision logic circuit 24 of the selected entry is non-active, one of the two entry hit signals 16 is active. Then, 4-word data is output to the word selector 6 from the entry designated by the entry hit signal 16 in the redundant data memory 13. The word selector 6 outputs one word selected by the word address 1c to the outside.

(C-4) Read Miss When there is a read request from the outside and the hit signal 8 is not active, that is, when the data requested from the outside does not exist in the cache memory, it is called a read miss and the cache memory is read from the outside. Newly input 4-word data.

Entry address 1b given from the outside
When the output of the determination logic circuit 24 of the specific entry selected in step 4 is active, the newly read 4-word data is stored in the selected entry of the data memory 10. On the other hand, the tag address 1 obtained from the outside
a is stored in the selected entry of the tag memory 2, and the valid bit 7 of the selected entry is set to "1".

If the output of the decision logic circuit 24 of the selected entry is non-active, one of the two entry hit signals 16 is active. Then, in the redundant data memory 13, the entry of which the entry hit signal 16 is active stores the newly read 4-word data via the word selector 6. On the other hand, the tag address 1a obtained from the outside is stored in the entry of the redundant tag memory 11 where the entry hit signal is active, and the redundant valid bit 12 is set to "1".

(C-5) Write hit When there is a write request from the outside and the hit signal 8 is active, that is, when the requested data exists in the cache memory, it is called a write hit, and the cache memory is external. Is overwritten using the data shown in.

When the output of the determination logic circuit 24 of the specific entry selected by the entry address 1b obtained from the outside is active, one word data inputted from the outside is passed through the word selector 6 to the data memory 10.
Of the selected entries.

When the output of the decision logic circuit 24 of the selected entry is non-active, one of the two entry hit signals 16 is active. Then, one word of data input from the outside via the word selector 6 is written in the entry designated by the entry hit signal 16 of the redundant data memory 13.

(C-6) Write Miss When there is a write request from the outside and the hit signal 8 is not active, that is, when the requested data does not exist in the cache memory, it is called a write miss. Since the write-through method is adopted, the cache memory does nothing as in the first embodiment.

(C-7) Since the cache memory of the second embodiment operates as described above, the circuit is not cut off by the polysilicon fuse or the laser. Further, since the defective entry is known in advance, it can be easily replaced with the redundant memory. Further, when decoding the entry address, access to the regular memory is prohibited by the decision logic circuit 24, so that extra power is not consumed.

(D) Example 3. FIG. 4 shows an internal configuration diagram of a cache memory which is still another embodiment of the first invention. The memory mapping method and the main memory updating method of this cache memory are the same as those in the first embodiment. The block size is also 4 words as in the first embodiment, and when a read miss occurs, 4 words including the data of the requested address are read from the main memory.

The external address 1 can be divided into a tag address 1a, an entry address 1b and a word address 1c, as in the first embodiment. The input destination of these addresses is the same as that of the first embodiment, but the tag address 1a is also input to the redundant address comparator 28. Also, the sizes of the tag memory 2, the valid bit 7, and the data memory 10 are the same as those in the first embodiment.
Is the same as. The meaning indicated by the valid bit 7 is also the same as in the first embodiment.

Similarly to the first embodiment, the tag address comparator 3 also compares the tag address 1a input from the outside with the tag address from the tag memory 2. However, its output is the tag hit signal 26, unlike the first embodiment. If the tag address 1a and the tag address from the tag memory 2 match, the tag hit signal 26 becomes active, and if they do not match, it becomes inactive.

Unlike the first and second embodiments, the entry decoder 4 also disables the disable bit 9 in the decision logic circuit 2.
Not even equipped with 4. The entry decoder 4 decodes the entry address 1b, and a specific entry in the tag memory 2 and the data memory 10 is selected from the result.

Of the data stored in the entry selected in the data memory 10, the word specified by the word selector 6 by the word address 1c is selected via the fourth multiplexer 27.

The redundant memory has one line (one entry) only in the line direction. The structure of one entry is the same as that of the first embodiment.
Is the same as. Further, similar to the first embodiment, the entry register 14 stores the entry address of the data stored in the redundant tag memory 11 and the redundant data memory 13. The meanings of the redundant valid bit 12 and the used bit 15 are the same as in the first embodiment.

The redundant tag memory 11 is connected to the redundant tag address comparator 28. The redundant tag address comparator 28 compares the external tag address 1a with the tag address in the redundant tag memory 11 and outputs a redundant tag hit signal 29.

The entry address comparator 5 is connected to the entry register 14 and receives an entry address 1 from the outside.
b and the entry address from the entry register 14 are compared. The result of the comparison is output as the entry hit signal 16 and input to the fourth multiplexer 27 and the fifth multiplexer 30.

The fourth multiplexer 27 selects one of the data memory 10 and the redundant data memory 13 according to the entry hit signal 16.

The fifth multiplexer 30 selects one of the tag hit signal 26 and the redundant tag hit signal 29 according to the entry hit signal 16.

Further, this cache memory has a redundant memory control circuit 22 and a programmable ROM as in the first embodiment.
23 is provided.

The cache memory thus constructed does not use a fuse or the like for switching to the redundant memory. Programmable ROM 23 which is a non-volatile memory
The defective entry stored in advance is written in the entry register 14 during the reset period. Then, in the normal operation, the contents of the entry register 14 are referred to and the access to the normal memory and the redundant memory is switched. For this reason,
This cache memory operates so that it cannot be judged from the outside whether or not the redundant memory is used (similar to a perfect product). Specifically, it operates as follows.

(D-1) Registration in Redundant Memory Similar to the first embodiment, the defective entry detected in advance in the test before shipping the product is stored in the programmable ROM 23 in the redundant memory control circuit 22.

When the reset signal 21 becomes active,
In the cache memory, the valid bit 7, the redundant valid bit 12, and the used bit 15 are all set to "0". After that, under the control of the redundant memory control circuit 22, the contents of the programmable ROM 23 are written in the entry register 14, and the used bit 15 becomes "1". When the reset period ends, the cache memory operates normally (read miss,
Lead hit, etc.).

(D-2) Hit Judgment When the external address 1 is input, the cache memory makes a hit judgment regardless of a read request or a write request.

Of the input external address 1, the entry address 1b is decoded by the entry decoder 4 and a specific entry is selected.

In the third embodiment, the data of the selected entry in the tag memory 2 is read regardless of the content of the entry hit signal 16. The tag address comparator 3 activates the tag hit signal 26 when the valid bit 7 of the selected entry is "1" and the two tag addresses match. In other cases, that is, when the two tag addresses do not match, including the case where the valid bit 7 of the selected entry is "0" and the contents of the tag memory 2 are not input, the tag hit signal 26
Deactivate.

On the other hand, the entry address comparator 5 compares the entry address of the entry register 14 with the entry address 1b. If the used bit 15 is "1" and the two entry addresses match, the entry hit signal 16 is activated. In other cases, that is, in the case where the two entry addresses do not match, including the case where the content of the entry register 14 is not input because the used bit 15 is "0", it is made inactive.

At the same time, the tag address from the redundant tag memory 11 and the tag address 1a obtained from the outside are
The redundant tag address comparator 28 compares them. In the redundant tag address comparator 28, the redundant valid bit 12 is "1".
If the two tag addresses match, the redundant tag hit signal 29 is activated. In other cases, that is, in the case where the two tag addresses do not match, including the case where the content of the redundant tag memory 11 is not input because the redundant valid bit 12 is "0", it is made inactive.

The fifth multiplexer 30 outputs the tag hit signal 26 when the entry hit signal 16 is inactive, and outputs the redundant tag hit signal 29 as the hit signal 8 when it is active. If the hit signal 8 is active, it corresponds to “hit”, and if it is non-active, it corresponds to “miss”.

(D-3) Read hit When there is a read request from the outside and the hit signal 8 is active, that is, when the data requested from the outside exists in the cache memory, it is called a read hit and is called from the outside. Output the requested data from the cache memory.

When a read request is issued, 4-word data of a specific entry selected from the externally applied entry address 1b of the data memory 10 is read. Further, 4-word data in the redundant data memory 13 is also read.

When the entry hit signal 16 is active, that entry corresponds to a defective entry, so the fourth multiplexer 27 outputs the data obtained from the redundant data memory 13. On the other hand, the entry hit signal 16
Is inactive, the entry does not correspond to a defective entry, so the fourth multiplexer 27 outputs the data obtained from the data memory 10.

When the entry hit signal 16 is non-active and the tag hit signal 26 is active,
The hit signal 8 is active. Then, the 4-word data from the data memory 10 is transferred to the fourth multiplexer 27.
Selected by and output to the word selector 6. The word selector 6 outputs the data selected by the word address 1c from the outside.

When the entry hit signal 16 is active and the redundant tag hit signal 29 is active, the hit signal 8 is active. Then, the 4-word data from the redundant data memory 13 is selected by the fourth multiplexer 27 and output to the word selector 6. The word selector 6 outputs the data selected by the word address 1c from the outside.

(D-4) Read Miss When there is a read request from the outside and the hit signal 8 is not active, that is, when the data requested from the outside does not exist in the cache memory, it is called a read miss and the cache memory is read from the outside. Newly input 4-word data.

When the entry hit signal 16 is non-active, the fourth multiplexer 27 operates in the data memory 1
Select 0. When the tag hit signal 26 is inactive, the hit signal 8 is also inactive. In this case, newly read 4-word data is stored in the specific entry selected by the entry address 1b in the data memory 10 via the word selector 6 and the fourth multiplexer 27.

In this case, since it does not correspond to a defective entry, the tag address 1a obtained from the outside is used as the tag memory 2
Stored in the selected entry, and the valid bit 7 of the selected entry is set to "1".

When the entry hit signal 16 is active, the fourth multiplexer 27 operates in the redundant data memory 1
Select 3. When the redundant tag hit signal 29 is inactive, the hit signal 8 is also inactive. The 4-word data newly read into the redundant data memory 13 is the word selector 6 and the fourth multiplexer 2.
Stored via 7.

In this case, since this corresponds to a defective entry,
The tag address 1a obtained from the outside is used as the redundant tag memory 1
The redundant valid bit 12 is set to "1".

(D-5) Write hit When there is a write request from the outside and the hit signal 8 is active, that is, when the requested data exists in the cache memory, it is called a write hit, and the cache memory is external. Is overwritten using the data shown in.

When the entry hit signal 16 is non-active, the fourth multiplexer 27 operates in the data memory 1
Select 0. When the tag hit signal 26 is active, the hit signal 8 is also active, and 1-word data input from the outside is selected by the entry address 1b of the data memory 10 via the word selector 6 and the fourth multiplexer 27. Will be written to a specific entry.

When the entry hit signal 16 is active, the fourth multiplexer 27 operates in the redundant data memory 1
Select 3. When the redundant tag hit signal 29 is active, the hit signal 8 is also active, and one word of data input from the outside is written to the redundant data memory 13 via the word selector 6 and the fourth multiplexer 27.

(D-6) Write Miss When there is a write request from the outside and the hit signal 8 is not active, that is, when the requested data does not exist in the cache memory, it is called a write miss. Since the write-through method is adopted, the cache memory does nothing as in the first embodiment.

(D-7) Since the cache memory of the third embodiment operates as described above, the circuit is not cut by the polysilicon fuse or the laser. Further, since the defective entry is known in advance, it can be easily replaced with the redundant memory.

(E) Example 4. FIG. 5 shows an internal configuration diagram of a cache memory which is an embodiment of the third invention. The memory mapping method and the main memory updating method of this cache memory are the same as those in the first embodiment. The block size is also 4 words as in the first embodiment, and when a read miss occurs, 4 words including the data of the requested address are read from the main memory.

The external address 1 can be divided into a tag address 1a, an entry address 1b and a word address 1c, as in the first embodiment. The input destinations of the tag address 1a and the word address 1c are the same as in the third embodiment, but the entry address 1b is input to the redundant address comparator 31, the redundant entry memory 32, and the entry decoder 4. The sizes of the tag memory 2, the valid bit 7, and the data memory 10 are the same as those in the first embodiment. The meaning indicated by the valid bit 7 is also the same as in the first embodiment.

As in the third embodiment, the tag address comparator 3 compares the tag address 1a with the tag address from the tag memory 2 and outputs the tag hit signal 26. If the tag address 1a and the tag address from the tag memory 2 match, the tag hit signal 26 becomes active, and if they do not match, it becomes inactive.

Inside the entry decoder 4, there is one check bit 33 for each entry. Therefore, its size is 1 bit × 256 entries. A specific entry in the tag memory 2 and the data memory 10 is selected from the result decoded by the entry decoder 4.

Unlike the first to third embodiments, the entry register 14, the used bit 15, and the entry address comparator 5 are not provided.

The redundant memory has one line (one entry) only in the line direction. Redundant entry memory 32 (8 bits), redundant tag memory 11 (20 bits), redundant valid bit 12 (1 bit), redundant data memory 13
One entry is composed of (128 bits).

The redundant tag memory 11 and the redundant entry memory 32 store a tag address and an entry address, respectively. The meaning of the redundant valid bit 12 is the same as that of the first embodiment.

The redundant address comparator 31 is connected to the redundant memory, inputs the tag address 1a and the entry address 1b obtained from the outside to one side, and inputs the tag address from the redundant tag memory 11 and the redundant entry memory 32 to the other side. The entry address is input and compared, and the redundant address hit signal 34 is output. If the results of comparing these match, the redundant address hit signal 34 is activated,
If they do not match, they are made inactive and the redundant data memory 13 is accessed.

The tag hit signal 26 and the redundant address hit signal 34 are input to the second OR circuit 35, where they are logically summed to generate the hit signal 8. If the hit signal 8 is active, it indicates a hit (the requested data exists in the cache memory), and if it is non-active, it indicates a miss (the requested data does not exist in the cache memory).

Further, this cache memory includes a redundant memory control circuit 22 and a programmable ROM as in the first embodiment.
23 is provided.

The cache memory thus constructed does not use a fuse or the like for switching to the redundant memory. During the reset period, of the check bits 33 inside the entry decoder 4, "1" is written in the entry corresponding to the defective entry previously stored in the programmable ROM 23 which is a non-volatile memory. Then, in normal operation, the access to the normal memory and the redundant memory is switched by referring to the check bit 33.

The fourth multiplexer 27 selects one of the data memory 10 and the redundant data memory 13 according to the check bit 33.

A defective entry does not always correspond to the same redundant memory, and even if the number of defective addresses exceeds the number of redundant memories, it is possible to overwrite and switch to the redundant memory when a read miss occurs. As a matter of course, the cache memory of the fourth embodiment operates so that it cannot be judged from the outside whether or not the redundant memory is used (similar to a perfectly good product). Specifically, it operates as follows.

(E-1) Registration in Redundant Memory Similar to the first embodiment, a defective entry is stored in the programmable ROM 23 in the redundant memory control circuit 22 in advance in a test before shipping the product.

When the reset signal 21 becomes active,
The cache memory sets the valid bit 7, the check bit 33, and the redundant valid bit 12 to "0".
After that, the redundant memory control circuit 22 executes the programmable RO.
The defective entry is judged from the contents of M23, and the check bit 33 of the entry is set to "1". When the reset period ends, the cache memory starts normal operation (read miss, read hit, etc.).

(E-2) Hit Determination When the external address 1 is input, the cache memory makes a hit determination regardless of a read request or a write request.

When the external address 1 is input, the entry address 1b is given to the entry decoder 4 where it is decoded and a specific entry is selected.

Check bit 33 of selected entry
Is 0, it corresponds to an entry that has not failed in the test before shipping the product. Therefore, the data of the memory 2 is read by the selected entry.

In this case, the tag address comparator 3 compares the tag address read from the tag memory 2 with the tag address 1a input from the outside. When the valid bit 7 of the selected entry is "1" and the two tag addresses match, the tag address comparator 3 activates the tag hit signal 26. In other cases, that is, in the case where the two tag addresses do not match, including the case where the valid bit 7 of the selected entry is "0", the tag hit signal 26 is made non-active.

Check bit 33 of selected entry
Is 0, the contents of the redundant entry memory 32 and the redundant tag memory 11 are not input to the redundant address comparator 31. Therefore, the redundant address hit signal 34 becomes non-active. Therefore, the hit signal 8 output from the second OR circuit 35 is active when the tag hit signal 26 is active, and nonactive when the tag hit signal 26 is nonactive.

Check bit 33 of selected entry
Is "1", it corresponds to a defective entry that failed in the test before shipping the product, and the redundant memory becomes active. Due to the check bit 33, the entry decoder 4 does not activate any entry in the tag memory 2. Therefore, the contents of the tag memory 2 are not input to the tag comparator 3, and the tag hit signal 26 becomes non-active.

When the redundant address hit signal 34 output from the redundant address comparator 31 is active,
The hit signal 8 becomes active. When the redundant address hit signal 34 is not active, the hit signal 8 becomes non-active.

(E-3) Read hit When there is a read request from the outside and the hit signal 8 is active, that is, when the data requested from the outside exists in the cache memory, it is called a read hit and is called from the outside. Output the requested data from the cache memory.

When the check bit 33 of a particular entry selected by the entry address 1b from the outside is "0", the fourth multiplexer 27 determines the data memory 10
Select. Therefore, 4-word data is read from the data memory 10 to the word selector 6 via the fourth multiplexer 27, and one word selected by the word address 1c is output to the outside.

Check bit 33 of selected entry
Is “1”, the fourth multiplexer 27 selects the redundant data memory 13. When the redundant address hit signal 34 is active, 4-word data is output from the entry designated by the redundant address hit signal 34 to the word selector 6 via the fourth multiplexer 27. The word selector 6 outputs one word selected by the word address 1c to the outside.

(E-4) Read Miss When there is a read request from the outside and the hit signal 8 is not active, that is, when the data requested from the outside does not exist in the cache memory, it is called a read miss and the cache memory is 4 words of data are newly input from the main memory).

Entry address 1b given from the outside
When the check bit 33 of the specific entry selected in step 4 is “0”, the fourth multiplexer 27 selects the data memory 10, and the newly read 4-word data is stored in the data memory 10 via the fourth multiplexer 27. It is stored in the selected entry.

In this case, since it does not correspond to a defective entry, the tag address 1a obtained from the outside is used as the tag memory 2
Stored in the selected entry, and the valid bit 7 of the selected entry is set to "1".

Check bit 33 of selected entry
Is "1", it corresponds to a defective entry. When the redundant address hit signal 34 is non-active, the fourth multiplexer 27 selects the redundant data memory 13. The newly read 4-word data is stored in the redundant data memory 13 via the fourth multiplexer 27. Then, the tag address 1a from the outside is stored in the redundant tag memory 11, and the redundant valid bit 12 is set to "1".

Even if data is already written in the redundant memory, if the check bit 33 of the selected entry is "1" and the redundant address hit signal 34 is inactive, a new data is newly added as described above. The 4-word data, tag address 1a, and entry address 1b input from the outside are overwritten in the redundant memory and used as a spare circuit for the corresponding entry.

That is, in the check bit 33, even if there are a plurality of entries which are set to "1" from the contents of the programmable ROM 23 during the reset period, at least one redundant memory is sufficient.

For example, it is assumed that the check bit 33 is “1” in the first and second entries of the 256 entries during the reset period, and the first entry is first read-accessed. At this point, no data is stored in the redundant memory. Therefore, a read miss occurs in the redundant memory, and new data is written in the redundant memory.

Then, when the first entry is read-accessed once again, the redundant tag address 11 and the redundant entry memory 32 coincide with the external tag address 1a and the entry address 1b. Data is output.

After that, when the second entry is read-accessed, the check bit 33 of this entry is "1", so that the redundant address comparator 31 compares it with the external address. However, since the entry addresses are different, a read miss will occur. In this case, the address of the second entry will be overwritten in the redundant memory.

(E-5) Write hit When there is a write request from the outside and the hit signal 8 is active, that is, when the requested data exists in the cache memory, it is called a write hit, and the cache memory is external. Is overwritten using the data shown in.

When the check bit 33 of the specific entry selected by the entry address 1b is "0", the fourth multiplexer 27 selects the data memory 10, and the 1-word data input from the outside is the word selector. 6 and the fourth multiplexer 27 through the data memory 10
Written to the selected entry of.

Check bit 33 of selected entry
Is “1”, the fourth multiplexer 27 selects the redundant data memory 13. If the redundant address hit signal 34 is active, the word selector 6 and the fourth
One word of data input from the outside is written into the redundant data memory 13 via the multiplexer 27.

(E-6) Write Miss When there is a write request from the outside and the hit signal 8 is not active, that is, when the requested data does not exist in the cache memory, it is called a write miss. Since the write-through method is adopted, the cache memory does nothing as in the first embodiment.

(E-7) Since the cache memory of the fourth embodiment operates as described above, the circuit is not cut by the polysilicon fuse or the laser. Further, since the defective entry is known in advance, it can be easily replaced with the redundant memory.

Further, when the address is decoded, access to the regular memory is prohibited by the check bit 33, so that extra power is not consumed.

Furthermore, since the redundant memory is accessed by referring to the check bit 33, the redundant memory can be overwritten and used even if the number of redundant memories is smaller than the number of defective entries.

Since the number of redundant memories is smaller than the number of defective entries, the storage capacity of the cache memory is equivalently reduced. Therefore, although the hit rate of the cache memory is slightly lowered, the number of defective entries is usually very small as compared with the storage capacity, so that there is no practical problem.

[0192]

According to the first aspect of the present invention, the fault circuit and the spare circuit can be rewritten without using a device such as laser trimming. It is also possible to perform a sufficient memory test and replace the faulty circuit and the spare circuit during a short reset period.

According to the second invention, it is possible to replace the defective circuit with the spare circuit without using a device such as laser trimming. Also, perform a sufficient memory test,
The faulty circuit and the spare circuit can be replaced during a short reset period. Further, since the defective entry prohibiting means can prohibit access to the tag memory and the data memory at the time of decoding the entry address, extra power is not used.

According to the third invention, the fault circuit and the spare circuit can be replaced without using a device such as laser trimming. Also, perform a sufficient memory test,
The faulty circuit and the spare circuit can be replaced during a short reset period. Further, since the defective entry prohibiting means can prohibit access to the tag memory and the data memory at the time of decoding the entry address, extra power is not used. Further, since the spare circuit is accessed by referring to the defective entry prohibiting means, even if the number of spare circuits is smaller than the number of faulty circuits, the cache memory performance (hit rate) is slightly lowered, but the spare circuits are overwritten. Can be used.

[Brief description of drawings]

FIG. 1 is an internal configuration diagram showing a cache memory according to a first embodiment of the present invention.

FIG. 2 is an internal configuration diagram showing a cache memory according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a configuration of a decision logic circuit 24.

FIG. 4 is an internal configuration diagram showing a cache memory according to a third embodiment of the present invention.

FIG. 5 is an internal configuration diagram showing a cache memory according to a fourth embodiment of the present invention.

FIG. 6 is an internal configuration diagram showing a conventional cache memory.

[Explanation of symbols]

 1 Address 1a Tag Address 1b Entry Address 2 Tag Memory 5 Entry Address Comparator 9 Disable Bit 10 Data Memory 11 Redundant Tag Memory 13 Redundant Data Memory 14 Entry Register 23 Programmable ROM 24 Judgment Logic Circuit 32 Redundant Entry Memory 33 Check Bit

─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] February 15, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0026

[Correction method] Change

[Correction content]

On the other hand, the entry address comparator 5 compares each entry address of the entry register 14 with the entry address 1b. And used bit 15
Is "1" and the two entry addresses match, the entry hit signal 16 is activated. Otherwise, i.e. including the case using bit 15 Ru der "0", two entries address If no match to the non-active.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0028

[Correction method] Change

[Correction content]

In this case, the tag address comparator 3 compares the tag address read from the tag memory 2 with the tag address 1a input from the outside and arriving via the first multiplexer 18. When the valid bit 7 of the selected entry is "1" and the two tag addresses match, the tag address comparator 3 activates the hit signal 8. Otherwise, i.e. including if valid bit 7 is Ru der "0" of the selected entry, the two tag addresses when they do not match, the hit signal 8 non-active.

[Procedure 3]

[Document name to be amended] Statement

[Name of item to be corrected] 0030

[Correction method] Change

[Correction content]

In this case, the tag address comparator 3 compares the tag address from the redundant tag memory 11 with the tag address 1a input from the outside via the first multiplexer 18. When the redundant valid bit 12 of the corresponding entry is "1" and the two tag addresses match, the tag address comparator 3 activates the hit signal 8. Otherwise, i.e. appropriate including cases redundant valid bit 12 is Ru der "0" of the entry, two tag addresses when they do not match, the hit signal 8 non-active.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0056

[Correction method] Change

[Correction content]

The tag address comparator 3 outputs a hit signal 8. The tag address 1a input from the outside is compared with the tag address obtained from the tag memory 2, and if they match, the hit signal 8 is activated. If they do not match, the hit signal 8 is made inactive.

[Procedure Amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0071

[Correction method] Change

[Correction content]

On the other hand, the entry address comparator 5 compares each entry address of the entry register 14 with the entry address 1b. Used bit 15 is "1"
If the two entry addresses match, the entry hit signal 16 is activated. Otherwise,
That use bit 15 is "0" Ru der case including two entry address is non-active when they do not match.

[Procedure correction 6]

[Document name to be amended] Statement

[Correction target item name] 0073

[Correction method] Change

[Correction content]

In this case, the tag address comparator 3 compares the tag address read from the tag memory 2 with the tag address 1a input from the outside. When the valid bit 7 of the selected entry is "1" and the two tag addresses match, the tag address comparator 3 activates the hit signal 8. In other cases, that is the valid bit 7 is "0", including Der Ru If,
If the two tag addresses do not match, the hit signal 8 is made inactive.

[Procedure Amendment 7]

[Document name to be amended] Statement

[Correction target item name] 0075

[Correction method] Change

[Correction content]

In this case, the tag address comparator 3 compares the tag address from the redundant tag memory 11 with the tag address 1a input from the outside. When the redundant valid bit 12 of the corresponding entry is "1" and the two tag addresses match, the tag address comparator 3 activates the hit signal 8. Otherwise, i.e. corresponding redundant valid bit 12 of the entry including "0" der Ru If, two tag addresses when they do not match, the hit signal 8 non-active.

[Procedure Amendment 8]

[Document name to be amended] Statement

[Correction target item name] 0099

[Correction method] Change

[Correction content]

On the other hand, the entry address comparator 5 compares each entry address of the entry register 14 with the entry address 1b. And used bit 15
Is "1" and the two entry addresses match, the entry hit signal 16 is activated.
Otherwise, i.e. including the use bit 15 is "0" Ru der if, when the two entries addresses do not match, the non-active.

[Procedure Amendment 9]

[Document name to be amended] Statement

[Correction target item name] 0101

[Correction method] Change

[Correction content]

In this case, the tag address comparator 3 compares the tag address read from the tag memory 2 with the tag address 1a input from the outside. When the valid bit 7 of the selected entry is "1" and the two tag addresses match, the tag address comparator 3 activates the hit signal 8. Otherwise, i.e. including if the valid bit 7 is Ru der "0" of the selected entry, if the two tag addresses do not match, the hit signal 8 non-active.

[Procedure Amendment 10]

[Document name to be amended] Statement

[Correction target item name] 0102

[Correction method] Change

[Correction content]

[0102] The decision logic circuit 24 of the selected entry when a non-active, i.e. if the OR is an entry hit signal 16 calculated by the 1OR circuit 25 is active (that is, the entry is registered in the redundant memory If it exists ), it corresponds to the defective entry that failed in the test before shipping the product. In this case, no data is read from the tag memory 2. Then, one of the two entry hit signals 16 is always active. Therefore, the data of the entry corresponding to the active entry hit signal 16 in the redundant tag memory 11 is read.

[Procedure Amendment 11]

[Document name to be amended] Statement

[Correction target item name] 0103

[Correction method] Change

[Correction content]

In this case, the tag address comparator 3 compares the tag address from the redundant tag memory 11 with the tag address 1a input from the outside. When the redundant valid bit 12 of the corresponding entry is "1" and the two tag addresses match, the tag address comparator 3 activates the hit signal 8. In other cases, that is, the redundant valid bit 12 of the corresponding entry is
When the two tag addresses do not match, including the case of "0" , the hit signal 8 is made inactive.

[Procedure Amendment 12]

[Document name to be amended] Statement

[Name of item to be corrected] 0131

[Correction method] Change

[Correction content]

In the third embodiment, the data of the selected entry in the tag memory 2 is read regardless of the content of the entry hit signal 16. The tag address comparator 3 activates the tag hit signal 26 when the valid bit 7 of the selected entry is "1" and the two tag addresses match. Otherwise, i.e. if the selected two tag address valid bit 7 is "0" der Ru If be included in the entry does not match, a tag hit signal 26 to non-active.

[Procedure Amendment 13]

[Document name to be amended] Statement

[Correction target item name] 0132

[Correction method] Change

[Correction content]

On the other hand, the entry address comparator 5 compares the entry address of the entry register 14 with the entry address 1b. If the used bit 15 is "1" and the two entry addresses match, the entry hit signal 16 is activated. Otherwise, i.e. if the use bit 15 is "0" Ru der If even including two entry address does not match, the non-active.

[Procedure Amendment 14]

[Document name to be amended] Statement

[Name of item to be corrected] 0133

[Correction method] Change

[Correction content]

At the same time, the tag address from the redundant tag memory 11 and the tag address 1a obtained from the outside are
The redundant tag address comparator 28 compares them. In the redundant tag address comparator 28, the redundant valid bit 12 is "1".
If the two tag addresses match, the redundant tag hit signal 29 is activated. In other cases, that is redundant valid bit 12 is "0" Der Ru If even including 2
If the two tag addresses do not match, deactivate them.

[Procedure Amendment 15]

[Document name to be amended] Statement

[Correction target item name] 0174

[Correction method] Change

[Correction content]

Check bit 33 of selected entry
Is “1”, the fourth multiplexer 27 selects the redundant data memory 13. When the redundant address hit signal 34 is active, the redundant data memory 1
Data of 3 to 4 words is output to the word selector 6 via the fourth multiplexer 27. Word selector 6
Then, one word selected by the word address 1c is output to the outside.

[Procedure Amendment 16]

[Document name to be amended] Statement

[Correction target item name] 0178

[Correction method] Change

[Correction content]

Check bit 33 of selected entry
Is "1", it corresponds to a defective entry, and the fourth multiplexer 27 selects the redundant data memory 13. The newly read 4-word data is stored in the redundant data memory 13 via the fourth multiplexer 27. Then, the tag address 1a from the outside is stored in the redundant tag memory 11, and the redundant valid bit 12 is set to "1".

[Procedure Amendment 17]

[Document name to be amended] Statement

[Correction target item name] 0179

[Correction method] Change

[Correction content]

Even if data has already been written in the redundant memory, if the check bit 33 of the selected entry is "1 ", 4-word data and tag newly input from the outside as described above are added. The address 1a and the entry address 1b are overwritten in the redundant memory and used as a spare circuit for the corresponding entry.

[Procedure 18]

[Document name to be amended] Statement

[Name of item to be corrected] 0192

[Correction method] Change

[Correction content]

[0192]

According to the first aspect of the present invention, the fault circuit and the spare circuit can be rewritten without using a device such as laser trimming. It is also possible to perform a sufficient memory test and replace the faulty circuit and the spare circuit during a short reset period. Also, at the same time as the address decoding,
Since the contents of the register are compared, the spare circuit was accessed.
Even if you don't waste your time.

[Procedure Amendment 19]

[Document name to be amended] Statement

[Name of item to be corrected] 0193

[Correction method] Change

[Correction content]

According to the second invention, it is possible to replace the defective circuit with the spare circuit without using a device such as laser trimming. Also, perform a sufficient memory test,
The faulty circuit and the spare circuit can be replaced during a short reset period. Further, since the defective entry prohibiting means can prohibit access to the tag memory and the data memory at the time of decoding the entry address, extra power is not used. Also with address decoding
At the same time, the contents of the registers are compared, so the spare circuit
You don't waste your time even if you do.

[Procedure amendment 20]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 1

[Correction method] Change

[Correction content]

[Figure 1]

[Procedure correction 21]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 2

[Correction method] Change

[Correction content]

[Fig. 2]

[Procedure correction 22]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 5

[Correction method] Change

[Correction content]

[Figure 5]

Claims (3)

[Claims] 1. A tag address, which is a part of an address,
A tag memory for storing an entry address which is another part of the address, a data memory for storing data corresponding to the entry address, a redundant tag memory corresponding to at least one entry, and the redundant tag A redundant data memory corresponding to the memory; a defective entry storage unit that stores a defective entry address that is determined to be defective in the tag memory or the data memory as a result of a pre-inspection among the entry addresses; An entry address storage unit corresponding to the redundant tag memory for reading the defective entry address from the defective entry storage unit; an external entry address corresponding to the entry address among external addresses given from the outside; Entry address memorizer And a defective entry address obtained from the above, and if the two match, the redundant tag memory and the redundant data memory are accessed, and the redundant tag memory and an entry address comparison means corresponding to the redundant data memory are provided. memory. 2. A tag address, which is a part of the address,
A tag memory for storing an entry address which is another part of the address, a data memory for storing data corresponding to the entry address, a redundant tag memory corresponding to at least one entry, and the redundant tag A redundant data memory corresponding to the memory; a defective entry storage unit that stores a defective entry address that is determined to be defective in the tag memory or the data memory as a result of a pre-inspection among the entry addresses; A cache memory provided corresponding to each of the addresses, and a defective entry prohibiting unit that makes the tag memory and the data memory of the entry corresponding to the defective entry address stored in the defective entry storage unit inaccessible. . 3. A tag address, which is a part of the address,
A tag memory for storing an entry address which is another part of the address, a data memory for storing data corresponding to the entry address, a redundant tag memory corresponding to at least one entry, and the redundant tag A redundant data memory corresponding to the memory; a defective entry storage unit that stores a defective entry address that is determined to be defective in the tag memory or the data memory as a result of a pre-inspection among the entry addresses; Bad entry prohibiting means provided corresponding to each of the addresses and making the tag memory and the data memory of the entry corresponding to the bad entry address stored in the bad entry storing means inaccessible; Of the external addresses that are When the external entry address corresponding to the entry address is the defective entry address, it is accessed together with the redundant tag memory by referring to the defective entry prohibiting means, and the redundant entry memory provided corresponding to the redundant tag memory is provided. And a cache memory including.