JPS6029841A - Arithmetic controller - Google Patents

Abstract

PURPOSE:To send out a correct control signal when the same control word is reexecuted by storing the correct control signal in a history storage area when there is an error in the design of the decoder of a microprogram control processor. CONSTITUTION:If an error in the design of the highly integrated decoder (DEC) 4 is found in the stage of a test of a decoder processor, a specific field of a relative control word is used as an address of the history storage part (HS) 6 to access the history storage part. Then, the correct control signal stored previously in the address is read out to a data register (HISDR) 8 and a control signal switching part 5 is controlled to send out the correct control signal to an arithmetic part, thereby carrying on the test without reference to the error in the design of the DEC4.

Description

DETAILED DESCRIPTION OF THE INVENTION +81 Technical Field of the Invention The present invention relates to a method of using a history storage section of a microprogram-controlled data processing device as a control storage section.

(bl Background of technology) With the recent trend toward higher integration of logic circuits, each functional part of a data processing device is becoming more highly integrated.In a microprogram-controlled data processing device, for example, reading from its control storage If the decoder that decodes the output of the data register is highly integrated and a design error is discovered during the test stage, the test cannot proceed unless the highly integrated circuit is rebuilt.

On the other hand, since the history storage section of the data processing device can operate in machine cycles, we focused on the fact that the history storage section can be replaced with a control storage section, and developed an effective control storage section. It is now possible to consider the use of proxy means.

(C) Prior art and problems When testing a microprogram-controlled data processing device, a design error is discovered in the decoder that decodes the output of the read data register of the control storage section. In the case of an integrated data processing device, there is a problem in that the current technology does not allow testing of the data processing device because there is no means to extract correct control signals on behalf of the decoder in real time.

+d) Purpose of the Invention In view of the above-mentioned conventional drawbacks, the present invention focuses on the function of the history storage unit (that is, it can operate in machine cycles) possessed by a microprogram-controlled data processing device.
If a design error is discovered in the decoder that decodes the output of the read data register of the control storage section, when the control word is read out again, the correct arithmetic section control signal is transferred from the read data register of the history storage section. The purpose of this is to provide a method for extracting the information.

According to the present invention, a control storage section storing a microprogram, an address register for accessing the control storage section, and a readout register for holding data read from the control storage section are provided. a register, a history storage section for recording history information, a history address register for accessing the history storage section, a read data register for holding data read from the history storage section, and data written to the history storage section. In an arithmetic control device equipped with a write data register that holds a memory, an address switching circuit for the history storage section, a write data switching circuit, and a control signal switching circuit for the arithmetic section are provided. A first means for setting a field for setting an address for accessing the history storage section in a word, and setting a specific value in the field from an external device, and specifying specific data in the history storage section indicated by the set value. and third means for detecting that the control word has been accessed, and when the third means detects that the control word has been accessed, the switching circuit This is achieved by providing a method for controlling the data in the history storage section set by the first and second means and using it as a control signal for the arithmetic section, and the control word is read out separately. At that point, the correct decoder output can be retrieved from the read data register of the history storage section. Therefore, when the decoder that decodes the output of the read data register of the control storage section malfunctions during the testing stage of the data processing device, it is possible to retrieve the correct decoder output from the read data register of the history storage section. Also, there is an advantage that the data processing device can be tested using the correct control signal.

(fl Embodiment of the invention is a block diagram showing an embodiment of the invention,
1 is a control storage unit (C5), 2 is a control storage address register (C5AR), 3 is a control storage data register (C5DR), 4 is a decoder (DEC), 5
is a control signal switching circuit that selects either the control signal from the decoder (DEC) 4 or the control signal from the history storage read data register (IIIsDR) 8 and sends it to the arithmetic unit (not shown). controlled as follows. 6 is a history storage section (IIs).

7 is the history storage unit address register (IIIsAR
), 8 is hiss, tree storage read data register (
llIsD, R'), 9 is a history storage write data register (IIIsWR), 10 is a history address switching circuit, which selects the history address from the counter 13 or the control storage data register (C5D).
R) It is controlled to select any of the data from 3 and store it in the history record ↑, part 9 address register (IIISAR) 7. Reference numeral 11 denotes a history write data switching circuit which selects either history information or control data (correction control signal) related to the present invention, and selects either history information or control data (correction control signal) related to the present invention, and selects the history storage write data register (IIIS).
WR) is controlled to be stored in 9.

12 is a multiplexer (IPχ), and 13 is a counter.

14 is an overall control section.

First, operations related to control storage will be explained.

The operation part of the instruction is the control storage address register (CSAR)
2, and according to this address the control memory (C
S) Execution of the instruction when 1 is accessed.

The control words required for the data are sequentially read out and placed in the control storage data register (C3DR) 3. Decoder (DE
C) In 4, some specific fields of the control storage data register (C5DR) 3 are decoded to send out N calculation unit control signals, which are sent to the calculation unit through the control signal switching circuit 5 and the relevant calculation is executed. . In order to read out all the control words necessary to execute one instruction, a part of the control memory data register (C5Dt?) 3 (the next control memory address indicated by D) is read out from the control memory address register (C5AR).
) is set to 2.

Regarding the history storage section (IIs) 6, normally the history address from the counter 13 is set in the history storage section address register (IIIsAI?) 7 through the history address switching circuit 10.
The history information at that time is set in the history part 1.9 part write data register (IIISWR) 9 through the history write data switching circuit 11,
History 1.1 part (IIs) 6 is accessed and history storage address register (IIIs 8R)
The data indicated by the history storage write data register (IIIsWI! > 9) is stored at the address indicated by ) 6. 1. α is applied.

In addition, multiplexer = (MPX) 12 is history storage section read data register (IIISDR') 8
This circuit serially sends history information read out to a service processor (not shown).

In the present invention, when a design error is discovered in a highly integrated decoder (DEC) 4 during the testing stage of a data processing device, a specific field of a related control word is set as an address of a history storage section (IIs) 6. The history storage section (IIs) 6 is accessed, the correct control signal stored in advance at the address is read out to the history storage section read data register (IIIsDR) 8, the control signal switching circuit 5 is controlled, and the correct control signal is By sending the above to the arithmetic unit, the decoder (DEC) 4
The aim is to allow testing to continue regardless of design errors.

For this reason, in this embodiment, the control word is assigned a specific field (for example, an 8-bit node not related to the decoder (DEC) 4) by using a specific field (for example, the storage capacity M256 words of the history storage section (Its) 6). When a certain instruction is executed, the control words necessary for the execution of that instruction are read out, and the certain control words are stored in the control storage data register (C3DR).
3, if a design error is found in the decoder (D[IC) 4, the service processor will set the value in the specific field of the control word related to the error, and The value is stored in the history section (
Its) 6 address is History IQ Department (
Is) 6 and write the correct control signal as data in the relevant area. The address value set in the above-mentioned specific field may be any value as long as it is 8-bit data, but it is necessary to set the value to be mutually independent against multiple failures of the decoder (DEC) 4.

By placing this, the control memory address of the control word that executes the instruction and causes an error in the decoder (DEC) 4 is stored in the control memory address register (C3AR).
2, when the address is detected in the control circuit 14, the history address switching circuit 10
Control storage data register (C3DR) 3
- Set the above specified field in the storage address register (I (ISAR) 7), access the history storage section (Its) 6, and write the data that is the correct control signal stored at the address into the history. The data is read to the storage read data register (IIIsDR) 8, and the control signal switching circuit 5 is controlled.
The output signal of the decoder (DEC) 4 is suppressed and the history storage read data register (IIIsDR) 8
It is controlled to send the data read out to the arithmetic unit, and a correct arithmetic unit control signal can be sent to the arithmetic unit.

In addition, considering another usage example to which the gist of the present invention is applied, it is also possible to simulate the operation at the time of abnormality by intentionally changing the control signal to the arithmetic unit of an arbitrary control word.

(gl Effects of the Invention As explained in detail above, according to the present invention, when testing a microprogram-controlled data processing device,
If a design error is discovered in the decoder that executes a control word and decodes each field of the control word, the service processor immediately writes the address of the history storage unit into the specific field provided in the control word. By setting the correct control signal and accumulating the correct control signal in the memory area, when the same control word is executed again, the control is controlled so that the correct control signal is sent to the arithmetic unit, so the above decoder is highly integrated. This has the effect of allowing the test to continue even if it cannot be corrected immediately.

[Brief explanation of the drawing]

The figure is a diagram showing one embodiment of the present invention in a professional drawing. In the drawing, 1 is the control storage unit (C5), 2 is the control storage address register (C3AR), and +3 is ff1.
lJ Memory Cheetare'; Suku (C5DR), 4
Hachi: j-da (DEC). 5 is a control signal switching circuit, 6 is a history storage unit (I
IS), 7 is the history storage address register (
HISAR), 8 is a history storage read data register (IIIsDR), 9 is a history storage write data register (IIISWR), 10 is a history address switching circuit, 11 is a history write data switching circuit, 12 is a multiplexer (
MPX), 13 is a counter, and 14 is a control circuit, respectively.

Claims (1)

[Claims] a control storage section that stores a microprogram, an address register that accesses the control storage section, a read register that holds read data from the control storage section, and a history storage section that records history information; An arithmetic control device comprising a history address register for accessing the history storage section, a read data register for holding data read from the history storage section, and a write data register for holding data written to the history storage section, An address switching circuit for the history storage section, a write data switching circuit, and a control signal switching circuit for the calculation section are provided, and an address for accessing the history storage section is set in the control word. a first means for providing a field and setting a specific value in the field from an external device; a second means for setting specific data in a history storage section indicated by the set value; and a third means for detecting that the control word is accessed, and when the third means detects that the control word is accessed, the switching circuit is controlled to switch the switching circuit to the first. An arithmetic control device characterized in that the data set in the history storage section by the second means is retrieved and used as a control signal for the arithmetic section.