JPH02168314A - Memory control system in semiconductor disk device - Google Patents

Abstract

PURPOSE:To effectively use a semiconductor memory without wasting it by using the memory as jumping the address of the erroneous place without switching it to an alternate track when the error occurs in a memory part. CONSTITUTION:In the case where some address of the semiconductor memory part 3 is abnormal and can not be used, a service processor SVP 2 stores an error address in an error address storing part 6. Next, the address for read or write in order to access the semiconductor memory part 3 is transmitted from a director part DIR 1. The transmitted address is sent to an address comparing part 7 through an address buffer 4. By comparing this address and the address of the storing part 6, it is checked whether it is the error address or not. In the case of the error, an adding instruction is executed for the address, and the read/write is executed by accessing the semiconductor memory part 3 by said address.

Description

[Detailed Description of the Invention] [Requires 1N] Regarding a memory control method in a semiconductor disk device, when an error occurs on the semiconductor memory section, by skipping only the address of the part where the error occurred without using a replacement track. The purpose is to provide a memory control method that can effectively use a semiconductor memory section, and includes a semiconductor memory section, a director section that transfers data, and a service processor that performs diagnosis and maintenance. In a memory control method in a semiconductor disk device that controls the semiconductor memory section, an error address storage product that stores an error address when an error occurs in the semiconductor memory section as a result of diagnosis from the service processor, and the director section. an address comparison section for determining whether an error location exists when the semiconductor memory section is accessed from the semiconductor memory section; and an address addition section for skipping the partial address when an error address is selected; When an error occurs in the memory section, the address where the error occurred is skipped and used instead of using a replacement track.

[Industrial Application Field] The present invention relates to a memory control method in a semiconductor disk device.

In the semiconductor disk iJt, if an error occurs in a part of the data section on the semiconductor memory section, even if there are normal sections before and after the error, that area will not be used at all and a replacement track will be used. was.

For this reason, the usage efficiency of the semiconductor memory section was extremely poor. Therefore, there has been a demand for the development of a memory control method that improves the usage efficiency of the semiconductor memory section.

[Prior art] Memory in conventional semiconductor disk devices! 1IJ11
One method is shown in FIGS. 6 and 7.

In FIG. 6, 1 is a director (
DIR> section, 2 is a service processor (SVP) that performs diagnosis and maintenance, 3 is a semiconductor memory section, and 4 is an address buffer? , 5 is a data bus, 9 is an address bus, 1
0 is the data bus.

In this semiconductor disk device, for example, when writing data to the semiconductor memory section 3, the data is transferred from the DIR section 1 to the semiconductor memory section 3 at a specified address using a track emulation foot mat as shown in FIG. is written.

The track emulation format consists of a directory part at the beginning, a home address (HA) indicating the physical location of the track, the track status, etc., a count (C) part, and a data (D> part). .

Here, if an error occurs in the data section of the semiconductor memory section 3, the microprogram of the DIR section 1 causes the data to be written to a replacement track.

[Problems to be Solved by the Invention] However, in the memory control method of such a conventional semiconductor disk device, when an error occurs in a part of the data section on the semiconductor memory section 3, even before and after the error occurs, Even if there is a normal area, the area is not used at all and a replacement track is used, so there is a problem that the usage efficiency of the semiconductor memory section 3 is very poor.

The present invention has been made in view of such conventional problems, and is capable of skipping only the address of the part where the error occurred without using a replacement track when an error occurs on the semiconductor memory section. Accordingly, it is an object of the present invention to provide a memory control method that can effectively use a semiconductor memory section.

[Means to solve the WR problem] FIG. 1 is a diagram explaining the principle of the present invention.

In FIG. 1, 3 is a semiconductor memory section, 1 is a director section that transfers data, 2 is a service processor that performs diagnosis and maintenance, etc., and 6 is a diagnosis from the service processor 2 that indicates that an error has occurred in the semiconductor memory section 3. 7 is an address comparison unit for determining whether or not an error location exists when the semiconductor memory unit 3 is accessed from the director unit 1; 8 is an address comparison unit for storing an error address when This is an address adder for skipping the partial address when an error address is selected.

[Operation] In the present invention, when an error occurs in the semiconductor memory section, the error address is stored in the error address storage section, and the error address is compared with the address when the semiconductor memory section is accessed. The address addition section skips the address where the error occurred and uses the next address if there is a match, so there is no need to use a replacement track, which improves the efficiency of semiconductor memory usage. can be increased.

[Example] Embodiments of the present invention will be described below based on the drawings.

2 to 5 are views showing one embodiment of the present invention.

First, the apparatus for carrying out the present invention will be explained.
In the figure, 1 is a director section (hereinafter referred to as DIR section), and DIR section 1 is connected to address bus 9 and data path code 0.
Data is transferred via. 2 is a service processor (hereinafter referred to as 5VP), and 5VP2 is an address bus 9.
Diagnosis, maintenance, etc. are performed via the data pathco0.

Reference numeral 3 denotes a semiconductor memory section connected to the DIR section 1 and the 5VP2 through an address bus 9, an address buffer 4, a data bus 10, and a data buffer 5, respectively. Data is being written or read, and instructions for diagnosis, maintenance, etc. are received from the 5VP2.

Reference numeral 6 denotes an error address storage section, and the error address storage section 6 stores an error address when an error occurs in the semiconductor memory section 3 when the 5VP2 diagnoses the semiconductor memory section 3 under the instruction of the 5VP2.

Reference numeral 7 denotes an address comparison unit, which compares the error address from the error address storage unit 6 with the address when the semiconductor memory unit 3 is accessed from the DIR unit 1, and determines whether the address is an error location or not. .

8 is an address addition section, and when an error address is selected by the address comparison section 7, the address addition section 8
This is to add 1 to that address and skip 7 addresses in that part.

Next, the operation will be explained.

FIGS. 3(A-3C) are flowcharts for explaining the present invention in detail.

In FIG. 3 (A-C), in step S1, 5VP2 performs an initial diagnosis on the semiconductor memory section 3 to check whether the semiconductor memory section 3 operates normally after turning on the power and before operating the system. Read and write test data. Next, in step S2, if there is no abnormality in the semiconductor memory section 3, no error address is stored in the error address storage section 6, and step S4
Proceed to.

On the other hand, if a certain address in the semiconductor memory section 3 is abnormal and cannot be used in step S2, then in step S3
It is assumed that the VP2 stores an error address in the error address storage section 6.

Next, the DIR section 1 transmits an address for reading or writing in order to access the semiconductor memory section 3. Is the address sent in step S5 an address buffer? 4 to the address comparator 7.

Next, in step S6, in order to check whether the address sent to the address comparison section 7 is an error location, the same address is compared with the address stored in the error address storage section 6.

At this time, if nothing is stored in the error address storage section 6, it is assumed that there is no match.

On the other hand, if the results do not match in step S7, the address comparator 7 does not send an addition instruction to the address adder 8 in step S8.

Conversely, if they match, the address comparator 7 sends an instruction to add +1 to the address adder 8 in step S9.

Then, in step S10, the address adder 8 executes the above addition instruction to the address transmitted from the address buffer 4, and in step S11, the address adder 8 accesses the semiconductor memory unit 3 with the address obtained as a result, Then, reading and writing to the semiconductor memory section 3 is executed at that address.

Further, in step S13, the 018 part 1 and the semiconductor memory part 3 are
If the reading and writing of the data portion between the data section and the data section has not been completed, the above operation is repeated.

At this time, as shown in FIG. 4, when reading and writing the same data section as the data section in which the error has occurred is successively executed, the addition instruction sent by the address comparator 7 is always held.

That is, the +1 addition instruction is always sent from the point where the error occurs until the data section ends.

When the reading and writing of the data section containing the error is completed in step S14, the addition instruction sent by the address comparing section 7 to the address adding section 8 is canceled in step S15. At the earliest opportunity, if there is a next count section or data section with a gap in step 516 and step S17, the above operation is repeated again.

Next, a specific example according to the embodiment will be explained based on FIG.

Here, it is assumed that an error occurs at address 920005 in the semiconductor memory section 3. 018 unit 1 attempts to access the semiconductor memory unit 3 that includes the error address, but first, there is no error location from address 0001 to address 0004, and the address does not match the address stored in the error address storage unit 6, so address comparison is performed. The unit 7 does not issue an addition instruction and directly accesses the semiconductor memory unit 3 using the address from the 018 unit 1.

Next, when the 018 unit 1 transmits the address 920005, the address comparison unit 7 transmits a +1 addition instruction because it matches the address stored in the error address storage unit 6, and accesses the semiconductor memory unit 3 as the address 0006. do.

When the 018 section 1 transmits the data from address 0006 to address 0OOF where the data section ends, it is the same data section as before, so the tens addition instruction sent from the address comparison section 7 remains unchanged. Therefore, in the semiconductor memory section 3, addresses 0007 to 0010 are accessed.

Furthermore, when the 018 part 1 transmits the next count part or the first address of the data part after the address 0021 across the gap, the addition instruction from the address comparison part 7 is canceled and the address transmitted from the 018 part 1 is The semiconductor memory section 3 will be accessed as is.

[Effects of the Invention] As explained above, according to the present invention, even if an error occurs in the semiconductor memory section, the address where the error occurred is checked without skipping to a replacement track under the control of the microprogram. Since the address of the error location is skipped and used under the control of the address comparison section, the semiconductor memory can be used effectively without wasting it.

[Brief explanation of the drawing]

Fig. 1 is a diagram explaining the principle of the present invention, Fig. 2 is a block diagram showing an embodiment of the present invention, and Fig. 3 (
A-C) are flowcharts for explaining the operation, Fig. 4 is a diagram showing an error occurrence state in the emulation format, Fig. 5 is an explanatory diagram of a specific example according to the embodiment, and Fig. 6 is a diagram of a conventional example. FIG. 7 is a block diagram showing an example of an emulation format of a semiconductor disk device. In the figure, 1° Director (DIR> section, 2: Service processor (SVP), 3° Semiconductor memory section, 4° Address buffer, 5, Data buffer, 6: Error address storage section, 7° Address comparison section, 8 , address adder, 9 near address bus, 10 data bus.

Claims (1)

[Claims] A semiconductor disk device that controls the semiconductor memory section (3) and has a semiconductor memory section (3), a director (1) section that performs data transfer, and a service processor (2) that performs diagnosis, maintenance, etc. In the memory control method, an error address storage section (6) for storing an error address when an error occurs in the semiconductor memory section (3) as a result of diagnosis from the service processor (2), and the director section (1) ) to the semiconductor memory section (3
) is provided with an address comparison unit (7) for determining whether or not it is an error location when accessed, and an address addition unit (8) for skipping the partial address when an error address is selected. The semiconductor memory section (3
), a memory control method for a semiconductor disk device is characterized in that when an error occurs in a semiconductor disk device, the address where the error occurs is skipped and used without using a replacement track.