JPH02236755A - Memory control system in semiconductor disk device - Google Patents

Abstract

PURPOSE:To use a semiconductor memory part with high efficiency by making access to the semiconductor memory part by the output of an address addition part, and making access by jumping a continuous error address when the error of a continuous address occurs in the semiconductor memory part. CONSTITUTION:An error address control part 11 controls an addition instruction based on the continuous number of addresses in an error address storage part 6. Also, the address addition part 8 executes the addition instruction from the error address control part 11 on an access address when the error address is selected. An error address comparison part 7 checks whether or not a sent address coincides with the error address stored in the error address storage part 6. When coincidence is obtained between them, it is informed to the error address control part 11, and the error address control part 11 issues the addition instruction to the address addition part 8 with the number corresponding to a continuous number recorded on the error address control part 11. Thereby, it is possible to improve the utilization ratio of the semiconductor memory part even when the error occurs in the continuous address in the semiconductor memory part.

Description

[Detailed Description of the Invention] [Summary] Regarding memory control in a semiconductor disk device, the purpose of the present invention is to provide a semiconductor memory for use by skipping only those error addresses even if an error occurs in consecutive addresses in the semiconductor memory section. In a semiconductor disk device including a director unit that performs data transfer, and a service processor that performs diagnosis, maintenance, etc., an error address is determined when an error occurs in the semiconductor memory unit as a result of diagnosis from the service processor. an error address storage section for storing the error address; an error address comparison section for comparing the access address with the address stored in the error address storage section when the semiconductor memory section is accessed from the director section; an error address control unit that checks whether consecutive addresses exist and controls an address addition instruction based on the number of consecutive addresses; and an address addition unit that executes an addition instruction from the error address control unit to the access address when an error address is selected. accessing the semiconductor memory section by the output of the address adding section, and when an error occurs in consecutive addresses in the semiconductor memory section, only the consecutive error addresses are skipped and accessed. Configure. [Industrial Application Field] The present invention relates to a memory control method in a semiconductor disk device. A semiconductor disk device is a device that is composed of semiconductor memory elements and can be accessed from a channel using the same commands as those of a magnetic disk device by emulating a control device. In such semiconductor disk devices, there is a need for a memory control method that allows the semiconductor memory section to be used efficiently even if an error occurs in the memory at a certain address on the semiconductor memory section. Ta.

[Conventional technology]

Conventional memory control methods for semiconductor disk devices include those shown in FIGS. 6 and 7. In FIG. 6, l represents address bus 9 and data bus 1.
This is a director unit (DIR) that transfers data via 0. 2 is a service processor (hereinafter abbreviated as SVP) that performs diagnosis, maintenance, etc. via an address bus 9 and a data bus 10. 3 is a semiconductor memory section, in which data is written via an address bus 9, an address buffer 4, a data path 10, and a data buffer 5 according to instructions from a director section 1;
Or, while data is being read, instructions for maintenance, diagnosis, etc. are being received from SVP2. Reference numeral 6 denotes an error address storage section that stores an error address when an error occurs in the semiconductor memory section 3 as a result of diagnosis from the service processor 2. 7 is the director section l
This is an error address comparison unit for determining whether or not there is an error location when the semiconductor memory unit 3 is accessed from. 8 is an address adder for skipping the partial address when an error address is selected. 9 is an address bus, and 10 is a data path. In this semiconductor disk device, when writing data to the semiconductor memory section 3, for example, a "track emulation layer" is written to the address of the semiconductor memory section 3 corresponding to the address specified from the director section l. format"
The data is written in. The track emulation format has a directory section at the beginning, which is a table of contents that records the start address of each file stored in this semiconductor memory section 3.
After that, the home address (HA), count section (C
), followed by information consisting of a data part (D). The configuration consisting of the home address (HA), count section (C), and data section (D) is the same as the data structure on one track of the variable length record format in a magnetic disk device, and is an emulation of it. ．． The home address (HA) records the track number and track status of each track, and the count section (C) is the length of the next data section (D), and the data section (D) is the length of one record. It is data. There are gaps GO, Gl, G2, and G3 between each part, and no data is stored here. FIG. 8 is a flowchart showing memory control according to a conventional example. (1) After turning on the power and before operating the system, the service processor (SVP) 2 performs read/write operations on the semiconductor memory section 3 as an initial diagnosis to check whether it is operating normally. (2) If there is no abnormality in the semiconductor memory section 3, step (4)
), and if there is an abnormality, proceed to step (3).
(3) The SVP 2 writes the error address in byte units to the error address storage section 6. (4) An address (byte unit) for reading/writing the semiconductor memory section 3 is transmitted from the director section 1. (5) The transmitted byte address is transmitted to the error address comparator 7 through the address buffer 4. (6) The error address comparison unit 7 compares the received byte address with the byte address stored in the error address storage unit 6 to check whether they match. (7) If there is one loss, proceed to step (8); if there is no match, proceed to step (9). (8) The error address comparator 7 instructs the address adder 8 to add +1. This addition instruction is step (b)
It is retained until it is canceled with . (9) Address addition section 8
performs the indicated addition to the byte address from address buffer 4. The semiconductor memory unit 3 is accessed using the byte address processed by the 0ω address addition unit 8.

01) Execute read/write in semiconductor memory section 3.
02) Check whether the read/write operation between the director section 1 and the semiconductor memory section 3 has been completed. If the process is completed, proceed to step Q, and if not completed, return to step (4). The addition instruction of the round address addition unit 8 is canceled.

In the θ director unit 1, the next count unit (C),
Check whether there is data transfer to the data section (D) (see Figure 7), and if there is still data transfer, return to step (4).
If not, this process ends. [Problems to be Solved by the Invention] In the memory control according to the conventional technology shown in FIG. , writing to the error address will occur, and the semiconductor memory section will have to be replaced. The problem to be solved by the present invention is to provide a memory control method that solves these conventional problems. [Means for Solving the Problems] FIG. 1 is a block diagram showing the configuration of the present invention. In the figure, 1 is a director unit that executes data transfer. 2 is s■P that performs diagnosis, maintenance, etc. Reference numeral 3 denotes a semiconductor memory section which is constituted by a semiconductor memory element and stores information.

Reference numeral 6 denotes an error address storage section, which stores an error address when an error occurs in the semiconductor memory section 3 according to diagnosis. Reference numeral 7 denotes an error address comparison section, which compares the access address when the semiconductor memory section 3 is accessed from the director section 1 with the address stored in the error address storage section 6. Reference numeral 11 denotes an error address control unit, which checks whether consecutive addresses exist in the error address storage unit 6 and controls addition instructions based on the number of consecutive addresses. Reference numeral 8 denotes an address addition unit, which executes an addition instruction from the error address control unit 11 to the access address when an error address is selected. This address addition section 8
The semiconductor memory section 3 is accessed by the output of . [Function] The present invention includes an error address control section 11,
Accordingly, first, the error addresses stored in the error address storage section 6 as a result of the initial diagnosis by the SVP 2 are checked, whether or not there are consecutive addresses is checked, and the error addresses and the number of consecutive addresses are recorded. When an address for accessing and reading/writing the semiconductor memory section 3 is sent from the director section 1,
The error address comparison section 7 checks whether the sent address and the error address stored in the error address storage section 6 match. If they match, the error address control unit l1 is notified, and the error address control unit l1 instructs the address addition unit 8 to add a number corresponding to the recorded consecutive number. Thereafter, the addition instruction is retained and addition is performed, and is canceled when the data section is completed. With the above configuration, even if an error occurs in consecutive addresses on the semiconductor memory section, the addition instruction can be changed accordingly, thereby improving the usage efficiency of the semiconductor memory section. [Example] Hereinafter, the present invention will be explained in more detail with reference to Examples shown in FIGS. 2 to 5.

FIG. 2 is a diagram showing the configuration of an embodiment of the present invention. Director section (DIR) 1, service processor (sv
p) The operations of the semiconductor memory section 3, address buffer 4, data buffer 5, error address storage section 6, and error address comparison section 7 are the same as in the conventional example shown in FIG.

Reference numeral 11 denotes an error address control section, which checks the error addresses stored in the error address storage section 6 to check whether there are consecutive addresses, and controls addition instructions to the address addition section 8 based on the number of consecutive addresses. The succession section 111 reads out the error addresses stored in the error address storage section 6 in address order. The checking unit 112 compares the sequentially read addresses with the previous address, checks whether there is a continuation, and how many consecutive addresses there are, and if there is, stores the first address and the consecutive number in the storage unit 113. It is memorized in . The addition instruction unit 114 receives a notification from the error address comparison unit 7 that the access address matches the error address, and stores the storage unit 0 at that address.
3 is searched for, the consecutive number is checked, and an addition instruction is output to the address adder 8 based on this number. This addition instruction is held until a cancellation instruction is given. 8 is an address adder 8, which adds address number 1'. , executes an addition instruction instructed by the address control unit 11 to the address value in the file 4, and accesses the semiconductor memory unit 3 based on the output data. FIG. 3 is a flowchart showing processing according to an embodiment of the present invention. The operation will be explained below according to the processing steps of the flowchart.

■After the power is turned on and before operating the system, the SVP2 reads/writes test data to the semiconductor memory section 3.
Write and perform initial diagnosis ■If there is no abnormality in the semiconductor memory section 3, jump to step ■; if there is, go to step ■. (2) The SVP 2 stores the error address in the error address storage section 6.

(2) The error address control section 11 reads out the error addresses stored in the error address storage section 6 and checks whether there are consecutive addresses.

■If there are no consecutive addresses, proceed to step ■; if there are, proceed to step ■. (2) The error address control unit 11 stores an instruction to add +1 to the error address.

(2) If there are consecutive addresses, it is stored to instruct to add 10 only to the first address according to the number of consecutive addresses n. For example, if there are two consecutive error addresses at addresses A and (A+1), it is stored to instruct to add +2 only to address A. ■The error address control unit 11 memorizes that no addition instruction is given. Up to this step,
This is a process performed at the time of initial diagnosis.

(2) An address to be read or written is transmitted from the director section 1 in order to access the semiconductor memory section 3.

[Phase] The address sent from the director section 1 is sent to the error address comparison section 7 via the address buffer 4.

(2) The error address comparison section 7 compares the sent address with the error address stored in the error address storage section 6 and checks whether there is a loss.

■If no match is obtained, proceed to step ■; if one loss is obtained, proceed to step 0.

(2) The error address control section 11 does not send an addition instruction to the address addition section 8.

[Phase] The error address control unit 11, at that address,
The stored contents in step (2) are searched and an instruction to add the corresponding amount to be added is sent to the address adding section 8.

(2) The address adder 8 adds the specified addition amount to the address transmitted from the address buffer 4.

■Access the semiconductor memory using the address added by the address adder 8. ■Perform reading/writing to the semiconductor memory section 3 according to the accessed address. [Phase] Director section 1
It is checked whether reading/writing of the data section is completed between the data section and the semiconductor memory section 3.

[Phase] If completed, proceed to step @; if not completed, return to step ■ and repeat the above operation. [Phase] If reading/writing of one data section is completed,
The error address control section 11 cancels the addition instruction sent to the address addition section 8. - The director section 1 checks whether there is data transfer to the next count section or data section across the gap. @If there are still more, return to step ■ and repeat the above operation, otherwise end the process. FIG. 4 is a diagram showing an error occurrence state in the track emulation format. When reading/writing the same data section as the one in which the error occurred, as indicated by the cross in the figure, , the error address control unit 11 continues to send the addition instruction at step 0 shown in FIG. 3 from the point where the error occurred until the end of that data section. phase].

FIG. 5 is a diagram illustrating an example of processing according to an embodiment of the present invention.

In this example, it is assumed that an error occurs at two consecutive addresses 0005 and 0006 in the semiconductor memory unit 3.

The director unit 1 attempts to access the semiconductor memory unit 3 that includes the error address, but since there is no error location from address 0001 to address 0004 and the address does not match the address stored in the error address storage unit 6, the error address The control unit 11 does not instruct addition, but directly accesses the semiconductor memory unit 3 using the address from the director unit 1. Next, when the director unit 1 transmits the address 0005, it will be lost to the address stored in the error address storage unit 6, so the error address control unit 11
sends an addition instruction. The error address control unit l1 checks in advance whether consecutive addresses exist in the error address storage unit 6, and stores the addition amount accordingly, and in the above case, sends an instruction to add +2. Therefore, the semiconductor memory unit 3 is accessed at address 0007 where the +2 addition instruction was executed.

After that, when the director section 1 transmits data from address 0006 to address 000F, where the data section ends, the +2 addition instruction sent from the error access control section l1 remains as it is because it is within the same data section, and the semiconductor memory section 3
Addresses 0007 to 0011 are accessed. Furthermore, when the director unit 1 transmits the address 0021 and beyond, which is the beginning of the next count section or data section, with a gap in between, the addition instruction from the error address control section l1 is canceled and the address transmitted from the director section 1 is You can now access the semiconductor memory section 3 by leaving it as it is. [Effects of the Invention] As is clear from the above description, according to the present invention, even if an error occurs in memory at consecutive addresses on the semiconductor memory section, the address of the error location can be skipped by the control of the error address control section. This has the remarkable industrial effect of making it possible to use the semiconductor memory section effectively without wasting it.

[Brief explanation of drawings]

Fig. 1 is a diagram showing the configuration of the present invention, Fig. 2 is a diagram showing the configuration of an embodiment of the invention, Fig. 3 is a flowchart showing processing according to an embodiment of the invention, and Fig. 4 is an emulation format. 5 is a diagram illustrating an example of processing according to an embodiment of the present invention. FIG. 6 is a diagram illustrating the configuration of a conventional example. FIG. 7 is a diagram illustrating an emulation format of a semiconductor disk device. FIG. 8 is a flowchart showing processing according to a conventional example. In the figure, 1 is the director section (DIR), 2 is the svp, 3 is the semiconductor memory section, 4 is the address buffer, 5 is the data buffer, 6 is the error address storage section, 7 is the error address comparison section, and 8 is the address adder. 9 is an address bus, 10 is a data path, 11 is an error address control section, 111 is a reading section, 112 is a check section,
113 is a storage unit, 114 is an addition instruction unit, (1) to 06), and ■ to @ are processing steps. FIG. 1 is a flowchart showing processing according to an embodiment of the present invention.FIG. 1 (part 1) FIG. Part 2) Figure 7 is a diagram showing an example of the emulation format of a semiconductor disk device.

Claims (1)

[Claims] The device includes a semiconductor memory section (3) configured with a semiconductor memory element and stores information, a director section (1) that executes data transfer, and a service processor (2) that executes diagnosis, maintenance, etc. In the semiconductor disk device, the error address storage section (2) stores an error address when the occurrence of an error is detected in the semiconductor memory section (3) by diagnosis from the service processor (2).
6) and from the director section (1) to the semiconductor memory section (3).
an error address comparison unit (7) that compares the access address with the address stored in the error address storage unit (6) when accessing the error address storage unit (6), and checks whether a continuous address exists in the error address storage unit (6). an error address control unit (11) that controls an address addition instruction based on the number of consecutive addresses, and an address addition unit (11) that executes an addition instruction from the error address control unit (11) to the access address when an error address is selected. 8), the semiconductor memory unit (3) is accessed by the output of the address adder (8), and when an error occurs in consecutive addresses in the semiconductor memory unit (3), the consecutive error addresses are A memory control method in a semiconductor disk device characterized by controlling the memory so as to skip access only.