KR830002883B1 - Micro programmable controller - Google Patents

Abstract

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Description

Micro programmable controller

Fig. 1 is a main block diagram of an example of an information processing apparatus of a micro program control system according to the present invention.

The present invention relates to an information processing apparatus and the like of microprogram control.

In an information processing apparatus that controls hardware by a micro instruction, an error is usually performed by performing a parity check or a hamming code check on a micro instruction read out from a control memory. Is detected.

When an error of a micro instruction is detected, as a recovery method, the micro instruction is repeatedly read and reread, and the micro instruction is read from an accumulator which stores the same information as that of the control memory to continue execution of the micro instruction. The method of correcting the error detection point of memory is conventionally used.

In the case of permanent disturbances, however, the normal microcommand cannot be obtained in the former way. In the latter method, since the possibility of correcting an error is low, an operation of reading out from the accumulator every time an error is required. As described above, the conventional method takes a considerable time to recover the error of the micro-instruction, and at the same time, there is a problem that it becomes complicated with logic for realizing the control.

SUMMARY OF THE INVENTION An object of the present invention is to provide a micro-program control apparatus which greatly reduces the down time of operation due to an error of a miter command and simplifies logic for recovering an error.

Therefore, in the present invention, a plurality of control memories are provided, and each micro instruction group having the same contents is stored, and one control memory is selected, which is high, and the micro instruction is read out and executed.

When an error is detected in the micro instruction read out from this control memory, subsequent control is executed by switching to another control memory. Next, an embodiment of an information processing apparatus of a microprogram control system according to the present invention will be described with reference to the drawings.

1, 2, 3, and 4 are control memories for storing the same microprogram, respectively, and each control memory is composed of a single or a plurality of memories.

5 is a data selection circuit which reads the micro-instructions read out from one of the control memories 1 to 4 selected from the control memories 1 to 4 and supplies them to the data register 8.

7 is an error detection circuit for checking an error of a micro instruction read into the register 8.

6 is a read control circuit for controlling the selection of the control memory in the data selection circuit 5 and controlling the address register 9 at the same time.

10 is a write control circuit for controlling the writing of the control memories 1 to 4. Since it is not directly related to this invention other than this, description is abbreviate | omitted.

The operation of this embodiment will be described below.

First, when the power is turned on or when an initial load instruction is issued, the head address of the control memory is set in the address register 9 by the address update command line 14, and it comes out in the address line 13.

A micro instruction code is loaded on the write data line 11. By the write line 12 from the write control circuit 10, micro-commands are written to the control memories 1 to 4 simultaneously or sequentially. Next, the address register 9 is updated by the address update command line, and the next micro command is loaded on the write data line 11 to perform writing.

By repeating the same operation, the micro instruction group is written to all the control memories 1 to 4.

Next, the read control circuit 6 is operated by the data select replacement instruction line 20.

By the read data selected 17, the data selection circuit 5 sequentially selects the read data lines 21 to 24 of the control memories 1 to 4. FIG.

In this way, check that there are no errors in the microcommands in each control memory.

Before starting the actual processing, the data selection replacement instruction line 20 instructs the read control circuit 6 to select one specific control memory, for example, the control memory 1. As a result, the data selection circuit 5 selects the read data line 21. The address update command line 14 is used to set the start address of the micro instruction and the address register 9. The first micro instruction is read from the control memory 1 and latched to the read data register 8 via the data select circuit 5 thereon.

The output 19 of this register 8, i.e., the microinstruction, is executed in the error detection circuit 7 if the error is checked and is normal. Thereafter, while updating the address register 9, micro-instructions are sequentially read out and executed in the control memory 1, and various checks are also performed.

If an error is detected in a microcommand, a signal is issued to the error detection line 16 of the error detection circuit 7. When this signal is issued, the read control circuit 6 suppresses the update of the address register 9 by the address update suppressing line 15. That is, the address of the micro instruction in which the error is detected is stored.

At the same time, the read control circuit 6 instructs the data selection circuit 5 to select one control memory other than the control memory 1 by the data selection line 17.

As a result, the data selection circuit 5 selects the control memory 2, for example.

By reading the control memory 2 in this state, the micro instruction of the address stored and held in the address register 9 is read out to the read data line 22, which is then passed through the data selection circuit 5 to the read data register. (8) is latched.

If this micro instruction is normal, the read control circuit 6 cancels the update suppression of the address register 9.

After that, the micro instruction is sequentially read from the control memory 2 and executed.

When an error is detected in the micro instruction read out from the control memory 2, the micro instruction execution is continued by replacing the control memories 3 and 4 in the same manner.

The order of replacement of control memory is arbitrary.

In this embodiment, the same address is given to the four control memories, but an address space corresponding to all the control memories may be set and a specific control memory may be designated in the upper two bits of the address.

In this case, another microcommand may be stored in each control memory at the time of diagnosis immediately after the initial load of the microcommand. The present invention has been described, and since the normal microcommand can be obtained immediately by replacing the control memory at the time of detecting the microcommand error, the waste of time is drastically reduced, and the error of the microcommand due to the permanent failure is assuredly. Since recovery can be avoided, the device can be stopped.

Although the above embodiment has been described assuming a random access memory as a control memory, it goes without saying that the present invention can be implemented even in a read only memory.

Claims (1)

Means for selecting one from a plurality of control memories and a plurality of control memories storing the same microprogram and reading microcommands therefrom, and detecting an error of a microcommand read out from the control memory selected by the selection means; Means and a means for replacing the selection of the control memory in the selection means when an error is detected in the error detection means, and executing a micro instruction read out from the control memory selected in the selection means. .

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