JP2000020489A - Data transfer device for computer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently execute data transfer between a CPU and communication control equipment connected to an external line. SOLUTION: Communication control equipment 4a connected to an external device refers to transfer control information for a CPU 2 to transfer data written in a descripter 7 in a fixed cycle so as to apply the information to a data transfer device for computer to perform data transfer between the CPU 2 and the communication control equipment 4a. On the side of the communication control equipment 4a, a cache memory 10 is provided for storing the transfer control information in the descripter 7, the communication control equipment refers to the transfer control information in the cache memory 10, and an updating means is provided for updating stored contents in the cache memory 10 corresponding to the update of stored contents in the descripter 7.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer device in a computer for transferring data between a CPU and a communication control device connected to an external device via a descriptor.

[0002]

2. Description of the Related Art In a computer that frequently transmits and receives data to and from an external device, a computer that performs various arithmetic processes and a communication control device that transmits and receives data to and from the external device. As a method for efficiently performing the transfer, a data transfer method using a descriptor has been proposed.

FIG. 5A is a block diagram showing a schematic configuration of a computer in which a data transfer device using a disk printer is incorporated. A CPU 2 that performs various arithmetic processing, a main storage unit 3, and a communication control device 4 that transmits and receives data to and from a plurality of networks 5 as external devices are connected to a system bus 1 of the computer. .

[0006] In the main storage unit 3, a plurality of disc printers 7 are formed in addition to the data memory 6 for storing various normal data. Therefore, each of the descriptors 7 is formed in, for example, the main storage unit 3 accessible by both the CPU 2 and the communication control device 4.

As shown in FIG. 6, a transfer address 9b indicating a head address of a storage area 6a of data to be transferred in the data memory 6 and a data size 9c are written in each of the descriptors 7. Further, control information 9a and transfer status 9d are stored in each descriptor 7.

[0006] The control information 9a includes the disc printer 7
A valid flag (disc printer valid flag) 10a indicating that the transfer control information composed of the transfer address 9b and the data size 9c written in the disc is valid, and a continuation flag 10b indicating that the disc printer 7 is continuous. Is set.

Further, a transfer end status 11a and an error occurrence status 11b indicating that an error has occurred during the transfer are set in the transfer status 9d. In the data transfer device having such a configuration, when the CPU 2 transfers data in the data memory 6 to the communication control device 4, first, the CPU 2
, The transfer address 9b and the data size 9c are set, and the valid flag 10a of the control information 9a is set.

The communication control device 4 always refers to (polls) the descriptor 7 in the main storage unit 3 at a predetermined fixed cycle, and the validity flag 1
If 0a is set, data of a data size 9c is read from the data memory 6 from the transfer address 9b stored in the descriptor 7 and transferred to the own communication control device 4. When the data transfer ends, the transfer end status 11a is set in the transfer status 9d.

Conversely, when the CPU 2 takes in data from the communication control device 4, the data is transferred to the CP similarly to the communication control device.
U2 sets the transfer address 9b and the data size 9c in the descriptor 7, and sets the valid flag 10a of the control information 9a.
Set. When the communication control device 4 confirms that the valid flag 10a has been written, the data is transferred to the storage area 6a in the data memory 6 specified by the transfer address 9b and the data size 9c written in the descriptor 7. Is written (transferred).

FIG. 5B is a block diagram showing a schematic configuration of a computer in which another data transfer device using a descriptor is incorporated. In this computer, the descriptor 7 is formed not in the main storage unit 3 but in a memory 8 for storing the descriptor. Then, the CPU 2 accesses the disk printer 7 in the disk printer storage memory 8 via the system bus 1, and the communication controller 4 directly accesses the disk printer 7 in the disk printer storage memory 8. With such a configuration, the load on the system bus 1 is reduced by the amount by which the communication control device 4 directly accesses the descriptor 7.

[0011]

However, FIG.
The data transfer devices shown in (a) and (b) still have the following problems to be improved. That is, CPU2
When the transfer speed of data from the communication control device 4 to the communication control device 4 is increased, or conversely, the transfer speed of data from the communication control device 4 to the CPU 2 is increased, the communication control device 4 refers to the reference period ( Polling cycle) must be set short.

However, if the reference period (polling period) is set short, the communication controller 4 accesses the descriptor 7 via the system bus 1 in the calculator shown in FIG. The burden on the computer increases, and a problem arises that the original data processing efficiency of the computer decreases.

On the other hand, in the computer shown in FIG. 5B, as described above, the load on the system bus 1 is reduced by the amount by which the communication control device 4 directly accesses the descriptor 7. CPU such as RAM
A dedicated descriptor storage memory 8 accessible from both the communication control device 2 and the communication control device 4 is required, which complicates the entire computer.

The present invention has been made in view of such circumstances, and by providing a cache memory for storing the storage contents of the descriptor in addition to the descriptor, the communication control apparatus can directly The number of times to access the descriptor can be reduced as much as possible,
Even if the reference period of the transfer control information from the communication control device is shortened, the increase in the load on the system bus can be suppressed, and the data transfer between the CPU and the communication control device can be performed without lowering the original data processing efficiency of the computer. An object of the present invention is to provide a data transfer device in a computer that can improve efficiency.

[0015]

SUMMARY OF THE INVENTION According to the present invention, a communication control device connected to an external device refers to transfer control information for performing data transfer written in a descriptor by a CPU at a constant period. The present invention relates to a data transfer device in a computer that performs data transfer between a CPU and a communication control device.

In order to solve the above problem, in the present invention, a cache memory for storing transfer control information of a descriptor is provided on the communication control device side, and the communication control device is made to refer to the transfer control information of the cache memory. Updating means for updating the storage contents of the cache memory in accordance with the update of the storage contents of the descriptor.

In the data transfer device of the computer configured as described above, for example, when the transfer control information written in the descriptor formed in the main storage unit is rewritten by, for example, the CPU, the storage contents of the cache memory are also changed. Be updated.

The transfer control device may refer to (polling) the transfer control information stored in the cache memory at regular intervals, instead of the descriptor. Since this cache memory is provided on the communication control device side,
The communication controller can access the cache memory without going through the system bus.
Even if the cycle is set short, it does not impose an excessive burden on the system bus.

Therefore, the data transfer efficiency between the CPU and the communication control device can be improved without lowering the original data processing efficiency of the computer. In another invention,
In the cache memory, transfer control information including a transfer address and a data size for executing data written in the descriptor is stored.

In the data transfer device in the computer configured as described above, all the transfer control information written to the descriptor is stored in the cache memory. Therefore, the frequency of referring to the descriptor further decreases.

In another aspect of the present invention, a validity flag set in the cache memory when the transfer control information stored in the cache memory is valid is further added to the data transfer device in the computer according to the above invention. Only when the validity flag is set, reference to the transfer control information in the cache memory of the communication control device is permitted.

In the data transfer device in the computer configured as described above, when the communication control device refers to the cache memory, the communication control device first looks at the setting status of the validity flag, and transfers the transfer control information stored only when the data is valid. I read it out.

Therefore, the processing load on the communication control device can be reduced. In another aspect of the present invention, the updating means in the data transfer device in the computer according to the present invention comprises: a writing operation detecting means for detecting a writing operation of new transfer control information to the descriptor; It comprises flag releasing means for releasing the valid flag when an operation is detected, and writing means for writing the transfer control information read from the descriptor by the communication control device into the cache memory in the flag released state.

In the data transfer device in the computer configured as described above, when new transfer control information is written to the descriptor, the valid flag of the cache memory is released, and reference to the cache memory is prohibited. Then, the communication control device writes the new transfer control information from the descriptor into the cache memory.

In still another aspect of the invention, the updating means in the data transfer device in the computer according to the invention includes a writing operation detecting means for detecting an operation of writing new transfer control information to the descriptor, and a writing operation detecting means. When writing operation is detected, writing means for fetching the new transfer control information output on the data bus for writing to the descriptor and writing it to the cache memory is provided.

In the data transfer device in the computer configured as described above, when new transfer control information is written to the descriptor, the new transfer control information output on the data bus for writing to the descriptor is written. Captured and written to cache memory.

Therefore, in this case, the communication control device does not participate in the update processing for the cache memory at all. Therefore, the processing load on the communication control device is further reduced.

[0028]

Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIG. 1 is a block diagram showing a schematic configuration of a computer in which a data transfer device according to a first embodiment of the present invention is incorporated. The same components as those of the computer in which the conventional data transfer device shown in FIGS. 5A and 6 are incorporated are denoted by the same reference numerals. Therefore, the detailed description of the overlapping part will be omitted.

A CPU 2 for performing various arithmetic processing, a main storage unit 3, and a communication control unit 4a for transmitting and receiving data to and from a plurality of networks 5 as external devices are connected to a system bus 1 of the computer. Have been.

In the main storage unit 3, a plurality of disc printers 7 are formed in addition to the data memory 6 for storing various kinds of normal data. In each descriptor 7,
As shown in FIG. 6, a transfer address 9 indicating a head address of a storage area 6a of data to be transferred in the data memory 6.
b and the data size 9c are written. Further, in each descriptor 7, control information 9a including a valid flag 10a and a transfer status 9d including a transfer end status 11a are stored.

In the data transfer device of the first embodiment, the cache memory 10 is connected to the communication control device 4a. This cache memory 10
Is written (copied) to the storage contents of the descriptor 7 formed in the main storage unit 3 as necessary. More specifically, the communication control device 4a reads the content stored in the descriptor 7 via the system bus 1 and writes the content in the cache memory 10.

When the CPU 2 transfers the data in the data memory 6 to the communication control device 4a, first, the CPU 2
2 sets the transfer address 9b and the data size 9c for the descriptor 7 of the main storage unit 3, and sets the control information 9a.
Is set.

The communication control device 4 always refers to the contents stored in the cache memory 10 at a predetermined period. If the transfer control information shown in FIG. 6 is not stored in the cache memory 10 in this reference process, or if the valid flag 10a is released even if the transfer control information is stored, the main storage unit is connected via the system bus 1. 3 disk printer 7
CPU 2 reads out the transfer control information written therein and writes it into cache memory 10.

The communication control device 4a includes the cache memory 1
In a state where the transfer control information is written to 0, the validity flag 10a in the transfer control information stored in the cache memory 10 is checked, and only when the validity flag is set, the data is cached in the cache memory 10. The transfer address 9 stored in the
The data of the data size 9c from b is read from the data memory 6 and transferred to its own communication control device 4a. When the data transfer ends, the transfer end status 11a is set in the transfer status 9d.

Conversely, when the CPU 2 takes in data from the communication control unit 4a, the CPU 2 sets the transfer address 9b and the data size 9c to the descriptor 7 in the same manner as when transferring data to the communication control unit 4a. Then, the valid flag 10a of the control information 9a is set. Communication control device 4a
If necessary, the contents stored in the descriptor 7 of the main storage unit 3 are written to the cache memory 10 in the same procedure as described above.

The communication control device 4a includes the cache memory 1
When it is confirmed that the valid flag 10a in the transfer control information cached to 0 has been set, the data memory 6 specified by the transfer address 9b and the data size 9c written in the cached descriptor 7 is read.
The data is written (transferred) to the storage area 6a in the memory.

The communication controller 4a is connected to the system bus 1
, The address of the dispatcher 7 is monitored. When the access of the dispatcher 7 is made, it is determined that the storage content of the dispatcher 7 has been updated by the CPU 2, and the validity flag 10a of the transfer control information of the cache memory 10 is released ( Snoop operation).

In the data transfer device of the first embodiment configured as described above, the communication control device 4a transmits the transfer control information cached in the cache memory 10 from the disk printer 7 instead of the disk printer 7 for a predetermined period. Reference (polling) may be performed.

Since the cache memory 10 is provided on the communication control device 4a side, the communication control device 4a can access the cache memory 10 without passing through the system bus 1. Therefore, the reference (polling) cycle is set short. However, the system bus 1 is not overloaded.

The system bus 1 is used when updating the cache memory 10. However, the frequency of use of the system bus 1 is much lower than the frequency of reference (polling) performed by the communication control device 4a on the cache memory 10, so that the system bus 1 is used. The increase in burden is small.

Therefore, the data transfer efficiency between the CPU 2 and the communication control device 4a can be improved without lowering the original data processing efficiency of the computer. In the first embodiment, the transfer address related to the reference stored in the descriptor 7 shown in FIG.
The transfer control information including the data size was written. However, for example, it is possible to remove the control information 9a and the transfer status 9d from the transfer control information. In this case, the communication control device 4 a
Need to be monitored for updates.

(Second Embodiment) FIG. 2 is a block diagram showing a schematic configuration of a computer in which a data transfer device according to a second embodiment of the present invention is incorporated. The same parts as those of the computer according to the first embodiment shown in FIG. Therefore,
A detailed description of the overlapping part will be omitted.

A CPU 2, a main storage unit 3, and a communication control unit 4b are connected to a system bus 1 including an address bus 1a, a data bus 1b, a write line 1c, and a read line 1d. An access control circuit 11 is interposed between the communication control device 4b and the address bus 1a and the lead wire 1d. A plurality of networks 5 are connected to the communication control device 4b via a full-duplex communication line 12.

In this computer, in order to realize full-duplex communication, in the main memory 3, in addition to the data memory 6 described above, four descriptors 7a, 7b, 7c,
7d is formed. As shown in FIG. 6, control information 9a, a transfer address 9b, a data size 9c, and a transfer status 9d are set in each of the descriptors 7a to 7d. Therefore, in this computer, four cache devices 13a, 13b, 13c, 13d are provided corresponding to each of the descriptors 7a, 7b, 7c, 7d.

In each of the cache devices 13a to 13d,
The address memory 14 for storing the storage addresses of the descriptors 7a to 7d in charge in the main storage unit 3, the data memory 15 for storing the transfer control information of the corresponding descriptors 7a to 7d, and the corresponding transfer control information is valid. A flag memory 16 for storing a valid flag indicating that there is, and two comparators 17 and 18 are incorporated.

One comparator 17 compares an address output on the address bus 1a with an address stored in its own address memory 14 when a write command is output to the write line 1c. If they match, the CPU 2 determines that the transfer control information of the corresponding descriptors 7a to 7d has been rewritten by the CPU 2, and releases the valid flag in the flag memory 16.

When the valid flag is set in the flag memory 16, the other comparator 18 stores the address that can be output from the communication control device 4b via the address line 20 and its own address memory 14. The address and the address are compared, and if they match, a selection signal a is sent to the selector 19.

The selector 19 selects the corresponding data 1, 2, 3, 4 of the transfer control information according to the selection signals a, b, c, d from the comparator 18 and sends the data to the communication control device 4b. Send out. If none of the selection signals a to d is output, the data of the transfer control information read on the data bus 1b is selected and sent to the communication control device 4b.

Further, when any one of the selection signals a, b, c, and d is output from the comparator 18, the access control circuit 11 outputs a read command output from the communication control device 4b via the lead 21. To the lead 1d of the system bus 1. The access control circuit 11 prohibits the output of an address to the address bus 1a of the system bus 1 while any one of the selection signals a, b, c, and d is output and the read command is output.

Next, the operation of the data transfer apparatus according to the second embodiment having the above-described configuration will be described. First, CPU2
Are the address bus 1a and the data bus 1 of the system bus 1.
b, each of the descriptors 7a to 7 in the main storage unit 3
The address indicating the storage position of d is sent to the communication control device 4b. The communication control device 4b writes each received address to each address memory 14 in each of the cache devices 13a to 13d via the signal line 22. Further, the valid flag in the flag memory 16 is released.

Next, the communication control device 4a stores each data in the main storage unit 3 in order to secure a storage area for data transferred from the CPU 2 and to confirm that data to be transmitted to the CPU 2 is ready. A first reference (polling) process for the descriptors 7a to 7d is started.

At this point, each cache device 1
Since the valid flags of the flag memories 16 of 3a to 13d remain released, the selection signals a to d are not output at all. As a result, a read command output from the communication control device 4b via the lead 21 is output to the lead 1d of the system bus 1 via the access control circuit 11. Further, an address output from the communication control device 4b via the address line 20 is output to the address bus 1a of the system bus 1 via the access control circuit 11.

As a result, the data of the transfer control information of the addressed descriptors 7a to 7d in the main storage unit 3 is read onto the data bus 1b. As described above, at this time, the selection signals a to d are not output at all, so that
The transfer control information output onto the data bus 1b is taken into the communication control device 4b via the selector 19.

The communication control device 4b transmits the fetched transfer control information to the cache device 13 designated via the signal line 22.
The data is written into the data memory 15 of a to 13d. Further, a valid flag in the flag memory 16 is set.

When the transfer control information initialization process for all the cache devices 13a to 13d is completed, the communication control device 4b reads the transfer control information of each of the cache devices 13a to 13d and uses the read transfer control information. Then, the data stored in each storage area 6a of the data memory 6 is transferred to its own communication control device 4b, and each data fetched from the network 5 is stored in each storage area 6a of the data memory 6 of the main storage unit 3. Write.

Next, the communication control unit 4b starts a second reference process for the descriptors 7a to 7d in the main storage unit 3. In this case, since a valid flag is set in each flag memory 16 of each of the cache devices 13a to 13d, any one of the four selection signals a to d is output. 7d, not the data memory 15 of the cache devices 13a to 13d.
The transfer control information is read from the communication controller 4 and input to the communication control device 4 b via the selector 19.

Since any one of the four selection signals a to d is output, the access control circuit 11 prohibits the read command output from the communication control device 4b from being output to the system bus 1. .

Next, the processing in the case where the CPU 2 rewrites (updates) the transfer control information set in the descriptors 7a to 7d of the main storage section 3 will be described. In this case, the comparator 17
Are described in the above description, the descriptors 7a to 7
Since it is detected that the storage content of d has been updated, the valid flag in the flag memory 16 is released. As a result, the access control circuit 11 shifts to a state in which an address and a read command to the system bus 1 can be output.

In this state, when the communication control device 4b performs a reference (polling) to the corresponding descriptors 7a to 7d in the main storage unit 3, the valid flag in the flag memory 16 is released. Cash device 13
The selection signals a to d are not output from the comparators 18 of a to 13. Instead, the corresponding updated descriptors 7 a to 7 output on the data bus of the system bus 1 are updated.
The transfer control information read from d is input to the communication control device 4b via the selector 19.

The communication control device 4 b transmits the fetched transfer control information to the cache device 13 designated via the signal line 22.
The data is written into the data memory 15 of a to 13d. Further, a valid flag in the flag memory 16 is set.

The communication control device 4b reads the transfer control information of the corresponding cache devices 13a to 13d and uses the read transfer control information to transfer the data stored in each storage area 6a of the data memory 6 to its own. Communication control device 4b
Or writes each data taken from the network 5 into each storage area 6a of the data memory 6 of the main storage unit 3.

In the data transfer device of the second embodiment configured as described above, in the normal state, the communication control device 4a operates, for example, each of the descriptors 7a to 7a of the main storage unit 3.
Even if reference (polling) processing is performed on the cache device 13d at regular intervals, if the validity flags are set in the cache devices 13a to 13d, the comparator 18 and the access control circuit 11 operate to operate the main storage unit. 3 is prohibited. Instead, the data transfer between the CPU 2 and the communication control device 4 is performed using the transfer control information stored (cached) in the data memory 15 of the corresponding cache device 13a to 13d. ing.

Therefore, the frequency at which the communication control device 4a directly accesses the system bus 1 is reduced. Therefore, even if the reference (polling) cycle for the transfer control information of the communication control device 4a is set to be short, the system bus 1 is particularly not affected. There is no increase in the load.

Further, when the setting contents of the descriptors 7a to 7d of the main storage unit 3 are updated by the CPU 2, the communication control device 4b automatically transfers the transfer contents stored in the data memory 15 of the cache devices 13a to 13d. Control information is automatically updated.

(Third Embodiment) FIG. 3 is a block diagram showing a schematic configuration of a computer in which a data transfer device according to a third embodiment of the present invention is incorporated. The same parts as those of the computer according to the second embodiment shown in FIG. Therefore,
A detailed description of the overlapping part will be omitted.

In the data transfer device according to the third embodiment, the four cache devices 23a, 23b, 23c, and 23d provided on the communication control device 4c side have the main components of the descriptors 7a to 7d assigned to them. An address memory 14 for storing storage addresses in the storage unit 3, a data memory 15 for storing transfer control information of the corresponding descriptors 7a to 7d, and two comparators 17a and 18a are incorporated.

One comparator 17a compares an address output to the address bus 1a with an address stored in its own address memory 14 when a write command is output to the write line 1c. If they match, the transfer control information of the corresponding descriptors 7a to 7d is
Is determined to have been rewritten. Further, the comparator 17a fetches transfer control information for writing to the disk printers 7a to 7d from the CPU 2 output to the data bus 1b of the system bus 1 via a signal line 24 and writes the transfer control information to the data memory 15.

That is, when the transfer control information of the descriptors 7a to 7d in the main storage unit 3 is updated, the comparator 17a transfers the transfer control information stored in the data memory 15 of the corresponding cache device 23a to 23d. Information is automatically updated in synchronization. In this manner, the cache devices 23a to 23a-2
Since the transfer control information stored in the 3d data memory 15 always matches the transfer control information of the descriptors 7a to 7d of the main storage unit 3, the cache devices 23a to
No valid flag is provided in 23d.

The other comparator 18a is connected to the communication control device 4b
Then, the address output from the address line 20 via the address line 20 is compared with the address stored in its own address memory 14, and if they match, a selection signal a is sent to the selector 19.

The selector 19 selects the corresponding data 1, 2, 3, 4 of the transfer control information according to the selection signals a, b, c, d from the comparator 18a, and
Send to If none of the selection signals a to d is output, the data of the transfer control information read out on the data bus 1b is selected and sent to the communication control device 4c.

The configuration and operation of the access control circuit 11 are the same as those of the access control circuit 11 of the second embodiment. The configuration and operation of the communication control device 4c are basically the same as those of the communication control device 4b of the second embodiment.

In the data transfer device of the third embodiment configured as described above, each of the cache devices 23a to 23a
Since the storage content of d is automatically updated by the automatic update function of the cache device itself, the communication control device 4c, for example, at the time of initial setting, , Reference (polling)
Although the processing is performed, access to the main storage unit 3 via the system bus 1 is not performed thereafter, so that the processing load on the communication control device 4c can be reduced and the load on the system bus 1 can be reduced.

(Fourth Embodiment) FIG. 4 is a block diagram showing a schematic configuration of a computer in which a data transfer device according to a fourth embodiment of the present invention is incorporated. The same parts as those of the computer according to the third embodiment shown in FIG. 3 are denoted by the same reference numerals. Therefore,
A detailed description of the overlapping part will be omitted.

In the data transfer device of the fourth embodiment, the four cache devices 25a, 25b, 25c, 25d provided on the communication control device 4d side have the main components of the descriptors 7a to 7d assigned to them. An address memory 14 for storing storage addresses in the storage section 3, a data memory 15 for storing transfer control information of the corresponding descriptors 7a to 7d, and one comparator 17a are incorporated.

The comparator 17a has almost the same function as the comparator 17a in the data transfer device of the third embodiment shown in FIG.
When the transfer control information of d is updated, the transfer control information stored in the data memory 15 of the corresponding cache device 25a to 25d is also automatically updated in synchronization.

It should be noted that, even when the transfer control information is newly set in the descriptors 7a to 7d, the comparator 17a keeps the cache devices 23a to 23d in the same manner as when updating.
A new data is written in the 3d data memory 15.

As described above, the transfer control information stored in the data memory 15 of the cache devices 23a to 23d always includes the transfer control information of the descriptors 7a to 7d of the main storage unit 3 including the time of new setting. Since they match, the validity flag and the other comparator 18a are not provided in the cache devices 25a to 25d.

Therefore, in the data transfer device of the fourth embodiment, the communication control device 4d does not perform any reference (polling) processing to the descriptors 7a to 7d of the main storage unit 3 via the system bus 1. Reference only to cache devices 25a to 25d (polling)
Perform processing.

Thus, the processing load on the communication control device 4d can be further reduced. Further, it is not necessary to store the addresses indicating the storage positions of the descriptors 7a to 7d in the communication control device 4d, and the number of necessary comparators can be further reduced by half. Thus, the hardware configuration of the data transfer device can be further simplified.

[0080]

As described above, in the data transfer device in the computer according to the present invention, in addition to the descriptor, a cache memory for storing the storage contents of the descriptor is provided on the communication control device side.

Therefore, the number of times the communication control device directly accesses the descriptor can be reduced as much as possible.
Even if the reference period of the transfer control information from the communication control device is shortened, the increase in the load on the system bus can be suppressed, and the data transfer between the CPU and the communication control device can be performed without lowering the original data processing efficiency of the computer. Efficiency can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of a computer in which a data transfer device according to a first embodiment of the present invention is incorporated.

FIG. 2 is a block diagram showing a schematic configuration of a computer in which a data transfer device according to a second embodiment of the present invention is incorporated;

FIG. 3 is a block diagram showing a schematic configuration of a computer in which a data transfer device according to a third embodiment of the present invention is incorporated.

FIG. 4 is a block diagram showing a schematic configuration of a computer in which a data transfer device according to a fourth embodiment of the present invention is incorporated.

FIG. 5 is a block diagram showing a schematic configuration of a computer in which a conventional data transfer device is incorporated.

FIG. 6 is a diagram showing a relationship between storage contents of a general descriptor and respective storage areas of data in a data memory.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... System bus 2 ... CPU 3 ... Main storage part 4a, 4b, 4c, 4d ... Communication control device 5 ... Network 6 ... Data memory 7a, 7b, 7c, 7d ... Disc printer 10 ... Cache memory 11 ... Access control circuit 13a , 13b, 13c, 13d, 23a, 23b, 2
3c, 23d, 25a, 25b, 25c, 25d Cache device 14 Address memory 15 Data memory 16 Flag memory 17, 17a, 18, 18a Comparator 19 Selector

Claims (5)

[Claims] 1. A communication control device connected to an external device refers to transfer control information for performing data transfer written to a descriptor by a CPU at a constant period,
In a data transfer device in a computer that performs data transfer between the CPU and the communication control device, a cache memory for storing transfer control information of the descriptor is provided on the communication control device side, and the cache is provided in the communication control device. Refer to the transfer control information of the memory,
A data transfer device in a computer, further comprising updating means for updating storage contents of the cache memory in accordance with updating of storage contents of the descriptor. 2. The cache memory according to claim 1, wherein transfer control information including a transfer address and a data size for executing said data written in said descriptor is stored. A data transfer device in the computer as described. 3. The cache memory according to claim 1, further comprising a valid flag set when the transfer control information stored in the cache memory is valid, and the cache of the communication control device being set only when the valid flag is set. 2. The data transfer device in a computer according to claim 1, wherein reference to the transfer control information in the memory is permitted. 4. The updating means comprises: a writing operation detecting means for detecting a writing operation of new transfer control information to the disc printer; and when the writing operation detecting means detects a writing operation, the updating means sets the valid flag. 4. The apparatus according to claim 3, further comprising: a flag canceling means for canceling; and a writing means for writing the transfer control information read from the descriptor by the communication control device to the cache memory in the flag canceled state. Data transfer device in a computer. 5. The updating unit includes: a writing operation detecting unit that detects a writing operation of new transfer control information with respect to the descriptor; and when the writing operation detecting unit detects a writing operation, 4. A writing means for fetching the new transfer control information output on the data bus for writing and writing the new transfer control information into the cache memory.
A data transfer device in the computer as described.