WO1995006284B1 - Ata interface architecture employing state machines - Google Patents

Abstract

An ATA interface apparatus (Fig. 5), within a storage system, for controlling the transfer of sectors of data between a host processor and a buffer (11) within the storage system in response to READ and WRITE command issued by the host processor, the apparatus (Fig. 5) comprising a Byte Count State Machine (4) for controlling the transfer of sectors of data between the host processor and the buffer (11), an Update Task File State Machine (5) having a machine cycle for decrementing by one the number of sectors still to be transferred after a sector has been transferred by the Byte Count State Machine (4), a Read State Machine (6) for controlling the processing of all READ commands issued by the host to the storage system and a Write State Machine (7) for controlling the processing of all WRITE commands issued by the host to the storage system.

Claims

AMENDED CLAIMS[received by the International Bureau on 14 March 1995 (14.03.95); original claims 1 and 4-7 amended; remaining claims unchanged (4 pages)]

1. An interface apparatus, within a storage system, for controlling the transfer of sectors of data between a host processor and a buffer within the storage system in response to READ and WRITE command issued by the host processor, said apparatus comprising; a Byte Count State Machine for controlling the transfer of a sector of data between said host processor and said buffer and for generating a signal indicating when said last byte of data has been transferred for a sector; a Update Task File State Machine having a machine cycle for decrementing by one the number of sectors still to be transferred after a sector has been transferred by said Byte Count State Machine and for causing a sector address to be generated for the next sector to be transferred by said Byte Count State Machine; a Read State Machine for controlling the processing of all READ commands issued by said host processor to said storage system and processing said received READ command in response to said last byte signal generated by said Byte Count State Machine and the initiation of machine cycles in said Update Task File State Machine to maintain the count of the number of sectors still to be read and the generation of then next sectors address where a next sector is to be read; and a Write State Machine for controlling the processing of all WRITE commands issued by said host processor to said storage system and processing said received WRITE command in response to said last byte signal generated by said Byte Count State Machine and the initiation of machine cycles in said Update Task File State Machine to maintain the count of the number of sectors still to be written and the generation of then next sectors address where a next sector is to be written.

2. The apparatus of Claim 1 further comprising; a data register for temporarily storing data received from said host processor or to be transferred to said host processor; a multiplexer for controlling the data path through said storage system between said buffer and said data register; a buffer controller for controlling the transferring of data into and out of said buffer; and said Byte Count State Machine transfers one byte of data at a time between said data register and said buffer by issuing control signals to said multiplexer and said buffer controller.

3. The apparatus of Claim 2 further comprising; a plurality of AT registers for providing the status of said storage system during the processing of a READ or WRITE command where the contents of said AT registers may be modified and read by said host processor, said Byte Count State Machine, said Update task File State Machine,said Read State Machine and said Write State Machine thereby providing communication paths between said host processor, said Byte Count State Machine, said Update task File State Machine,said Read State Machine and said Write State Machine to facilitate the processing of READ and WRITE commands issued by said host processor.

4. The apparatus of Claim 3 wherein; said data register stores two bytes of data for receiving and sending data words to said host processor where a data word is comprised of two bytes of data, a high byte and a low byte; and said Byte Count State Machine further includes: first means for controlling the separation of said two bytes of data stored in said data register into two sequential bytes of data to be stored in said buffer; and second means for controlling the combining of two sequential bytes from said buffer for storage in said data register to form a data word to be transferred to said host processor.

5. The apparatus of Claim 3 wherein said Read State Machine comprises: third means for generating a gate first word signal to said Byte Count State Machine to allow the first data word to be formed in said data register by said Byte Count State Machine prior to a first request for a data word being generated by said host processor during a READ command.

6. The apparatus of Claim 5 wherein said AT registers comprise: a block count register for storing the number of sectors to be transferred for the block; and said Read State Machine further comprises: fifth means for setting said block count register to a value of 1 for all READ commands except a MULTIPLE READ command, said Read State Machine in response to a value of 1 in said block count register processing all READ commands in the same manner resulting in an increase in overall efficiency of said storage system in processing READ commands.

7. The apparatus of Claim 6 wherein said Write State Machine further comprises: sixth means for setting said block count register to a value of 1 for all WRITE command except a MULTIPLE WRITE command, said Write State Machine in response to a value of 1 in said block count register processing all WRITE commands in the same manner resulting in an increase in overall efficiency of said storage system in processing WRITE commands.