WO1995006284B1 - Architecture d'interface ata utilisant des automates finis - Google Patents

Architecture d'interface ata utilisant des automates finis

Info

Publication number
WO1995006284B1
WO1995006284B1 PCT/US1994/009386 US9409386W WO9506284B1 WO 1995006284 B1 WO1995006284 B1 WO 1995006284B1 US 9409386 W US9409386 W US 9409386W WO 9506284 B1 WO9506284 B1 WO 9506284B1
Authority
WO
WIPO (PCT)
Prior art keywords
state machine
data
read
host processor
write
Prior art date
Application number
PCT/US1994/009386
Other languages
English (en)
Other versions
WO1995006284A1 (fr
Filing date
Publication date
Priority claimed from US08/110,883 external-priority patent/US5465338A/en
Application filed filed Critical
Priority to EP94925958A priority Critical patent/EP0715735B9/fr
Priority to AT94925958T priority patent/ATE259515T1/de
Priority to DE69433548T priority patent/DE69433548D1/de
Priority to JP07507677A priority patent/JP3137293B2/ja
Publication of WO1995006284A1 publication Critical patent/WO1995006284A1/fr
Publication of WO1995006284B1 publication Critical patent/WO1995006284B1/fr

Links

Abstract

Dispositif d'interface ATA (fig. 5), à l'intérieur d'un système de mémorisation, servant à commander le transfert de secteurs de données entre un ordinateur central et un tampon (11) à l'intérieur du système de mémorisation en réponse à des commandes de lecture-écriture (READ-WRITE) émise par l'ordinateur central. Ledit dispositif (fig. 5) comprend un automate fini de comptage d'octets (4) servant à commander le transfert de secteurs de données entre l'ordinateur central et le tampon (11), un automate fini de mise à jour de fichiers de tâches (5) possédant un cycle machine servant à diminuer d'une unité le nombre de secteurs restant à transférer après le transfert d'un secteur par l'automate fini de comptage (4), un automate fini de lecture (6), servant à commander le traitement de la totalité des commandes de lecture (READ) émises par l'ordinateur central vers le système de mémorisation, un automate fini d'écriture (7) servant à commander le traitement de la totalité des commandes d'écriture (WRITE) émises par l'ordinateur central vers le système de mémorisation.
PCT/US1994/009386 1993-08-24 1994-08-22 Architecture d'interface ata utilisant des automates finis WO1995006284A1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP94925958A EP0715735B9 (fr) 1993-08-24 1994-08-22 Architecture d'interface ata utilisant des automates finis
AT94925958T ATE259515T1 (de) 1993-08-24 1994-08-22 Ata-schnittstellenarchitektur mit anwendung von zustandsmaschinen
DE69433548T DE69433548D1 (de) 1993-08-24 1994-08-22 Ata-schnittstellenarchitektur mit anwendung von zustandsmaschinen
JP07507677A JP3137293B2 (ja) 1993-08-24 1994-08-22 ステートマシンを利用するａｔａインターフェースアーキテクチャ

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/110,883 US5465338A (en) 1993-08-24 1993-08-24 Disk drive system interface architecture employing state machines
US110,883 1993-08-24

Publications (2)

Publication Number Publication Date
WO1995006284A1 WO1995006284A1 (fr) 1995-03-02
WO1995006284B1 true WO1995006284B1 (fr) 1995-04-20

Family

ID=22335437

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1994/009386 WO1995006284A1 (fr) 1993-08-24 1994-08-22 Architecture d'interface ata utilisant des automates finis

Country Status (6)

Country Link
US (1) US5465338A (fr)
EP (1) EP0715735B9 (fr)
JP (1) JP3137293B2 (fr)
AT (1) ATE259515T1 (fr)
DE (1) DE69433548D1 (fr)
WO (1) WO1995006284A1 (fr)

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