JPS61210464A - Data buffer device - Google Patents

Abstract

PURPOSE:To shorten access time and to enhance a responsiveness and a throughput of an entire of a system by setting and selecting a length of an optimum buffer memory block in accordance with a data transfer speed of I/O of an object. CONSTITUTION:All data inputted to a buffer memory block 8 in a data buffer device 2 through an I/O data bus 4 from an I/O 1 are transmitted to a CPU 3, and the data from the I/O 1 is written in a buffer memory block 9. At this time, the device 2 newly sets an output data of an initial address register 13 in buffer address counters 10, 11. The data from the I/O 1 is written in the memory 8 and the data in the memory 9 is transmitted to the CPU 3. A similar operation thereafter is repeated until all the receiving data from the I/O 1 is completed to be transmitted to the CPU 3. Thereby, an access time can be shortened and a responsiveness and a throughput of a system can be enhanced.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a data transfer method between a central processing unit and peripheral devices in a computer system, and in particular, to a method for buffering data transfer speed differences between the central processing unit and peripheral devices. Regarding the data buffer used.

[Background of the invention]

In the conventional alternating data buffering method, the entire buffer memory block is used as the buffer memory area, so if the data transfer rate of the target input/output device is semi-fixed (if it has multiple modes with different data transfer rates), the central Access time from the perspective of the processing device may become unnecessarily long. (For the central processing unit to start receiving data, at least one buffer memory block must complete receiving data from the input/output device.) [Object of the Invention] The object of the present invention is to The object of the present invention is to realize an alternating data buffer device in which the optimum access time t can be selected according to the transfer speed.

[Summary of the invention]

Access time (time taken for data from an input/output device to reach the central processing unit) in the alternating data buffering system
In order to shorten the time, it is sufficient to reduce the capacity of the buffer memory block.However, in order for the buffer device to achieve its original purpose, it is necessary to reduce the data transfer speed difference between the input/output device and the central processing. A sufficient number of buffer memory bytes is required, and the objective was realized by making it possible to select and set the actually used byte value of the buffer memory block that satisfies the above two conditions.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIGS. 1 and 2. In this embodiment, a case is shown in which data sent from an input/output device 1 is sent to a central processing unit 3. The data buffer device 2 has buffer memory blocks 8 and 9 that can sufficiently absorb the difference in data transfer speed between the input/output device 1 and the central processing unit 3.

An example of a circuit for realizing buffer memory block control of the data buffer device 2 is shown in FIG. 4 is an input/output device data bus that carries data from the input/output device, 8.9 is a buffer memory block that stores received data from the input/output device, and strobe signals of double lines 15 and 16 of equal capacity are provided, respectively. is stored in each buffer memory block 8.9. Reading data from the buffer memory blocks 8, 9 is taken out by the buffer memory output data bus 17.18,
7. One of the data buses of 18 is designated by the select line 19, and the data of the designated data bus is sent to the data buffer output data bus 5 via the selection circuit 12 and sent to the central processing unit 3. is sent. Here, the memory addresses of the buffer memory blocks 8.9 are designated by buffer memory address lines 26.27 carrying the data outputs of the respective buffer memory address counters 10.11. Buffered memory address counters 10, 11 transfer data on initial address register output line 23 to buffered memory address preset strobe lines 24, 25.
The initial count value is preset by the above strobe signal, and thereafter, the count up pulse input lines 21 and 22
The upper pulse signal increments the sear address by +1.

The count values of the buffer memory address counters 10 and 11 match the number of memory bytes of the respective buffer memory blocks 8 and 9 (each data bus 4 and 5 are 8-bit paths), and the last byte of the buffer memory block is accessed. After that, counters 10 and 11 are CARR indicating count over.
When the output lifeline 28 is in the active state, it is possible to detect that all the data in the allowable number of bytes has been accessed to the buffer memory block. The initial address register 13 is a register for storing which address in the buffer memory block to the final address is to be used as the actual buffer memory, and its setting data is placed on the initial address data line 14, and the initial address It is set in the initial address register 13 by a signal on the data set line.

The operation of the above circuit will be explained with a focus on the data buffer device 2t when receiving data sent from the input/output device 1 and transmitting it to the central processing unit 3.

Prior to data transfer, set the useful start address (1M!) of the buffer memory block in the initial address register, and set the output data of the initial address register in the buffer memory address counter lO. Data is written to the buffer memory address counter 1 at any time by a signal on the buffer memory write strobe line 15, and a pulse is applied to the count up pulse input line 21 every time one byte is written.
(1+1 is added. When data is written to the final address byte of the buffer memory block 8, the CARR, Y output line 2B becomes active, and the data buffer 2 registers the buffer memory address counter 10 and the IIK initial address register 13. After setting the output data, subsequent data from the input/output device 1 is written to the buffer memory block 9,
On the other hand, the data in the buffer memory block 8 is transferred to the selection circuit 12.
is selected and transmitted to the central processing unit 3 via the data buffer output data bus 5.

When all the data in the buffer memory block 8 has been transmitted to the central processing unit 3 and the received data from the input/output tj[x has been written to all the predetermined memory areas of the buffer memory block 9, the data buffer 2ri , new initial address register 13 is added to buffer memory address counter 10.11.
The data from the input/output device 1 is written to the buffer memory block 8, while the data in the buffer memory block 9 is selected by the selection circuit 12 and sent to the central processing via the data buffer output data bus 5. It is sent to device 3. Thereafter, similar operations are repeated until all received data from the input/output device 1 has been transmitted to the central processing unit 3.

According to the present invention, the optimum buffer memory block length is set in the initial address register 1 according to the data transfer speed of the input/output device.
3, the access time from the input/output device 1 to the central processing unit 3 can be controlled (shortened).

〔Effect of the invention〕

According to the present invention, it is possible to select and set the optimal buffer memory block length (number of buffer memory bytes actually used) according to the data transfer speed of the target input/output device, so access time can be reduced and the overall computer system Responsiveness and throughput can be improved.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the relationship between a data buffer, a central processing unit, and an input/output device, and FIG. 2 is a diagram showing an embodiment of buffer memory block control of the data buffer of the present invention. l...I/O device, 2...Data buffer device, 3...
・Central processing unit, 4...I/O device data bus, 5.
...Data buffer output data bus, 6...I/O device control line, 7...Data buffer control line, 8
, 9... Buffer memory block, 10.11... Buffer memory address counter, 12... Selection circuit, 13.
...Initial address register, 14...Initial Adnos data 2-in, 15, 16...Buffer memory write strobe line, 17.18...Buffer memory output data bus, 19...Select line, 20... - Initial address data set line, 21.22... Count up pulse input line, 23... Initial address register output line, 24.25... Buffer memory address preset strobe line, 26, 27... Buffer memory Address line, 28, 29...CAEl, BY output 1st country dormitory 20

Claims (1)

[Claims] 1. Two blocks of equal capacity data storage memory connected between the input/output device and the central processing unit (one block consists of two or more bytes; hereinafter referred to as "buffer memory block"). One buffer memory block receives data sent from an input/output device at any time, and when the data is received in all bytes of the buffer memory block, the data in the buffer memory block is transferred to the central processing unit. and continue to the other buffer memory block.
In so-called alternating data buffering, which receives data from an input/output device and then repeats the same operation,
Each buffer memory block has an initial address register for setting an initial address in an address counter that specifies the buffer memory address, and has means for writing arbitrary data (address) into the initial address register. A data buffering device characterized in that the alternating data buffering operation is executed in a buffer memory from an address set in an initial address register to a final address of the buffer memory.