JPH0237452A - Data transfer system for signal processing device - Google Patents

Abstract

PURPOSE:To shorten the processing time by designating address information in a proper period of a processor to read out data from a storage circuit in a prescribed period. CONSTITUTION:A processor 1 performs various processings and writes write data 6 in a storage circuit 4 by a write address signal 5 corresponding to the classification of data and a write indication signal 7. The processor 1 outputs address information 22, which consists of the start address of data to be read out from the storage circuit 4 and the number of transfer data, to an output control circuit 21 in a proper period. The processor 1 outputs an input indication signal 11 or an output indication signal 12 to an input/output device 10 to transfer input/output data 13 to /from the input/output device 10. The output control circuit 21 generates a read address signal 8 in order from the start address of address information 22 by the prescribed number of transfer data synchronously with a data output indication signal 3 from a timer 2. Thus, the processing time is shortened.

Description

[Detailed Description of the Invention] [Industrial Application Field 1] This invention relates to a data transfer method from a storage circuit in a signal processing device incorporating a processor [Prior art] Fig. 3 shows a conventional storage circuit. FIG. 2 is a block diagram showing a data transfer method from . In the figure, (1) is a processor that controls and processes the entire device, (2) is a timer that detects the data output timing, (3) is a data output instruction signal detected by timer (2), and (4) ) is a memory circuit that stores data, (5) is a write address signal for writing data to the memory circuit (4), and (6) is a processor (1).
The write data written from (7) is the processor (
1) is a write instruction signal; (8) is a read address signal that indicates the address to be read from the memory circuit (4);
(9) is the read data read out from the memory circuit, (1
0) is an input/output device controlled by the processor (1), and (11) is an input/output device (10) controlled by the processor (1).
), (12) is an output instruction signal from which processor α) instructs input/output device (1o) to output data, (13) represents processor α) and input/output device (10). This is data on the number of people during the period.

Next, the operation will be explained.

Processor 〇) performs various processes and sends the write address signal (5), write data (6), and write instruction signal (
7) and output to the memory circuit (4). Memory circuit (
4) is a write address signal (5) and a write instruction signal (7).
) Store write data (6) from K. on the timer)
The processor (1) sequentially counts the time, and when the time for data output comes, generates a guter output instruction signal (3), and the processor (1)
Output to. Based on the data output instruction signal (3), the processor (1) creates a read address signal (8) storing the corresponding data and outputs it to the storage circuit (4).

The storage circuit (4) reproduces data based on the read address signal (8) and outputs it as read data (9).

The input/output device (10) is a storage device (
After the transfer of the read address signal (8) to 4) is completed,
Human output data (13) is transferred in response to an input instruction signal (11) or an output instruction signal (12) from the processor (1).

[Problem to be Solved by the Invention 1] Since the conventional device for transferring data in a memory circuit is configured as described above, the processor can transfer data from the memory circuit to the input/output device or other devices. There were problems such as the need to wait for the transfer and the processing time.

This invention was made to solve the above-mentioned problems, and it reduces the processing time and allows the processor to perform other processing without being aware of when to start transferring data from the storage circuit. The purpose is to obtain a transfer method.

[Means for Solving the Problems j] The data transfer device from the storage circuit according to the present invention allows the processor to specify the start address and the number of data transfers for reading data from the storage circuit, so that the device can transfer data at a specified time regardless of the processing of the processor. In addition, a predetermined number of data can be read out from the memory circuit.

[Operation j] This invention allows the processor to instruct the output control circuit of the start address of data that needs to be output from the storage circuit and the number of data to be transferred at an appropriate time during processing, so that the output control circuit can respond to the output instruction from the timer. In synchronization, an address to be read from the memory circuit is created and read data is output.

[Example j An embodiment of the present invention will be described below with reference to the drawings.

In Figure 1, (1) is a processor that controls and processes the entire device, (2) is a timer that detects the data output timing, (3) is a data output instruction signal, and (4) stores various data. (5) is a write address signal for writing data, (6) is a processor (1)
), (7) is a write instruction signal, (8) is a read address for reading data from the memory circuit (4), (9) is read data from the memory circuit (4), (10) ) is an input/output device controlled by the processor (1), (11) is an input instruction signal that requests data from the processor (1) to the input/output device (10),
(12) is from the processor (1) to the input/output device (10)
(13) is the input/output data line between the input/output device (1O) and the processor (1), (21) is the data output instruction signal (3) from the timer (2). The read address signal of the storage circuit (4) (
(8) is the output control circuit that creates the output control circuit, (22) is the memory circuit (4)
) is address information specifying the start address of the data to be read and the number of data transfers, and (23) is a busy signal indicating that data is being output from the storage circuit (4).

The processor (1) performs various processes and writes write data (6) to the storage circuit (4) in response to a write address signal (5) and a write instruction signal (7) corresponding to the type of data. The processor (1) stores the memory circuit (
4), the output control circuit (
21). The processor (1) is an input/output device (
It outputs an input instruction signal (11) or an output instruction signal (12) to the input/output device (10) and transfers input/output data (13) to the input/output device (10). The output control circuit (21) synchronizes with the data output instruction signal (3) from the timer (2).
Read address signals (8) are created in order from the first address of address information 22) up to the specified number of data transfers.

Further, the output control circuit (21) outputs a busy signal (23) to the processor (1) so that data is not written to the memory circuit (4) while data is being output from the memory circuit (4).

The storage circuit (4) reproduces the read data (9) in response to the read address signal (8).

Although the above embodiment shows the case where data is read from the memory circuit (4) by specifying the address information (22) from the processor (1), it is also possible to write data from the outside to the memory circuit (4) as shown in FIG. As shown in Figure 3, adding the incoming control circuit and using the input instruction signal (32) from the timer (2),
The input control circuit (31) automatically selects the write address (33).
), write instruction signal (34) and external data transfer request (
39) can be generated and external input data (35) can be written. By importing external data (33) at any time, the processor (1)
〇 [Effects of the Invention] As described above, according to the present invention, if address information is specified to the processor at an appropriate time, data will be read from the memory circuit at the specified time. This configuration allows the processor to process regardless of the output timing, and has the effect of shortening processing time because processing can be performed in parallel.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing data transfer from a storage circuit according to one embodiment of the invention, FIG. 2 is a block diagram showing data transfer from a storage circuit according to another embodiment of the invention,
FIG. 3 is a block diagram showing data transfer from a conventional storage circuit. In the diagram, (1) is the processor and (2) is the tie?
-1 (3) is a data output instruction signal, (4) is a storage circuit,
(5) is a write address signal, (6) is write data,
(7) is a write instruction signal, (8) is a read address signal, (9) is read data, (10) is an input/output device, (1
1) is an input instruction signal, (12) is an output instruction signal, (13
) is the input/output data (21) is the output control circuit, (22) is the address information, (23) is the busy signal, -(31) is the input control circuit, (32) is the data input instruction signal, (33)
is an external data write address, (34) is an external data write instruction signal, (35) is external input data, (36) is an external data input completion signal, (37) is an external data read address, (38) is external data, (39) indicates an external data transfer request. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] It is characterized by reducing the load on the processor by being equipped with an output control circuit that automatically creates a read address by specifying the start address and number of data transfers from the processor and output instructions from the timer without going through the processor. A data transfer method for signal processing equipment.