JPS61206045A - Information processing system - Google Patents

Abstract

PURPOSE:To succeed the shared data without fail when one data processing device is abnormal while the shared data in the data processing system is maintained by stopping other system memory control device through the shared memory device. CONSTITUTION:When it is detected by the first data processing device that the second data processing device 22 is abnormal, the data concerning the second processing device 22 is read by the first processing device 21 from a memory part 15 in a shared memory device 1. At the time of succeeding, to maintain the data of the memory part 15, indication is executed by the command started by the first processing device from the first control device 41 to the shared memory device 1. Thus, the information is transferred between the shared memory device 1 and the second memory control device 42, the control of the second control device 42 is temporarily stopped, and while the first processing device 21 reads the data from the shared memory device 1, the abnormal writing is prevented from the second processing device 22 and thereafter, the processing can be succeeded at the shared memory device 1.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Field of Application) The present invention relates to a fault handling method in an information processing system in which data is shared by multi-theta data processing devices, and particularly relates to a failure handling method when a data processing device is abnormal. Concerning shared data maintenance methods.

(Prior art) Multiprocessor systems, that is, various systems that combine multiple data processing devices, have been proposed for the purpose of improving system reliability or performance. One form of such systems is a shared memory device. It is also common to construct systems using Because data is read from or written to the shared memory device arbitrarily, it is often difficult to determine the final state of the data.In such a system, if one of the data processing devices becomes abnormal, In this case, if the data being processed by the abnormal data processing device can be transferred to another data processing device and processing can be continued, the entire system will continue to operate without going down, and system reliability will increase. In addition, system operability can be increased.

For example, such technology was written by Mr. Ikuta and Mr. Takeyo, published in Information Processing Words, Volume 23, No. 1, pages 9 to 17, and published in 1982 in the book ``Large Mini Computer.'' Please refer to the paper entitled "Composite Computer System" by

However, in such techniques, the reliability of the shared data may be compromised unless the entire system is synchronized to read data from the shared memory device.

(Problem to be Solved by the Invention) For this reason, in various types of systems, data processing devices communicate closely with each other by performing host-to-host communication, and control write operations to a shared memory device. There is. However, the control of communication between hosts has the disadvantage that if the transfer capacity of the transmission line between data processing devices is reduced, the performance of the entire data processing system is reduced. communication between control programs of data processing equipment, communication between control programs of data processing equipment, and systems that require interrupt processing and message processing of control programs;
This has the disadvantage that the performance of the entire data processing system is degraded.

An object of the present invention is to provide a first data processing device and a second data processing device, which are connected to the first data processing device when the first data processing device reads data from a shared memory device. The shared memory device and the second
The above disadvantages are solved by transferring information between the memory control device connected to the second data processing device and stopping write requests from the second data processing device, thereby preserving the shared data in the data processing system. An object of the present invention is to provide an information processing system configured to efficiently perform the following operations.

(Means for Solving the Problems) An information processing system according to the present invention includes first and ga2 data processing devices, first and second main storage devices, and fi.
y, x, a second memory control device, and a shared memory device, the first data processing device and the second data processing device share the shared memory device at, and the second data processing device has an abnormality. When the first data processing device detects that the second data processing device is in the state, the data related to the second data processing device is read out by the first data processing device using a storage unit provided in the shared memory device, and the data is taken over. Sometimes, in order to preserve the data in the internal memory of the shared memory device,
Transfer of information between the υ shared memory device and the second memory control device by issuing instructions from the first memory control device to the shared memory control device based on a command activated by the data processing device. to temporarily stop the control of the second memory control device, prevent abnormal writing from the second data processing device while the first data processing device reads data from the shared memory device, and then The system is configured so that processing in the shared memory device can be taken over by the shared memory device.

The first memory control device is connected to the first data processing equipment and the first main storage device corresponding to the first data processing device, and is responsive to commands input from the first data processing device. It is primarily used to output or write data.

The second memory control device is connected to a second data processing device and a second main storage device corresponding to the second data processing device, and receives input from the first data processing device. It is used to read or write data based on commands.

The shared memory device is connected to the first and second memory control devices, and includes a pair of rounded input/output control units and a pair of input/output control units that transfer information between the first and second memory control devices. A pair of control buffer sections for storing information input from the output control section, a processing control section for analyzing the information stored in the pair of control buffer sections and instructing processing prescribed by the information, and processing. It consists of a storage section for holding data transferred between the first and second main storage devices via the first or second memory control section. .

(Example) Next, the present invention of VC1 will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of an information processing system according to the present invention, and is an actual example of a system that processes complex data using shared memory snowmaking. In FIG. 1, L is a shared memory device, 111 and 112 are first and second input/output control units, respectively, 12 is a processing control unit, and 1
31 and 132 are first and second control buffer sections, 14 is a storage control section, 15 is a storage section, 21.22 are first and second data processing devices, respectively, and 31 and 32 are first and second control buffer sections, respectively. 2 main storage devices, 41 and 42 are first and second memory control devices, 411 and 4, respectively.
21 are first and M2 data transfer control units, respectively;
412 and 422 are first and second command control units, respectively; 413 and 423 are first and second control register units, respectively; and 414 and 424 are first and second command control units, respectively.
and a second drive unit, 51 and 52 are first and second transmission lines, respectively.

In this embodiment, a pair of data processing devices @ 21 and 22 have one shared memory device tle, and the first and second main memories 31 and 22 are connected to each other via first and second memory control units @ 41 and 42, respectively. , 32 and the shared memory device 1.

In this system, the first data processing device 21
Data in the main memory 31JC is processed, and various table information is created in the first main memory 31 in connection with the processing.

When table information is created in the first main memory 31 or updated,
In order to preserve the data of the table information, the first data processing device 21 also stores the above creation table information or update table information in the shared memory device l. Its operation is below.

It is done as follows.

That is, when table information is created or updated on the first main memory 31 by the first data processing device 21, the storage location of the table information [t-address and the capacity of the table information are A block restorer consisting of the range shown is created on the first main memory 31, and the I(,)LD command is sent to the first memory controller
1 is running. FIG. 2 is an explanatory diagram showing an example of the structure of the block list.

In the first memory control device, the first command control unit 4
12 executes the processing of the 10LD command, stores the block list inputted with the 10LD command in the first control register 413, and then the first data processing device 21
The completion of the l0LD command processing is reported to. 4, the first data processing device 21 sends an I10 task command to start the first memory control device 41t, and based on the above block list, the first data processing device 21 sends an I10 task command to start the first memory control device 41t, and performs processing between the first main memory 31 and the shared memory device 1 based on the above block list. is requesting data transfer.

The I10 task command is analyzed by the command control unit 412 of the first memory control device 41, and the processing requested by the I10 task command is started.

If the I10 task command is a write request, the first command control unit 412 starts data transfer based on the block list stored in the first control register 413. At the same time, it controls the first drive unit 414 and transmits instructions to the shared memory device 1 and the block list of the first control register 413 to the shared memory device 1 via the first transmission path 51. .

In the shared memory device l, the first memory control device 41
The block list input from the first processing control unit 12
The signal is received by the first input/output control section 111 under the control of the control section 11, and is sent to the first control buffer section 131 and stored therein.

The first processing control section 12 instructs the storage control section 14IC to prepare for writing to the storage section 15 based on the instruction from the first memory control device 41 and the clock list of the first control buffer section 131. When the write preparation is completed, the processing control unit 12 permits the start of data transfer to the first memory control device 41 via the first transmission path 51. 1st
The first data transfer control unit 411 of the memory control device 41 of
reads the table information in the first main memory 31 according to the address and range value specified in the block list, and transmits it from the first drive unit 414 to the shared memory device l via the first transmission path 51. .

The first main memory 31 sent out via the first transmission path 51
The table information is temporarily stored in the second control buffer section 132 via the first input/output control section 111 of the shared memory device 1. Thereafter, the table information is stored in the storage section 15 under the control of the storage control section 14. When the storage control unit 14 detects completion of the write process to the storage unit 15, the storage control unit 14 notifies the processing control unit 12 of the detection result. The processing control unit 12 sends a completion signal to the first memory control device 41 via the first transmission path 51, and prepares for the next instruction.

When the data transfer by the first data transfer control section 411 in the first memory control device 41 is completed, the first data transfer control section 411 is deactivated.

Therefore, the first command control unit 412 waits for a completion signal from the first transmission line 51 and notifies the first data processing device 21 of the processed photons. In this embodiment, only write operations are executed regularly. The read process may be executed at regular intervals that are rounded off to verify the state of the storage unit 15 in the shared memory device l. However, if the data processing device of another system becomes abnormal, the table information is obtained from the shared memory device 1, and read processing is executed when the data processing device of the other system takes over the processing that was being executed. . In the read process as well, data transfer is defined by a block list similar to the write process.

When the first data processing device 21 becomes abnormal, the second data processing device 22 takes over the processing.

When taking over processing, the second data processing device 22 first sends a rounded message "rsTOP message" to prevent data writing due to malfunction of the first data processing device 21 and to guarantee table information in the storage unit 15 of the shared memory device 1. 2 on the main memory 32, and a block list related to the message information is created. Therefore, the second memory control device 4
Send the 10LD command to 2 to start it. The second command control unit 422 of the second memory control device 42 is l0L.
D command is executed, the block list is stored in the second control register 423, and the l is sent to the second data processing device 22.
Reports completion of 0LD command processing. Next, the second data processing device 22 sends an I10 task command as a communication request to start the second memory control device 42, and based on the block list, the “5TO” inside the second main memory 32 is
P message" to the first memory control device 41 of the other system. The I10 task command is processed using the same procedure as the I10 task command for write requests.
executed. In other words, “5” inside the second main memory 32
After storing the "TOP message" in the storage section 15 of the shared memory device l, the processing control section 12 instead of transmitting the completion signal to the second transmission path 52 sends the alternate top message,
It transmits a read signal to indicate to the second memory control device 42 that it is communicating with another system.

On the other hand, the processing control section 12 transmits a read request signal to the first transmission path 51, requesting the first memory control device 41 to read the message. The first command control unit 412 in the first memory control device 41KTh creates a block list on the first control register 413 based on the request from the first transmission path 51, and
The message is read out from the storage unit 15 at. The read message is stored in the first control register 413 via the first drive section 414. First command control unit 4
12 analyzes the message from the first control register 413 and performs processing based on the request. Upon receiving the "rSTOP message," the first command control section 412 sends an end signal to the first transmission path 51. Thereafter, all processing other than the initial setting request by the first data processing device 21 is stopped, and the first data processing device 21 waits for a 5TOP release instruction.

The processing control unit 12 in the shared memory device l waits for an end signal from the first transmission path 51 and sends a read request signal to the first transmission path 51 and a read request signal to the second transmission path 5.
2, and a completion signal is sent to the second transmission line 52 to notify completion of the I10 task command processing.

The second data processing device 22 sends the r8TOP message.
Upon completion of the transmission, the table information in the storage unit 15 transferred to the shared memory device 1 is read. l0LD in read processing
command and an I10 task command with a read request is activated.

The second memory control unit 422 starts processing based on the block list input in the 10LD command, enables the second data transfer control unit 421, and transfers the data to the second drive unit 424.
, and transmits instructions to the shared memory device 1 and the block list of the control register 423 to the shared memory device 1 via the second transmission path 52. The block list is received by the second input/output control unit 112 under the control of the processing control unit 12, and the block list is received by the second control buffer unit 13.
2 and stored. Based on the instruction from the second memory control device 42 and the block list in the second control buffer section 132, the processing control section 12 causes the storage control section 14 to read and prepare the storage section 15.

When read preparation is completed, the processing control unit 12 notifies the second memory control device 42 via the second transmission path 52 of the start of data transfer.

The storage control unit 14 reads table information from the storage unit Is, and transmits the table information to the second memory control device 42 via the first input/output control unit 112.

According to the address and range value specified by the block list, the second data transfer control unit 421 stores the table information input from the second transmission path 52 into the second main memory 32. The storage unit 15 is controlled by the storage control unit 14.
When the completion of reading is detected, this signal is notified to the processing control unit 12. The processing control unit 12 transmits a completion signal to the second memory control device 42 via the second transmission line 52Vc and prepares for the next instruction.

When the second data transfer control unit 421 in the second memory control device 42 completes data transfer, the second command control unit 422 deactivates the second data transfer control unit 421 and transfers the second data. The processing device 22 is notified of the completion of the processing. The second data processing device 22 is rREsTA
RT message" on the second main memory 32, and
The first message of the other system is sent using the same procedure as sending the OP message.
A message is sent to the memory control device 41 of the memory controller 41 to instruct it to restart processing.

FIG. 3 is an operation flowchart showing the takeover operation as a flowchart. That is, this figure is a flowchart showing the operation of the memory control device in the abnormal system, the operation of the memory control device in the alternative system that takes over the processing, and the operation of the shared memory unit, respectively.

(Effects of the Invention) As explained above, the present invention is advantageous in stopping the memory control device of another system via the shared memory device, and in order to protect the data stored in the shared memory as shown in FIG. This has the effect that the shared data of the shared memory device can be more reliably taken over even when the data processing device is in an abnormal state, and the reliability of the composite data processing system can be improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of an information processing system according to the present invention. FIG. 2 is an explanatory diagram showing an example of the structure of a block list related to the data processing device shown in FIG. 1. FIG. 3 is a flowchart showing the flow of processing when processing is taken over in the information processing system shown in FIG. l... Shared memory device 111.112... Input/output control section 12... Processing control section 131, 132... Control buffer section 14... Storage control section 15... Storage section 21.2
2...Data processing device 31.32...Main storage device 41.42...Memory control device 411.421...Data transfer control unit 412.422
... Command control section 413.423 ... Control register section 414.424 ... Drive section 51.52 - ... Transmission line patent issuer NEC Corporation agent Patent attorney Hisashi Inoro Figure 22

Claims (1)

[Claims] first and second data processing devices, first and second main storage devices corresponding to the first and second data processing devices, the first data processing device and the first main storage device a first memory control device connected to said first data processing device for reading or writing data based on a command input from said first data processing device; and said second data processing device and reading data based on a command input from the second data processing device, which is connected to the second main storage device;
or a second memory control device for writing;
a pair of input/output control units connected to the first and second memory control devices for transferring information between the first and second memory control devices; a pair of input/output control units; a pair of control buffer units for storing the information inputted from the control buffer unit, and a processing control unit for analyzing the information stored in the pair of control buffer units and instructing a process defined by the information. for holding data transferred to and from the first or second main storage device via the first or second memory control device based on instructions from the processing control section and the processing control section. a shared memory device comprising a storage unit, the first data processing device and the second data processing device share the shared memory device, and the second data processing device is in an abnormal state. is detected by the first data processing device, the first data processing device reads data related to the second data processing device from the storage section, and at the time of handover, the data related to the second data processing device is read out from the storage section. In order to preserve the data,
transfer of information between the shared memory device and the second memory control device by issuing an instruction from the first memory control device to the shared memory device based on a command activated by a data processing device; and temporarily stop the control of the second memory control device, and while the first data processing device is reading data from the shared memory device, an abnormal write is performed from the second data processing device. 1. An information processing system characterized in that the information processing system is configured such that the shared memory device can take over the processing after that.