KR20020033254A - Apparatus and method for flow control in dual processor system - Google Patents

Abstract

PURPOSE: An apparatus and method for controlling the flow of a dual processor is provided to simply control processes by controlling a dual flow according to a state of a dual FIFO using a bus intermediation function between a CPU and a dual control unit. CONSTITUTION: Processors(31, 41) are operated as the active or the stand-by mode. Memories(32, 42) store data to which the processors(31, 41) access. Dual control units(33, 43) transmit information on data an active processor among the processors(31, 41) stores in the memories(32, 42) to dual FIFOs(First-In First-Out)(34, 44). In addition, the dual control units(33, 43) occupy or release a system bus according to a level of each dual FIFOs(34, 44). The dual FIFOs(34, 44) store data the active processor(31) stores data in the relevant memory(32) according to information transmitted from the dual control units(33, 43). After that, the dual FIFOs(34, 44) transmit the data to dual FIFO(44) of the stand-by processor(41) through a dual channel.

Description

{Apparatus and method for flow control in dual processor system}

The present invention relates to redundancy flow control of a redundant processor, and in particular, to overcome the problems of the prior art according to the operating system-level software control by an interrupt method, by using a bus arbitration function between a central processing unit (CPU) and a redundancy control unit. The present invention relates to a flow control device of a redundant processor through bus arbitration and a method of operating the same, which are suitable for simplifying a control procedure by performing a redundant flow control according to the state of a first-in first-out (FIFO) at a hardware level.

In general, processor redundancy is active / standby. Thus, the active processor is configured to simultaneously store newly updated data in its main memory, not only in its own memory but also in the standby processor side memory.

As such, the redundant processors maintain memory coherence with each other. This case is called duplication by the concurrent write method between the two processors.

In order to implement redundancy based on concurrent writes in a plurality of processor boards, each board must include a processor matching unit, a main memory unit, a redundant control unit, and a redundant FIFO.

According to the concurrent write method, the FIFO queue is used as a redundancy channel when updating the value written to the main memory by the active processor to the same value at the same address in the standby memory. At this time, in order to reduce the constraints on the standby processor state to the minimum when the active processor operates, the active processor continues to write to the memory unless the active redundant FIFO is full.

However, in the standby side, since the standby processor and the redundancy control unit share a bus to access memory, if the standby processor continuously accesses the memory, the redundancy data transmitted from the active board side is interrupted because the access of the redundancy control unit is interrupted. Update to the memory on the standby board side becomes slow.

Therefore, the amount of data waiting in the redundant FIFO on the active board side may increase, causing the redundant FIFO to become full. In this case, since the active processor can no longer transfer the data written to the main memory to the standby processor side, the active processor is notified that the state of the current redundant FIFO is full and until the full state is cleared. This will limit the interruption of the write process.

This operation results in a redundant control flow.

Hereinafter, the prior art of the redundant flow control of the redundant processor in contrast to the present invention.

First, Figure 1 is a block diagram of a redundant flow control apparatus of a redundant processor according to the prior art.

As shown in FIG. 1, the conventional apparatus is composed of two processor boards connected by redundant channels. Each processor board includes a processor (11, 21); Memories 12 and 22; It is comprised of the duplication control part 13 and 23 and the duplication FIFO 14 and 24.

In this configuration, the operation of writing data to the memory 12 by the processor 11 of the active board is sensed by the redundancy control unit 13. The duplication control unit 13 writes the address and data of the memory written by the processor 11 to the duplication FIFO 14.

The information in the redundant FIFO 14 of the active board is transmitted to the redundant FIFO 24 of the standby board through the redundant channel and sensed by the corresponding redundant control unit 23.

In the standby board, the information detected by the redundancy control unit 23 is written to the memory 22 after passing through the processor 21 and the bus.

The information updated in the main memory 12 of the active board in the above-described scheme is stored in the memory 22 of the standby board, thereby maintaining the sameness of the storage contents of the active board and each memory in the standby board.

However, in the above scheme, when the redundant FIFO 14 of the active board is full, the information about the update of the memory 12 may not be stored in the redundant FIFO 14, and as a result, may be transmitted to the standby board. There will be no. The identity between the memories 12 and 22 of the two boards is no longer maintained.

As described above, the loss of identity between the memory boards 12 and 22 between two boards is a significant factor causing dual down.

In order to prevent the above problem, the redundancy control unit 13 of the active board monitors the state of the redundant FIFOs 14 and 24 of both boards. That is, the generation of AFF (Almost FIFO Full), which is a flag indicating that the queue is almost full, among the flags of each redundant FIFO 14 (24) is monitored. Thus, if an AFF flag is generated in any of the two redundant FIFOs 14 and 24, an interrupt is notified to the processor 11 of the board.

Upon receiving the interrupt, the processor 11 requests interpretation of the operating system for the interrupt. The operating system should include a series of interrupt processing routines for stopping the write operation to the memory 12 of the processor 11 for the redundant flow control when the above-mentioned interrupt occurs.

At this time, the interrupt is processed by the operating system requires software programming in the application layer, and programming in such an application layer is generally system dependent. In other words, such an interrupt processing routine is not easy to port from one system to another.

In this way, the operating system that handled the interrupt controls the operation of the processor 11. When the interrupt is received from the duplication control unit 14, the full level of the duplication FIFO 14 and 24 must be prevented. Will abort the memory write operation.

The processor 11 which has stopped writing to the memory monitors the state of the redundant FIFOs 14 and 24 through flags (AAF, EF, HEF, etc.) coming into the register of the redundant control unit 13. The processor 11 performing the monitoring operation notifies that the state of the redundant FIFOs 14 and 24 is changed to notify that the queue is empty or that the queue is about half empty. Checking the flag, HEF (Half Empty Flag), will continue the aborted memory write operation.

Referring to FIG. 2, a more specific flow of control operations will be described. First, the processor 11 of the active board writes to the memory 12.

The duplication control unit 13 monitors the operation and writes the data DATA1 to the duplication FIFO 14 of the board if the data DATA1 written to the memory is to be transmitted to the standby board.

Information accumulated in the redundant FIFO 14 is transmitted to the redundant FIFO 24 of the standby board through the redundant channel. Thus, the information received by the standby board is stored in the memory 24 by the redundancy control unit 23 of the board.

Concurrent write operations are performed in the above steps, and when the high level state of the redundant FIFO is induced during the repetitive execution of these operations, flow control is performed in the following steps.

When either of the redundant FIFOs 14 and 24 outputs the AFF flag, the redundancy control unit 13 of the active board detects this and notifies the processor 11 of the corresponding board of the interrupt.

The processor 11 receiving the interrupt stops writing to the memory 12 under the control of the operating system because the redundant FIFOs 14 and 24 are full. The processor 11 then periodically reads the flag register in the redundancy control section 13 to check the status of the redundancy FIFOs 14 and 24.

When a state change of the redundant FIFOs 14 and 24 occurs and the EF or HEF flag is read from a register in the redundant control unit 13, the processor 11 resumes the interrupted memory write operation.

However, in the prior art described above, when the redundant FIFO is full, the processor of the active board must limit the memory write operation. The limited state for the memory write operation is until the state of the redundant FIFO with the AFF flag is changed to EF or HEF. Maintained continuously.

At this time, the restriction and release of the memory write operation are handled by the operating system using a CPU interrupt. Since such a program is generally low in portability, it is difficult to apply to a general-purpose operating system.

When the processor goes to the interrupt service routine, some time difference occurs. During this time, when the write operation to the redundant FIFO continues and the redundant FIFO reaches the full level, the standby side can update the data updated on the active side. There was also a problem that the memory identity is lost.

Therefore, if any one of the two redundant FIFOs is full, the memory identity between the two processor boards will not be achieved, and if the redundant switch between the active board and the standby board is made in this state, the standby processor will not function properly as the active processor. do.

In this case, all of the redundant processor boards cause a dual down operation, which is a serious problem in the operation of the redundant processor.

Accordingly, the present invention has been proposed to solve the above conventional problems, and an object of the present invention is to solve the problems of the prior art according to the software control of the operating system level by the interrupt method in the redundant flow control of the redundant processor. To overcome this problem, the bus arbitration function between the central processing unit (CPU) and the redundancy control unit is used to perform redundant flow control according to the state of the redundant first-in first-out (FIFO) to simplify the control procedure. The present invention provides a flow control apparatus for a redundant processor and a method of operating the same.

In order to achieve the above object, a flow control apparatus of a redundant processor through bus arbitration according to the present invention includes a processor operating in an active or standby mode; A memory for storing data accessed by the processor; A redundancy control unit which transfers information about data stored in the memory by an active processor among the processors to a redundant FIFO, and occupies a system bus or releases an occupation of the system bus according to the level of each redundant FIFO; The active processor stores data stored in the corresponding memory according to the information transmitted by the redundancy control unit, and transfers the data stored in the corresponding memory to the redundant FIFO on the standby processor side and sends a flag indicating the level of each FIFO. The technical configuration is characterized by consisting of a redundant FIFO delivered to the redundant control unit.

In addition, in order to achieve the above object, the operation method of the flow control apparatus of the redundant processor through the bus arbitration according to the present invention, in the redundant processor board transfers the information written to the memory by the processor of the active board through the redundant channel Maintaining identity between memories; The technical configuration features that the redundancy controller of the active board performs the steps of occupying and releasing the system bus according to the level of redundancy FIFO of each board when exchanging information to maintain the sameness between memories.

1 is a block diagram of a redundant flow control apparatus of a redundant processor according to the prior art,

2 is a block diagram of an apparatus for controlling a flow of a redundant processor through bus arbitration according to an embodiment of the present invention;

3 is a flowchart illustrating a method of operating a flow control apparatus of a redundant processor through bus arbitration applied to FIG. 2.

Hereinafter, the configuration and operation of the present invention will be described in detail according to an embodiment according to the technical idea of the flow control apparatus and the operation method of the redundant processor through the bus arbitration as described above.

First, FIG. 2 is a block diagram of a flow control apparatus of a redundant processor through bus arbitration according to an embodiment of the present invention, and FIG. 3 is a method of operating the flow control apparatus of a redundant processor through bus arbitration applied to FIG. It is a flow chart.

As shown in FIG. 2, a suitable embodiment of the apparatus proposed by the present invention is composed of two processor boards connected in a redundant channel, each processor board comprising: processors 31 and 41 operating in an active or standby mode; ; Memory (32, 42) for storing data accessed by the processor (31, 41); The active processor among the processors 31 and 41 transmits information about data stored in the memories 32 and 42 to the redundant FIFOs 34 and 44 and according to the level of each of the redundant FIFOs 34 and 44. A redundancy control unit (33, 43) for occupying or releasing the system bus; The data stored in the memory 32 by the active processor 31 is stored in the memory 32 according to the information transmitted by the redundancy control units 33 and 43, and then transferred to the redundant FIFO 44 on the standby processor side through the redundancy channel. And redundancy FIFOs 34 and 44 which transmit flags (AFF, EF, HEF, etc.) indicating the level of each FIFO to the redundancy control unit 33 of the active board.

As shown in FIG. 3, a suitable embodiment of the method proposed by the present invention may include transmitting information written in a memory of a processor of an active board to a memory through a redundant channel in a redundant processor board (ST11). ST13); If the AFF flag of the redundant FIFO is output during the information exchange to maintain the sameness between memories, the redundancy control unit of the active board receives the bus occupancy rights from the processor of the board and maintains the flag until the flag of the redundant FIFO becomes EF or HEF. Perform (ST14 ~ ST18).

The operation of the method configured as described above is as follows.

The system to which the present invention shown in FIG. 3 is applied is a redundant processor board as in the prior art.

The present invention performs not only the detection of the full state of the redundant FIFO 34 (44) but also a series of control operations including memory write restriction and release of the processor without the involvement of the operating system. That is, by allowing the redundancy control unit to control the operation of the redundant processor in the hardware layer by using the bus arbitration function, the redundancy flow control can be completed in the hardware layer.

At this time, the processors 31 and 41 and the redundancy control unit 33 and 43 access the memory 32 and 42 through one system bus, and two buses (processor and redundancy control unit) are connected to one bus. Since it is necessary to access the bus arbitration function between each entity.

Therefore, each entity occupies and uses the bus only if it requests a bus request (BR) and receives a response from the other party (BG).

As such, two objects (processor and redundancy control unit) capable of accessing and reading / writing memory share memory through the bus arbitration function.

As shown in FIG. 2, the present invention controls the operation of the processor using this bus arbitration function.

That is, when the redundancy control unit 33 of the active board detects the Alf FIFO Full (AFF) flag of the redundancy FIFOs 34 and 44, the redundancy control unit 33 requests (BR) the bus occupancy right from the processor 31. Receive the response (BG) and occupy the bus.

The redundancy control unit 33 occupying the bus does not pass the bus occupancy right to the processor 31 until the state of the redundancy FIFO 34 is at a level defined by EF (Empty Flag) or HEF (Half Empty Flag). Then, since the processor 31 cannot occupy the bus until the water level of the redundant FIFO 34 is lowered to an appropriate position, the write operation to the memory 32 is not performed, so that the information stored in the redundant FIFO 34 is further reduced. It will not increase any more.

The write restriction on the redundant FIFO 34 is a condition sufficient to reduce the information stored in the corresponding FIFO queue.

The operation flow of the redundant flow control apparatus will be described in more detail with reference to FIG. 3.

First, the operation of writing to the memory 32 by the processor 31 of the active board in order to maintain the same memory between the respective processor boards is monitored by the duplication control unit 33 (ST11).

If the data DATA1 to be written to the memory to monitor the operation to be transmitted to the standby board, the redundancy control unit 33 writes the data DATA1 to the redundant FIFO 34 of the board (ST12).

Information accumulated in the redundant FIFO 34 is transmitted to the redundant FIFO 44 of the standby board through the redundant channel. Thus, the information received by the standby board is stored in the memory 44 by the redundancy control unit 43 of the board (ST13).

A concurrent write operation is performed in the above step, and when AFF of the redundant FIFOs 34 and 44 is generated during the repetitive execution of the operation, flow control is performed in the following step.

When either of the redundant FIFOs 34 and 44 outputs the AFF flag, the redundant control unit 33 of the active board detects this (ST14).

Thus, the redundancy control unit 33 that detects the AFF flag requests the bus occupancy right for the processor 31 (ST15). The request for bus occupancy (BR) to the processor is implemented by the bus arbitration function and the response (BG) is as described above.

That is, the redundancy control unit 33 on the active processor side occupies the bus by using an arbitration function for the system bus shared between the processors 31 and 41 and the redundancy control units 33 and 43 (ST16).

The redundancy control unit 33 on the active processor side occupying the system bus periodically detects a flag indicating the level of each redundancy FIFO 34, 44 (ST17).

When both the redundant FIFOs 34 and 44 transmit the EF or HEF flags, the level of the FIFO is lowered, so the redundancy control unit 33 on the active processor side gives the bus occupancy right to the active processor 31 (ST18). .

As described above, the present invention is not limited to using an interrupt service routine at the operating system level in limiting memory access of the processor 31, but is completely implemented using a bus mediation function for controlling operation between hardware. This eliminates the need for separate software programming.

Upon receiving the bus occupancy right request BR of the redundancy control unit 33, the processor 31 transfers the bus occupancy right to the redundancy control unit 33 after finishing the work being performed. At this time, the operation of handing over the bus occupancy right is made as a response (BG) to the occupancy request BR.

Upon receiving the response BG, the redundancy control unit 33 occupies the bus.

The redundancy control unit 33 occupying the bus checks the state of the redundancy FIFOs 34 and 44 through the status flags AAF, EF, and HEF arriving at the registers, and the level is below a certain level (EF or HEF). Stay in the bus until you get down.

Thus, if the status flag of the redundant FIFOs 34 and 44 is EF or HEF, the redundant control unit 33 passes the bus occupancy right to the processor 31.

Processor 31 then takes over the bus and resumes the interrupted memory write operation.

As described above, the present invention can control the duplication flow between two processor boards in a system that is redundantly operated in a concurrent write method using a bus mediation function without a separate software processing routine.

Although the preferred embodiment of the present invention has been described above, the present invention may use various changes, modifications, and equivalents. It is clear that the present invention can be applied in the same manner by appropriately modifying the above embodiments. Accordingly, the above description does not limit the scope of the invention as defined by the limitations of the following claims.

As described above, the apparatus for controlling the flow of the redundant processor through the bus arbitration and the operating method thereof according to the present invention provide a redundant flow control that does not cause the full state of the redundant FIFO by using the bus arbitration at the hardware level. By doing so, it is possible to overcome the disadvantage of requiring a separate interrupt processing routine, thereby simplifying the control procedure.

And unlike the prior art using the interrupt to the processor, the time difference does not occur according to the invocation of the interrupt processing routine, so that the high water level state of the redundant FIFO is generated by performing the flow control immediately according to the flag indicating the high water level possibility of the redundant FIFO. There is an effect that can block the possibility more firmly.

In addition, the memory write limit and release operations of the processor can be completely processed at the hardware level, so that no special software processing is required in the redundant flow control, so that the limitations of the portability of the program can be overcome and applied to a general-purpose operating system. There is also an effect.

Claims (2)

In the case where a plurality of processor boards connected in a redundant channel constitutes a redundant system, each processor board is A processor operating in an active or standby mode; A memory for storing data accessed by the processor; A redundancy control unit which transfers information about data stored in the memory by an active processor among the processors to a redundant FIFO, and occupies a system bus or releases an occupation of the system bus according to the level of each redundant FIFO; The active processor stores data stored in the corresponding memory according to the information transmitted by the redundancy control unit, and transfers the data stored in the corresponding memory to the redundant FIFO on the standby processor side and sends a flag indicating the level of each FIFO. Flow control apparatus of the redundant processor, characterized in that it comprises a redundant FIFO delivered to the redundant control unit. Maintaining the duplicated board-to-board memory identity by storing data according to the transmitted information in a memory of a standby board when the processor of the active board transmits the information written in the memory through the duplication channel; Controlling the operation of the processor of the active board to write to the memory by occupying or releasing a system bus according to the level of the redundant FIFO of each board when exchanging information for maintaining the same memory; Flow control method of a redundant processor, characterized in that.