JPH0324634A - Double system device - Google Patents

Abstract

PURPOSE:To remarkably reduce the shock to an I/O device by providing exter nal memories between respective computers in a double system through an IF cable and controlling required processing such as the accumulation of source data, source addresses and module execution information and their transfer periods. CONSTITUTION:Each of respective memories 7, 8 connected to each other through the IF cable monitors an abnormal signal outputted from the computer 1 or 2, applies an operation command to the normal computer 1 e.g. and switches an I/O bus switch 5 so that the computers 1, 2 are respectively used as a practical working system and a stand-by system. Then the source data, source address and module execution information are stored in the memory 8 through the memory 7, and at the time of detecting a module end, the stored data are transferred to a main memory in the computer system 2 in a paving system. Since the module execution information can be transferred as switching information while holding the synchronism of data, the double system device capable of remarkably reducing the shock to the I/O device can be obtained.

Description

[Detailed Description of the Invention] [Field of Industrial Application] This invention provides a dual-system system in which a main system and a standby system control a common input/output device using redundant computers to execute actual work processing. This is related to equipment. [Prior Art] Figure 8 is a conceptual diagram showing a conventional dual system device disclosed in, for example, Japanese Patent Publication No. 1809/1983.
In the figure, 1 and 2 are computers that are duplicated into a main system and a standby system, and 3 is connected to these computers 1 and 2 by a memory bus, a monitoring signal line, a control signal line, etc., and monitors and controls their operations. This is a redundant control device. 41
and 42 are input/output buses of the computer 1 or 2, respectively, and 5 is an input/output bus switcher for switching between the input/output buses 4l and 42 under the control of the redundant control device 3. 6 is a calculator! and 2, and the connection to the input/output bus 41, 42 is switched by the switch 5. FIG. 9 is a block diagram showing the detailed connection relationship between the computer 1.2 and the redundant control device 3, focusing on memory transfer. In order to avoid complexity, Figure 9 only shows the structure of memory transfer from computer l to calculation [2] when computer 1 is the main system and computer 2 is the standby system. The memory transfer system to computer 1 has the same structure. In the figure, l1 and 2l are the processors of computer 1 or 2, and l2 and 22 are the processors of computer l or 2.
This is the main memory of 31 has a built-in first-in first-out memory (hereinafter referred to as FIFO),
This is an address monitor unit that intercepts the address when the processor 11 accesses the main memory l2. 3
2 is a monitoring unit that monitors the data ready signal from this address monitor unit 31 and the ready signals from computers 1 and 2, and 33 is a database etc. that performs equalization of the database according to the fifJJ control signal from this monitoring unit 32. The digitizing section 34 is a database copying section that also copies the database according to the control signal from the monitoring section 32. 35 is a FIFO overflow detection unit that detects an overflow of the FIFO in the address monitor unit 3l. Next, we will explain the operation. The duplex control device 3 determines the wandering behavior of the duplex computers 1 and 2, gives an input/output bus use permission signal to one of the normal computers, for example, computer 1, and switches the input/output bus switch 5 to the computer. Switch to the l side. In this way, the computer 1 to which the input/output bus use permission signal has been given engages in actual work as the main system, while the other computer 2 stands by as the standby system.
When the main computer l that has started processing the actual work executes a write access to its main memory 12, the address monitor unit 3l of the redundant control device 3 intercepts the address at that time and sends an equalization request signal. When an address is received, it is stored in the built-in FIFO. The monitoring section 32 monitors the ready signal of the computer 1.2 and the data ready signal of the address monitor section 3l, and controls the operations of the database equalization section 33 and the database copying section 34. The database equalization unit 33 reads out the main memory 12 of the computer 1 according to the control signal of the monitoring unit 32 and the address given from the FIFO of the address monitoring unit 31, and writes the read data to the same address of the main memory 22 of the computer 2. Enter.
As a result, the data requested by computer 1 is transferred to computer 2 and equalized. At this time, the FIFO of the address monitor section 31 buffers the timing difference between the main memory access of the computer 1 and the equalization operation of the duplex control device 3. The equalization request by the computer l is issued when the computer l writes certain data in the database in the main memory 12. This type of data can be obtained using Calculator 1.2
It is considered to be data that is commonly used when performing actual work. Therefore, each time this type of shared data changes due to writing by computer 1, the changed data is transferred to the database of computer 2. On the other hand, the database copying section 34 writes all the databases in the main memory 12 of the computer 1 to the computer 2 according to the control signal from the monitoring section 32. The operation of the database copying unit 34 is mainly performed as one of the initialization tasks for the computer 2 when the computer 2 is put into a dual system. The database equalization section 33 and the database copying section 34 can operate in parallel. Therefore, when computer l rewrites shared data during database copying, equalization is performed on that data each time. The FIFO overflow detection unit 35 detects that a new equalization request has occurred while the FIFO of the address monitor unit 3l has been filled with addresses to be equalized according to the equalization request that occurred previously. , that is, detects FIFO overflow. On average, the operation speed of the database equalization unit is sufficiently faster than the frequency of equalization requests of computer 1, but momentarily, the frequency of equalization requests exceeds the processing speed of equalization operations. In this case, FIFO acts as a buffer. FI
There is no problem if the FO capacity is sufficient, but in reality it is limited, so when the frequency of equalization requests becomes extremely high, the above-mentioned FIFO overflow may occur. As soon as the status is detected, the monitoring unit 32 is notified. Upon receiving this notification, the monitoring unit 32 once resets the FIFO and initializes it to an empty state, and then transfers the FIFO to the database copying unit 3.
4 and transfer the entire database of computer l to computer 2. This guarantees a match even for addresses that cannot be equalized due to FIFO overflow. In this operation as well, the database equalization section 33 starts operating again at the same time as the database copying section 34 is activated, and operates in parallel with the entire database transcription. here,
In program execution, when one function is realized by multiple programs, the collection of those programs is called a module, and it is necessary to maintain data synchronization while executing within this module. It would be a problem if the data in the main memory l2 (hereinafter referred to as source data) in the computer 1 that is running is changed other than in the program. In process control, where processing is realized by a collection of multiple modules, when considering switching in a redundant system,
The synchronization of this source data is a particular problem.4. In addition, in recent years, the processing of this module has also been changed to multitasking OS.
(operating system), the processor 11.
The execution of processing in 21 is no longer a series. Figure 10 is a time chart for explaining the flow of such processing. When a request for the processing of module 8 occurs, its execution begins. If a request for processing of module B occurs while module A is being executed, the execution of module A is temporarily interrupted and enters a waiting period, and execution of module B is started instead. When the execution of module B is completed, the execution of module A that was waiting is resumed. Here, when module B is not a module that is started according to the conditions of module A, and a switch occurs from main computer 1 to standby computer 2, computer 2 will not be able to restart processing as shown in Figure 10. a. b
, c) It is necessary to know in which state the switching occurred, and module execution information that represents the execution state of the module is essential. [Problem to be solved by the invention] Since the conventional dual system device is configured as described above, when there is a change in the source data, it is immediately transferred to the standby system computer 2. If switching occurs in the middle of module processing, data synchronization cannot be maintained unless the start addresses after switching are completely consecutive, and since there is no module execution information, the main memory l1 and 2l Even if the data match, there were problems such as the standby computer 2 not knowing where to start executing the program again. This invention was made to solve the problems mentioned above.
The purpose of this paper is to obtain a duplex system device that can smoothly switch between duplex systems by passing module execution information as switching information while maintaining data synchronization. [Means for Solving the Problems] The dual system device according to the first claim writes source data information, source address information, and transmitting means for sending information such as module execution information to an external bus, and when the system becomes a standby system, it detects the module end from the module execution information received from the external bus, and sends the information stored in the external memory to the main system. Each computer is provided with a processor having a transfer means for transferring the information onto the memory, and a backup memory and a main computer are connected to each other by an interface (hereinafter referred to as I/F) cable and store the information from the main computer. a transmission means for receiving the information sent from the system computer to the external bus and transmitting it to the other party's external memory; a transfer means for transmitting the information stored in the backup memory to the standby computer via the external bus; a redundancy execution determination circuit that monitors an abnormal signal from a control signal line, determines which of the computers should be made the main system, and generates a switching signal that selectively operates the backup memory and the receiving means or the transmitting means; This is an external memory equipped with an external memory placed between redundant computers. The dual system device according to the second claim is characterized in that the external memory includes the save memory, the transmitting means, the receiving means, the transferring means,
In addition to the redundancy execution determination circuit, a latch circuit that once latches the source address information received by the receiving means and sends it to the save memory together with the source data information, and an address generation circuit that generates an address for the save memory. It is. A duplex system device according to a third aspect of the present invention is characterized in that the external memory includes a source received from the main computer in addition to the save memory, the receiving means, the transfer means, the address generation circuit, and the duplex execution determination circuit. A save memory that stores address information, a latch circuit that sends the source data information received from the main computer to the save memory, and a microprocessor that executes transcription control at the module end timing detected from the module execution information in the save memory. and a transmission means for transmitting information from the save memory to the external memory of the other party. [Operation] The dual system device in the first claim rearranges the external memories interconnected by I/F cables between the computers in the dual system, so that the main computer can read source data. When updating, the source address and module execution information along with the source data are temporarily stored in an external memory connected to the standby computer, and when the module execution information from the main computer reaches the module end, the source address and module execution information are stored in the external memory. By transferring the information stored in the computer to the main memory of the standby computer, we provide a dual-system device that causes extremely little shock to input/output devices. The dual system device according to the second aspect of the invention stores the information from the main computer in an external memory connected to the standby computer by once latching the source address information. The input/output device is stored as data in external memory, and when the module execution information from the main computer reaches the end of the module, the information stored in external memory is transferred to the main memory of the standby computer. We provide Schick's extremely small dual-system device for this purpose. In the dual system device according to the third claim, when the main computer updates source data, the information is temporarily stored in an external memory connected to the main computer, and the information is read from the main computer. When the module execution information reaches the module end, the information accumulated in the external memory connected to the main computer is transferred to the main memory of the standby computer via the external memory connected to the standby computer. This provides an extremely small dual-system device for input/output devices. [Example] An example of the present invention will be described below with reference to the drawings. 1st
In the figure, 1.2 is a duplicated computer, 41.42
5 is the input/output bus, 5 is the input/output bus switch, and 6 is the input/output device, which are the same as those with the same symbols in FIG. 8.
Or a considerable portion. Further, 7 and 8 are external memories connected to each other by an I/F cable and connected to the computer 1 or 2 by an external bus (address bus, data path) and a control signal line (operation command, abnormal signal). Yes, it monitors the abnormal signals of computer 1 and computer 2 to determine which one should be the main system, and sends an input/output bus use permission signal to the computer determined to be the main system, and also sends an input/output bus use permission signal to the computer determined to be the main system.
It controls the input/output bus switch 5 to connect the computer to the input/output bus of the computer, and also controls the transfer between the external memories 7 and 8. FIG. 2 is a block diagram showing the detailed connection relationship between the computer 1.2 and the external memories 7 and 8 in one embodiment of the invention according to the first claim, focusing on memory transfer. To avoid complexity, Figure 2 only shows the structure of memory transfer from computer 1 to computer 2 when computer 1 is the main system and computer 2 is the standby system. In the figure, 12 and 22 are the main memories of the computer 1 or 2, which correspond to those with the same reference numerals in FIG. 13 and 2
3 is the processor of computer 1 or 2;
If (2) is the main system, when writing information such as source data to the main memory l2 (22), the information will be continuously leaked to the external bus, and if it is the standby system, the module end will be determined from the module execution information. is detected and the external memory 8 (7
) stored in the main memory 22 (12) in the computer 2 (1).
It differs from the conventional processor l1 or 2l in that it has a means for transferring data onto the processor l1 or 2l. Further, 5l has a 2-port memory structure and is a save memory for storing source data information to be transferred. 52 and 53 are differential amplifiers as transmitting means, and the differential amplifier 52 is connected to a computer l.
The differential amplifier 53 sends the source address information received from the computer 1 to the external memory 8, and the differential amplifier 53 sends the source data information received from the computer 1 to the external memory 8. 54 and 55 are differential amplifiers as receiving means, the differential amplifier 54 receives source address information from the differential amplifier 52 and sends it to the save memory 5l, and the differential amplifier 55 receives source data from the differential amplifier 53. Receive information and save memory 5
This is what is sent to 1. 56 and 57 are buffers serving as transfer means; the buffer 56 temporarily stores source address information read from the save memory 51 and sent to the computer 2, and performs I/F of the address bus; the buffer 57 transfers information from the save memory 5l to It temporarily stores the source data information that is read and sent to computer 2 and performs data path I/F. 58 monitors the abnormal signal from the control signal line and determines which of the computers 1 and 2 should be the main system, and activates the backup memory 51 and the differential amplifier 54, 55 which is the receiving means, or activates the differential amplifier 54, 55 which is the transmitting means. This is a duplication execution determination circuit that generates a switching signal that determines whether to operate differential amplifiers 52 and 53. Here, these external memories 7 and 8 have the same hardware configuration, and the main part thereof is shown in FIG.
In the external memory 7 connected to the main computer 1, differential amplifiers 52 and 53 as transmitting means are activated by the switching signal from the duplexing execution determination circuit 58, and the external memory 8 connected to the standby computer 2 operates. In response to the switching signal from the duplication execution determination circuit 58, the backup memory 51 and the differential amplifiers 54 and 55 serving as receiving means are activated. Next, we will explain the operation. The external memory 7.8 monitors the abnormal signal sent from the computer 1 or 2 via the control signal line with the duplication execution determination circuit 58, determines its status, and then selects one of the normal computers, e.g. While giving an input/output bus usage permission signal to computer 1,
Switch the input/output bus switch 5 to the computer 1 side. The computer 1 to which the input/output bus usage permission signal has been given in this way engages in actual work as the main system, while the other computer 2 stands by as the standby system. At this time, in the external memory 7, the differential amplifiers 52 and 53, which are transmitting means, operate according to the switching signal from the duplication execution determination circuit 58, and the external memory 7 operates.
◆By the switching signal from the other duplication execution determination circuit 58, the save memory 51 and the differential amplifiers 54 and 55, which are receiving means, are activated. When the processor 13 of the main computer 1 starts actual work processing and executes write access to the main memory l2, the processor 13 of the main computer 1 successively connects source address information and source data information to the computer 1 via an external bus. The data is sent to the external memory 7. In the external memory 7, the source address information and source data information are received by the differential amplifier 52 or 53 and transmitted to the external memory 8. In the external memory 8, these are received by the differential amplifier 54 or 55, sent to the save memory 5l, and stored there. FIG. 4 is an explanatory diagram showing the data organization of this save memory 51. As shown in the figure, the source address information, source data information, the number of sources per module, module execution information, etc. are stored in this save memory 51. Here, the module execution information is information indicating the execution state of the module, and is written to the save memory 5l at the time of module switching. The external memory 8 generates an interrupt to the processor 23 of the standby computer 2 when module execution information indicating the end of the module is written to the save memory 5l.
The processor 23 uses this interrupt as a trigger to detect module start and module end from the module execution information, and transfers the corresponding source data information and module execution information stored in the save memory 5l onto the main memory 22 in the computer 2. do. That is, Brosetsa 23
checks the module where the module end occurred,
When the module is determined, the corresponding source address information and source data information are received from the buffers 56 and 57 via the external bus, the corresponding source address is determined by referring to the module-specific source address table, and the source address information is determined. Write the data to the corresponding address in the main memory 22. In this way, the source data on the main memory l2 in the main computer 1 is transferred to the main memory 22 of the standby computer 2 at the end of the module, and at the same time, the module execution information of the processor l3 is also transferred. Here, the differential amplifiers 52 to 52 are connected between the external memories 7 and 8.
55 is used for I/FL, but this is the main computer
If an error occurs in the external memory 8 while the main computer 1 is operating normally, and the standby computer 2 is turned off while the main computer 1 is still powered, the power to one system may be turned off. This is to prevent failures from spreading to other systems due to disconnection. In addition, if a problem occurs in the external memory 8 or the standby computer 2 while the main computer 1 is operating, and the power on the standby side is turned off and then turned on again, the main memory l2 of the main computer l The contents of the main memory 22 of the standby computer 2 will be different. In such a case, an equalization signal is applied to the processor l3 of the main computer 1, and the entire area of the main memory 12 is transferred in appropriate block units to the standby computer 2, where it is copied onto the main memory 22. In that case, as in the case described above, the source address information, source data information, etc. in block units are once transferred to the save memory 5l of the external memory 8, and then transferred to the main memory 22 by the processor 23 of the standby computer 2.
Transfer it on top. This process is repeatedly executed for the entire area of the main memory 12 to make the contents of the main memory l2 of the main computer 1 and the contents of the main memory 22 of the standby computer 2 the same. FIG. 5 is a block diagram showing the detailed connection relationship between the computer 1.2 and the external memories 7 and 8 in an embodiment of the invention according to the second claim, focusing on memory transfer, to avoid complexity. Therefore, only the structure of memory transfer from computer 1 to computer 2 is shown when computer 1 is the main system and computer 2 is the standby system. In the figure, 12.22 is the main memory,
13.23 is the processor, 5l is the save memory, 52,5
3 is a differential amplifier as a transmitting means, 54.55 is a differential amplifier as a receiving means, 56.57 is a buffer as a transfer means, and 58 is a duplication execution determination circuit, which are given the same reference numerals in FIG. It is the same or equivalent part. Reference numeral 59 designates a save memory that stores the source address information received by the differential amplifier 54, and a latch circuit that sends it to the data line of the save memory 51. 60 is an address generation circuit that generates addresses necessary for accessing the save memory 51. Here, these external memories 7 and 8 have the same hardware structure, and the main part thereof is shown in FIG. In the external memory 7 connected to the main computer 1, the differential amplifiers 52 and 53 as transmitting means are activated by the switching signal from the duplexing execution determination circuit 58, and the external memory 7 connected to the standby computer 2 is activated. 8, the duplication execution determination circuit 58
With the switching signal from , the save memory 51 and the differential amplifiers 54 and 55 as receiving means are activated. Next, we will explain the operation. The source address information and source data information sent to the external bus from the processor 13 of the main computer I in response to a write access to the main memory 12 are sent to the external memory via the differential amplifiers 52 and 53 of the external memory I). Sent to memory 8. In the external memory 8, the source address information is received by the differential amplifier 54, and the latch circuit 5
9 and latch it once. Further, the differential amplifier 55 receives source data information and sends it to the save memory 51. The save memory 5l stores this source data information according to the address generated by the address generation circuit 60, and also stores the source address information sent to the data line from the latch circuit 59. In this way, when writing to the main memory 12 is executed once in the main computer 1, writing is executed twice in the save memory 5l.
Here, when switching of a module occurs, when writing to the main memory 12 is executed, module execution information is similarly written to the corresponding area of the save memory 5l. Therefore, the processor 13 will receive positive acknowledgments from both the main memory l2 and the save memory 51 at the time of writing. Figure 4 shows the data structure of this save memory 51. When the module end is written to the save memory 51, the external memory 8 generates an interrupt to the processor 23 of the standby computer 2. Using this interrupt as a trigger, the processor 23 transfers the corresponding source data information and module execution information from the save memory 51 to the main memory 22.
Transfer it on top. In addition, when copying the entire area of the main memory l2 by the equalize signal, it is divided into predetermined blocks and transferred to the save memory 51 of the external memory 8 as in the case described above, and then copied to the standby system. The process of transferring onto the main memory 22 of the computer 2 is repeatedly executed for the entire area of the main memory 12. FIG. 7 shows the detailed connection relationship between the computer 1.2 and the external memory 7.8 in an embodiment of the invention according to the third claim, focusing on memory transfer, and shows that the meter l is the main system and the computer 2 is a block diagram showing only the structure of memory transfer from computer 1 to computer 2 when computer 2 is used as a standby system. FIG. In the figure, 12.22 is a main memory, 13.23 is a processor, 51 is a save memory, and 54.
55 is a differential amplifier as a receiving means, 56.57 is a buffer as a transfer means, 58 is a duplex execution determination circuit, 6
0 is an address generation circuit, which is the same or equivalent part to those with the same reference numerals in FIG. Further, 6l is a save memory that stores the source address information received from the main computer 1 via the external bus, and a latch circuit that sends the information to the data line of the save memory 51. This buffer receives incoming source data information and sends it to the data line of the save memory 51. 63 is a microprocessor that executes transfer WA control at the module end timing detected from the module execution information in the save memory 5l. 64 and 65 are differential amplifiers as transmitting means, and the differential amplifier 6
4 sends source address information to the external memory 8 of the destination, and a differential amplifier 65 sends source data information from the save memory 51 to the external memory 8 of the destination. Here, these external memories 7 and 8 have the same hardware configuration, and the external memory 7 connected to the main computer 1 transmits data to the backup memory 5l by a switching signal from the duplication execution determination circuit 58. Differential amplifier 64 as means
．． 65 is activated, and in the external memory 8 connected to the standby computer 2, the switching signal from the duplexing execution determination circuit 58 causes the backup memory 5l and the differential amplifier 54.5 as receiving means to be activated.
5 is activated. Next, we will explain the operation. The processor 13 of the main computer 1 that has executed the write access to the main memory l2 also sends the same source address information and source data information to the external bus. In the external memory 7, source data information is received in a buffer 62 and stored in a save memory 5l.
The source address information is once latched by the latch circuit 61 and then sent to the data line. The save memory 5l stores these source data information and source address information together with module switching information according to the address generated by the address generation circuit 60. At this time, a module magnet is added to the beginning of each information. Here, when switching of the module occurs, the module execution information is written to the cough pad area of the save memory 51 of the external memory 7 in the same way when writing to the main memory l2 is executed. The data structure of the save memory 5l at this time is shown in FIG. The microprocessor 63 of the external memory 7 reads out the source address information, the source data information 11, and the module execution information of the core module stored in the save memory 51, and calculates the difference. The data is sent to external memory 8 via dynamic amplifiers 64 and 65. In the external memory 8, this is a differential amplifier 54.5
5 and accumulates it in the backup memory 51.
When the module end is written to , standby computer 2
generates an interrupt to the processor 23. The processor 23 uses this interrupt as a trigger to transfer the corresponding source data information and module execution information from the save memory 5l of the external memory 8 onto the main memory 22. In addition, when copying the entire area of the main memory 12 by the equalize signal, it is divided into predetermined blocks, and as in the case described above, it is once transferred to the save memory 5l of the external memory 7, and then The process of transferring the standby calculation 82 onto the main memory 22 via the memory 51 is repeated for the entire area of the main memory l2. In each of the above embodiments, a case has been described in which the external memory generates an interrupt signal at the timing when the module end is written to its save memory, and triggers the processor of the standby computer. The processor may check the module end on the external memory save memory by polling. In this case, the timing at which the module end is detected is the timing at which transcription is started. In addition, in each of the above embodiments, the save memory in the external memory,
Although the switching signal for the operation of the transmitting means, receiving means, etc. is automatically given from the duplexing execution determination circuit, it may also be given manually by a switch, etc. Furthermore, the mutual connection of external memories may be Although the explanation has been made using an I/F using a dynamic amplifier, serial transmission using a coaxial cable may also be performed, and in either case, the same effects as in the above embodiment can be achieved. [Effects of the Invention] As described above, according to the invention according to claim 1, external memories interconnected by I/F cables are arranged between the computers of the dual system, and the main system When a computer updates source data, the source address and module execution information along with the source data are temporarily stored in an external memory connected to the standby computer, and the module execution information from the main computer becomes the module end. Since the information stored in the external memory is transferred to the main memory of the standby computer when the computer is connected to the standby computer, When storing each of the above information from the main computer in the external memory,
By latching the source address information once, it is transferred to external memory as data, and when the module execution information from the main computer reaches the module end, the information accumulated in the external memory is transferred to the standby computer. By transcribing it onto the main memory, the module execution information is reliably passed to the standby computer, and the synchronization of the most important source data can be maintained when switching between dual systems, making it possible to achieve a process that is close to natural. This has the effect of providing a dual system device with extremely small shock to the input/output device. According to the invention according to the third claim, when the main computer updates the source data, each piece of information is temporarily stored in an external memory connected to the main computer, and the module from the main computer When the execution information becomes the module end,
The information stored in the external memory connected to the main metering machine is transferred to the main memory of the standby computer via the external memory connected to the standby computer. , module execution information is passed to the standby computer, the synchronization of source data is maintained, and a dual system device with extremely low sick time for input/output devices is obtained, and the access time of the main computer is shortened. and has the effect of improving noise resistance.

[Brief explanation of drawings]

FIG. 1 is a schematic configuration diagram showing a dual system device according to an embodiment of the present invention, FIG. 2 is a block diagram showing details of essential parts of an embodiment of the invention according to claim 1, and FIG. FIG. 3 is a block diagram showing the configuration of the external memory, FIG. 4 is an explanatory diagram showing the data structure of the save memory, and FIG. 5 is details of the main part of an embodiment of the invention according to the second claim. , FIG. 6 is a block diagram showing the structure of the external memory, FIG. 7 is a block diagram showing details of the main part of an embodiment of the invention according to claim 3, and FIG. 8 is a block diagram showing the structure of the external memory. FIG. 9 is a block diagram showing details of the main parts, and FIG. 10 is a time chart showing the flow of module execution. 1.2 is a computer, 41.42 is an input/output bus, 5 is an input/output bus switch, 6 is an input/output device, 12.2
2 is the main memory, 13.23 is the processor, 5l is the backup memory, 5 2.5 3, 6 4.6 5 is the transmitting means (differential amplifier), 5 4.5 5 is the receiving means (differential amplifier), 56 and 57 are transfer means (banfers), 58 is a duplication execution determination circuit, 59 and 61 are latch circuits, 60 is an address generation circuit, and 63 is a microprocessor. In addition, the same reference numerals in the figures indicate the same or equivalent parts. 1 Figures 41 and 42: Input Cache Figure 3. 4 Figure 6 Punch escape memory Figure 10

Claims (3)

[Claims] (1) A computer that is duplicated into a main system and a standby system, an input/output device connected to the input/output bus of any of the computers, and a connection between the input/output device and the input/output bus of each computer. In a dual system device equipped with an input/output bus switcher for switching connections, a set of external memories interconnected by an interface cable and connected to one of the computers by an external bus and a control signal line. When writing source data to the built-in main memory as a main computer, each computer writes the source data information, the source address information on the main memory where the source data information is stored, and the computer's a transmitting means for transmitting information such as module execution information indicating a module execution state to the external bus, and a standby computer that detects a module end from the module execution information received from the external bus and stores the information in the external memory. a processor having a transfer means for transferring the information onto the main memory; the external memory includes a save memory for accumulating the information from the main computer; and a processor for transmitting the information from the main computer to the external bus. transmitting means for receiving the information stored in the save memory and transmitting the information to the external memory of the other party via the interface cable; receiving means for receiving the information from the interface cable; a transfer means for transferring the data to the standby computer via the control signal line; and monitoring an abnormal signal from the control signal line to determine which of the computers should be made the main system;
A duplex system device comprising: a duplex execution determination circuit that generates a switching signal for selectively operating the save memory and the receiving means or the transmitting means. (2) A computer that is duplicated into a main system and a standby system, an input/output device connected to the input/output bus of any of the computers, and a connection between the input/output device and the input/output bus of each computer. In a dual system device equipped with an input/output bus switcher for switching connections, a set of external memories interconnected by an interface cable and connected to one of the computers by an external bus and a control signal line. When writing source data to the built-in main memory as a main computer, each computer writes the source data information, the source address information on the main memory where the source data information is stored, and the computer's a transmitting means for transmitting information such as module execution information indicating a module execution state to the external bus, and a standby computer that detects a module end from the module execution information received from the external bus and stores the information in the external memory. a processor having a transfer means for transferring the information onto the main memory; the external memory includes a save memory for accumulating the information from the main computer; and a processor for transmitting the information from the main computer to the external bus. a transmitting means for receiving the information and transmitting it to the other party's external memory via the interface cable; a receiving means for receiving the information from the interface cable; and a receiving means for once receiving the source address information received by the receiving means. a latch circuit that latches and sends the data to the save memory together with the source data information; an address generation circuit that generates an address of the save memory;
Transfer means for transferring the information stored in the save memory to the standby computer via the external bus, and monitoring for an abnormal signal from the control signal line to determine which of the computers should be made the main computer. 1. A duplex system device comprising: a duplexing execution determination circuit that determines a switching signal to selectively operate the save memory and the receiving means or the transmitting means. (3) A computer that is duplicated into a main system and a standby system, an input/output device connected to the input/output bus of any of the computers, and a connection between the input/output device and the input/output bus of each computer. In a dual system device equipped with an input/output bus switcher for switching connections, a set of external memories interconnected by an interface cable and connected to one of the computers by an external bus and a control signal line. When writing source data to the built-in main memory as a main computer, each computer writes the source data information, the source address information on the main memory where the source data information is stored, and the computer's a transmitting means for transmitting information such as module execution information indicating a module execution state to the external bus, and a standby computer that detects a module end from the module execution information received from the external bus and stores the information in the external memory. a processor having a transfer means for transferring the information onto the main memory; the external memory includes a save memory for storing the information from the main computer; a latch circuit that once latches the source address information received from the computer and sends it to the save memory together with the source data information received from the main computer; an address generation circuit that generates an address of the save memory; and an address generation circuit that generates an address of the save memory; a microprocessor that executes transcription control at a timing of a module end detected from the module execution information in the memory, a transmitting means that transmits the information from the save memory to the external memory of the other party via the interface cable, and the interface receiving means for receiving the information from the cable; transfer means for transmitting the information stored in the backup memory to the standby computer via the external bus; and monitoring for an abnormal signal from the control signal line. and a duplication execution determination circuit that determines which of the computers should be the main system and generates a switching signal that selectively activates the save memory and the receiving means or the transmitting means. dual system equipment.