JP4030951B2 - Data duplication apparatus and method - Google Patents

Description

  The present invention relates to a data duplication apparatus and method having an active system and a standby system.

  In systems that require reliability in information communication systems, etc., when a failure occurs, it is necessary to avoid stopping the system. Therefore, the active / standby redundant configuration is used, and a failure occurs in the active system. At this time, switching to the standby system is performed. When switching from the standby system to the active system, various methods have been conventionally used in order to realize, for example, an operation that maintains data consistency and improves reliability.

  When a failure occurs in the active file memory while copying the contents of the file memory on the active CPU (Central Processing Unit) to the standby CPU, the standby system that has already been duplicated for the main memory A method is known in which the CPU is switched to the active system and restarted, and after that, a file backup is performed from the main memory of the standby system to the file memory, and only the file memory of the standby system CPU continues the service in the single lung operation state. (See, for example, Patent Document 1 below).

  An apparatus and a method for switching to the active processing apparatus of the standby processing apparatus without destroying the shared data held in the standby processing apparatus even if the active processing apparatus becomes a failure while writing the shared data Is also known (see, for example, Patent Document 2 below). According to this apparatus and method, the shared data written from the active processor to the storage device of the standby processor is temporarily stored in the buffer of the standby processor, and only when the shared data is normally written to the buffer. The shared data in the buffer is transferred and written to the storage device of the standby processing device, so that even if the active processing device becomes faulty while writing the shared data, the state before the system switching can be completely taken over. I have to.

  The above-described conventional method (the method described in Patent Documents 1 and 2 below) is to always duplex the latest data in a storage device existing on the active / standby system. In the case of these configurations, there are a memory controller that temporarily writes data into a memory via a general-purpose bus and a memory controller that writes data via a shared bus. However, in such a configuration, data transmission between the two control devices of the active system and the standby system must be performed at a somewhat low frequency due to measures such as noise, and as a result, the data transfer processing speed decreases. As a result, the system processing capacity also decreases.

  In addition, regarding the control system of the exchange system having a duplex configuration for compensating for uninterrupted operation, an external system having an area for storing data that needs to be shared between the active system, the standby system, and the active system and the standby system There is also known a system that includes a changeover switch for switching between a storage device and a system to which the external storage device is connected, and transfers operation information between the active system and the standby system to a common external storage device between the redundant systems ( For example, see Patent Document 3 below).

  Further, in a duplex system with shared memory, the shared system has a status information area for the main system and a status information area for the slave system in the shared memory, and the main system periodically sends a status information area for the main system in the shared memory. The data that is regularly updated is written, and the slave system periodically reads the status information area of the master system in the shared memory, checks the update status of the data value, and checks the normality of the master system. There is also known a shared memory duplex system that is determined (see, for example, Patent Document 4 below).

  These systems (configurations described in Patent Documents 3 and 4 to be described later) restore data by software control when system switching occurs, and require special software control. Since it takes time from occurrence of data to data restoration, the system may stop during that time.

  Further, as a redundant system switching device having a shared storage device, each of the active system and the standby system has a CPU, a shared memory, and an arbiter circuit, and the operating system is disconnected without disconnecting the bus when an operating system failure occurs. There is also known an apparatus and method that includes system switching means for switching from a standby system to a standby system, and performs system switching while suppressing loss of data being processed without stopping bus communication (see, for example, Patent Document 5 below). Furthermore, a shared disk is provided between the active server and the standby server, and each server has an operation mode management unit that manages operation mode information for identifying whether the server is the active system or the standby system, and a self-failure has occurred. There is also known a system that includes a configuration control management unit for notifying other servers and clients of the occurrence of a failure, and that when a failure occurs in the active server, the takeover to the standby server is performed quickly and smoothly ( For example, see Patent Document 6 below).

Japanese Patent Application Laid-Open No. 11-249923 (page 3, FIG. 1) JP 07-287694 A (page 3, FIG. 1). JP 05-244260 A (page 3, FIG. 1), JP-A 62-263554 (page 3, FIG. 1). JP 2002-63047 A (3rd, 4th page, FIG. 1) JP 2003-22259 A (page 3-5, FIG. 1)

  As described above, in the conventional duplex system, data transmission between the two control devices of the active system and the standby system is avoided at the maximum transmission speed in consideration of noise and the like, and is performed at a relatively low speed. Therefore, there is a problem that the processing performance of data transfer is lowered and the system performance is also lowered.

  In addition, in a configuration in which data is restored by software control when system switching occurs, dedicated software control is required, which increases costs.

  Further, in the data restoration processing by software control, it takes time from the time of system switching to the restoration of data. For this reason, there is a problem that the system may stop during that time.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a duplexing apparatus and method that avoids a decrease in the processing performance of the system, increases the speed, and improves the reliability.

  Another object of the present invention is to provide a duplexing apparatus and method that enables system switching without requiring special software processing such as data backup, and achieves high-speed and high-reliability system switching while reducing costs. Is to provide.

  The present invention that achieves the above-described object can be summarized as follows. In a duplex system apparatus comprising an active system and a standby system, a shared recording device is provided in the active system and the standby system, and the memory controller in each system is provided. Is provided with a determination flag, which enables high-speed access to the main memory except during system switching, thereby speeding up data transfer processing. The apparatus according to one aspect of the present invention is configured such that when one is the active system, the other is a standby system, and each of the systems can be freely switched from the active system to the standby system and from the standby system to the active system. Including at least one control device and a shared recording device shared by the two control devices, each of the two control devices controlling a CPU (Central Processing Unit), a memory, and data writing and reading. A memory control unit, and the memory control unit has flag information indicating validity / invalidity of data for each predetermined memory area with respect to the memory, and the memory control of the active control device The unit stores and holds the write data from the CPU of the active control device in the memory and the shared recording device in the active control device based on the flag information, In response to a data read request from the CPU of the active control device, the active control device reads out data from the memory in the active control device or the shared recording device based on the flag information. Means for supplying to the CPU.

  In the device according to the present invention, when the memory control unit of the active control device receives a data write request from the CPU of the active control device, the memory control unit in the memory area corresponding to a write address When the flag information indicates valid, the write data is written into the memory of the active control device and the shared recording device, whereas when the flag information indicates invalid, the write address Corresponding to the data read from the shared recording device and the data obtained by merging the write data from the CPU as the latest data, the memory of the active control device, and the shared recording It is good also as a structure which performs control which writes in an apparatus and validates the said flag information.

  In the device according to the present invention, the memory control unit of the active control device may receive a data read request from the CPU of the active control device, and the memory area corresponding to the read address When the flag information indicates valid, the data is read from the memory of the active control device and transferred to the CPU of the active control device, while the flag information indicates invalid Reading the data from the shared recording device, transferring the data read from the shared recording device to the CPU of the active control device, writing to the memory of the active control device, and the flag It is good also as a structure which performs control which validates information.

  The apparatus according to the present invention preferably has a communication line for notifying system switching from the active control apparatus to the standby control apparatus. When switching the standby control device from the standby system to the active system, the memory control unit of the control device switched from the standby system to the active system receives data processing access from the CPU of its own device, It is determined whether or not the flag information in the memory area corresponding to the access address is valid. As a result of the determination, when the flag information is invalid, data is read from the shared recording device corresponding to the access address, and when the access is data writing, the data read from the shared recording device and the CPU The merged data is merged into the memory and the shared recording device, and when the access is data read, the read data is written into the memory, and flag information corresponding to the memory area On the other hand, if the flag information is valid as a result of the determination, when the access is data writing, the data is written to the memory and the shared recording device, and when the access is data reading, from the memory It is good also as a structure which performs control which reads data.

  In the apparatus according to the present invention, the memory control unit determines whether the flag information is valid or invalid by a hardware circuit, thereby realizing high speed.

  In the present invention, the memory control unit includes at least one data buffer for inputting / outputting data to / from the shared recording device, and temporarily stores the data transferred from the CPU in the data buffer Then, it may be configured to be transferred to the shared recording device.

  In the present invention, when the memory control unit reads data from the shared recording device, the memory control unit reads data corresponding to the memory area and prefetches data corresponding to another memory area from the shared recording device. Good.

In the method according to another aspect of the present invention, when one is an active system, the other is a standby system, and each of the systems can be freely switched from the active system to the standby system and from the standby system to the active system. Including at least one control device and a shared recording device shared by the two control devices, and each of the two control devices includes a CPU, a memory, and a memory control unit that controls writing and reading of data. A data duplication method by a duplication device having flag information indicating validity / invalidity of data for each memory area predetermined for the memory in the memory control unit,
While the active control device is in operation, the memory control unit of the active control device uses the write data from the CPU of the active control device based on the flag information as the active control device. Storing and holding in the memory and the shared recording device,
In response to a data read request from the CPU of the active control device, based on the flag information, data is read from the memory in the active control device or the shared recording device, and the active control Supplying to the CPU of the apparatus.

In the method according to the present invention, when the memory control unit of the active control device receives a data write request from the CPU of the active control device,
If the flag information in the memory area corresponding to the write address indicates valid, writing the write data to the memory of the active control device and the shared recording device;
On the other hand, if the flag information indicates invalidity, the data obtained by merging the data read from the shared recording device corresponding to the write address and the write data from the CPU is the latest data. As another example, the information processing apparatus may include a step of writing to the memory of the active control device and the shared recording device, enabling the flag information, and performing control.

In the method according to the present invention, when the memory control unit of the active control device receives a data read request from the CPU of the active control device,
If the flag information in the memory area corresponding to the read address indicates valid, reading data from the memory of the active control device and supplying the data to the CPU of the active control device;
On the other hand, when the flag information indicates invalid, the data is read from the shared recording device, the data read from the shared recording device is transferred to the CPU of the active control device, and the active And a step of performing control to write the flag information in the memory of the control device and validate the flag information.

  According to the present invention, in a duplex system apparatus comprising an active system and a standby system, a shared recording device is provided for the active system and the standby system, a discrimination bit is provided in the memory control unit in each system, and system switching is performed. At other times, high-speed access to the main memory is possible, and data transfer processing is speeded up.

  In addition, according to the present invention, special software processing such as data backup is not required for system switching, so that costs can be reduced and system switching speed can be increased.

  In order to describe the present invention in more detail, it will be described below with reference to the accompanying drawings. As shown in FIG. 1, a duplexer according to an embodiment of the present invention includes an active control device (1a) and a standby control device (1b), and further includes an active control device ( 1a) and a standby control device (1b) are provided with a shared recording device (17) comprising a disk recording device or the like connected via a shared bus (19). The standby control device (1b) is operated by switching the system to the active system, for example, when a failure occurs in the active control device (1a).

  The active control device (1a) includes a CPU (11), a memory control unit (12), and a main memory (13). Similarly to the active control device (1a), the standby control device (1b) also includes a CPU (14), a memory control unit (15), and a main memory (16). The active control device (1a) and the standby control device (1b) have the same components.

  In one embodiment of the present invention, the latest data used by the CPU (11) is always held in the main memory (13) and the shared recording device (17) while the active control device (1a) is in operation. The

  A communication bus (18) is provided between the memory control unit (12) of the active control device (1a) and the memory control unit (15) of the standby control device (1b). The memory control unit (12) of the active control device (1a) and the memory control unit (15) of the standby control device (1b) are connected to the shared recording device (17) via the shared bus (19). Has been.

  FIG. 2 is a diagram illustrating a configuration of the memory control unit (12) of the control device (1a) (and the memory control unit (15) of the control device (1b)). As shown in FIG. 2, the memory control unit (12) of the control device (1a) forms flag information for determining whether or not the data held in the main memory (13) is valid (latest). It has a data discrimination bit (21). The memory control unit (12) reads the latest data from the main memory (13) or the shared recording device (17) according to the value (valid / invalid) of the data discrimination bit (21). The memory control unit (15) of the control device (1b) has a data determination bit (27) for determining whether or not the data held in the main memory (16) is valid (latest). The memory control unit (15) reads the latest data from the main memory (16) or the shared recording device (17) according to the value (valid / invalid) of the data discrimination bit (27). The data discrimination bit (21/27) is assigned 1 bit to a memory area (area) of a predetermined size in the main memory (13/16).

  When the system is switched due to a failure of the active control device (1a) and the operation of the standby control device (1b) is started, in the control device (1b) that has been the standby system until then, The latest data exists only in the shared recording device (17). For this reason, all the data discrimination bits (27) of the memory control unit (15) of the control device (1b) are in an invalid state.

  When there is a data request from the CPU (14) of the control device (1b), the memory control unit (15) reads the latest data from the shared recording device (17) according to the contents of the data discrimination bit (27).

  The data read from the shared recording device (17) is transferred to the CPU (14) and stored in the main memory (16), and the corresponding data discrimination bit (27) is updated (valid). ) Is performed.

  With this control, in the control device (1b) that is switched from the standby system to the active system, the memory control unit (15) accesses the corresponding memory area from the next time so that the transfer speed is higher than that of the shared recording device (17). A high-speed main memory (16) is selected, and the data transfer process can be speeded up.

  The present invention will be described with reference to examples in order to explain it in more detail. FIG. 1 is a diagram showing the configuration of an embodiment of the present invention. Referring to FIG. 1, in one embodiment of the present invention, an active control device 1 a includes a CPU 11 that executes data transfer processing, a high-speed main memory 13 that stores data, and a memory control that controls the main memory 13. Part 12. Similarly, the standby control device 1 b includes a CPU 14, a main memory 16, and a memory control unit 15. A shared recording device 17 is connected to the active control device 1 a and the standby control device 1 b via a shared bus 19. In the present embodiment, the shared bus 19 is preferably a general-purpose bus such as ATA 133, Serial-ATA, IEEE 1394, USB 2.0, etc., from the viewpoint of high speed and noise resistance. The shared recording device 17 is a recording device that can be connected to the shared bus 19. In addition, the control device 1a and the control device 1b have a communication bus 18 for transmitting information necessary for system switching when a failure occurs.

  While the active control device 1a is in operation, the latest data (or the data updated most recently) is written into the main memory 13 and simultaneously recorded in the shared recording device 17 via the shared bus 19. . Thereby, data duplication is realized.

  As shown in FIG. 2, the memory control unit 12 of the active control device 1 a has a data buffer 26, and the difference in writing time to the shared recording device 17 whose access speed is slower than the main memory 13. To avoid a decrease in processing speed. Write data from the CPU 11 of the control device 1a is transferred to the memory control unit 12, and the memory control unit 12 uses the data buffer 26 to share, for example, by double buffer processing, DMA (Direct Memory Access) or the like (block transfer). By writing to the recording device 17, the I / O time is shortened.

  As shown in FIG. 2, the memory control unit 12 has a data discrimination bit 21 and discriminates whether the latest data exists in the main memory 13 or the shared recording device 17. Can do. The data determination bit 21 is assigned 1 bit to a memory area (area) that can be set to an arbitrary size. The size of the memory area is, for example, in units of mK bytes (m is an arbitrary integer), and at least the number of data obtained by dividing the memory space of the main memory 13 (16) where data is written (updated) by mK bytes. A discrimination bit 21 (27) is provided corresponding to the memory area. The memory control unit 12 (15) can refer to the corresponding data determination bit 21 (27) from the access address from the CPU 11 (14). In the example shown in FIG. 2, the main memory (13 (16) in FIG. 1) has a memory area composed of area a to area n, and data discrimination bits 22 to 25 (28 to 31) corresponding to each area. Is provided. The data discriminating bit 21 (27) may be composed of an arbitrary storage device such as a register or a memory.

  In the active control device 1 a, when a data read request is generated from the CPU 11, the memory control unit 12 receives data from the main memory 13 or the shared recording device 17 according to the data determination bit 21 in the memory area corresponding to the access address. Read data.

  The data determination bit 21 indicates invalidity (the latest data does not exist in the main memory 13), the latest data exists in the shared recording device 17, and the memory control unit 12 reads the data from the shared recording device 17. In this case, the memory control unit 12 transfers the data to the CPU 11 and writes it into the main memory 13 to validate the data determination bit 21. Thereafter, when the CPU 11 accesses the corresponding memory area, the data discrimination bit 21 is set valid, so that data is read from the main memory 13 and the processing speed is increased.

  FIG. 3 is a schematic diagram for explaining the flow of data when reading data from the CPU in this embodiment shown in FIG.

  FIG. 4 is a schematic diagram for explaining the flow of data at the time of data writing from the CPU in the present embodiment shown in FIG.

  The operation of this embodiment will be described with reference to FIG. 1, FIG. 2, FIG. 3, and FIG. FIG. 5 is a flowchart for explaining the operation of this embodiment.

  In a system that requires reliability, as shown in Fig. 1, a redundant configuration of the active system and the standby system is adopted, and when the active system fails, the system is switched to avoid the system from shutting down. is doing.

  In the normal operation, the active control device 1a is in an operating state, and reading of data from the CPU 11 is executed from the main memory 13 through the route (path) of access a in FIG. Further, data writing from the CPU 11 during normal operation is executed simultaneously to the main memory 13 and the shared recording device 17 through the route of access c in FIG.

  With this configuration, the current main memory 13 and the shared recording device 17 always hold the latest data.

  Although the access speed of the shared recording device 17 is relatively low compared to the main memory 13, in order to avoid a decrease in the system processing speed during continuous writing, the data buffer 26 ( 2).

  At the time of continuous writing, data is temporarily stored in the data buffer 26, and the access to the main memory 13 side is not affected. However, when all the data buffers 26 of the memory control unit 12 are in a full state, the write request from the next CPU 11 is not accepted, and it is processed as a waiting state (the write request of the CPU 11 is waited). When the data buffer 26 becomes empty, the CPU 11 side is notified of ready or the like, and write data from the CPU 11 is written into the main memory 13 and the data buffer 26.

  The memory control unit 15 of the standby control device 1b determines the status of the active / standby system of its own device, stops the output of the shared bus 19, and avoids bus contention.

  Here, when a failure or the like occurs in the active control device 1a, the memory control unit 12 of the active control device 1a monitors the state of the data buffer 26 and determines that the processing of the data buffer 26 is completed. Thus, the switching information is transmitted via the communication bus 18. By this processing, switching between the active system and the standby system is executed, and the control device 1b that has been the standby system until then is switched to the active system and starts operation. At this time, the memory control unit 12 of the control device 1a switched from the active system to the standby system stops the output to the shared bus 19 (the bus driver output is set to the high impedance state), and the memory becomes the active system. The control unit 15 secures the occupation right of the shared bus 19.

  When the system is switched and the data access request is generated from the CPU 14 in the control device 1b which is the active system, the memory control unit 15 executes data access according to the data determination bit 27 (see FIG. 2). The data discrimination bit 27 is assigned to each memory area divided into arbitrary sizes.

  Next, with reference to FIG. 5, the operation after system switching in the present embodiment will be described.

  When the memory control unit 15 of the control device 1b which has become the active system receives a data transfer processing access from the CPU 14 (step 50), the data determination bit 27 of the memory area (area) including the access address is valid. It is discriminated whether it is invalid or not (step 51).

  If the data determination bit 27 of the memory area is invalid (NO branch of step 51), the memory control unit 15 determines that the latest data of the corresponding memory area is in the shared recording device 17, and the shared recording device Data is read from 17 (step 55). In step 51, in the case of an area accessed for the first time after execution of system switching, the data discrimination bit 27 in the memory area becomes invalid.

  When the data access is a write access (YES branch at step 56), only the data of the address to be updated from the CPU 14 is updated (data merge) in the memory control unit 15 in accordance with the route of access d in FIG. ) Is performed. That is, in the memory area corresponding to the data discrimination bit 27, only the data at the address to be updated is updated, and the data at the other addresses are held as they are.

  Thereafter, the data is written into the main memory 16 and the shared recording device 17, and the latest data is duplicated (step 57). After the data writing is completed, the data discrimination bit 27 of the area is updated effectively (step 59).

  If the data discrimination bit 27 of the area is invalid and the access is a read access (step 56), the data in the memory area corresponding to the data discrimination bit 27 is shared and recorded according to the route of access b in FIG. The data read from the device 17 and the request data from the CPU 14 are transferred to the CPU 14 and the data in the read area is written to the main memory 16 (step 58). Thereafter, the internal determination bit 27 of the corresponding area is effectively updated (step 59).

  Next, if the data discrimination bit 27 of the corresponding area is valid (YES branch of step 51), and the corresponding access is a write access (YES branch of step 52) (access is executed once, the data discrimination bit 27 is updated. The memory control unit 15 determines that the latest data exists in the main memory 16 and the shared recording device 17, and follows the route of access c in FIG. Then, data is written to the shared recording device 17 and the latest data is duplicated (step 53).

  In addition, when the data discrimination bit 27 of the corresponding area is valid (YES branch of step 51) and the corresponding access is read access (NO branch of step 52) (access is executed once, the data discrimination bit 27 is updated. The memory control unit 15 determines that the latest data is in the main memory 16, reads the data from the main memory 16 according to the route of access a in FIG. 3, and transfers it to the CPU 14 (step 54). .

  As described above, when the data transfer process access from the CPU 14 occurs in the invalid memory area, the latest data is written into the main memory 16 and the data determination bit 27 is updated. Thereafter, when an access to the corresponding area occurs, the data determination bit 27 is effectively updated, so that the main memory 16 is accessed, and the data transfer process is speeded up.

  According to this embodiment, when activated as a standby control device, all the data discrimination bits of the memory control unit of the standby control device are invalidated. As a result, even when system switching occurs during operation, the latest data can be duplicated without requiring special software control.

  In addition, according to the present embodiment, even when a faulty system (for example, the original active system) is recovered by device replacement or the like, a new duplex system is constructed without requiring special software control. Can do.

  Next, the function and effect of this embodiment will be described.

  According to this embodiment, since most of the data access can be performed in the main memory, the data transfer process can be speeded up. According to this embodiment, even when switching between the active system and the standby system, the memory area that has been accessed once will be accessed to the main memory from the next time. Processing is speeded up.

  According to the present embodiment, a data discrimination bit is provided in the memory control unit so that device recognition in which the latest data exists can be controlled by hardware. Therefore, no special software control is required when switching between the active system and the standby system, facilitating the implementation and reducing the cost.

  FIG. 6 is a flowchart for explaining the operation of the second embodiment of the present invention. Referring to FIG. 6, in this embodiment, steps 60 and 64 (comprising steps 61 to 63) are added to the processing operation of the embodiment described with reference to FIG. In FIG. 6, the same processing steps as those in FIG. 5 are denoted by the same reference numerals (step numbers) as those in FIG. 5. Is omitted.

  Immediately after the switching between the active system and the standby system occurs, when the access request is generated from the CPU 14 of the control device 1b switched from the standby system to the active system, the data determination bit 27 of the memory control unit 15 is invalid. Therefore, the access frequency to the shared recording device 17 may increase. Under such circumstances, data access takes time, and system performance may be degraded.

  In the present embodiment, as means for solving this problem, the memory control unit 15 (12) is provided with a data prefetching function. When the access address of the data request from the CPU 14 corresponds to the invalid area, after the data request cycle is completed (step 59), the previous request cycle address is incremented (step 61). In step 60 after reading data from the shared recording device 17, if pre-reading processing is in progress, it is read access, so determination of whether or not it is write access in step 56 is skipped, and the corresponding area is skipped. Performs main memory write processing.

  When the incremented address is within the prefetch range of the memory control unit 15 (the prefetch range can be arbitrarily set) (step 62), and an access request from the CPU 14 has not occurred in an area other than the prefetch range (step 63) Data is pre-read from the shared recording device 17 continuously in a plurality of areas (step 55).

  In addition, after the address increment is executed (step 61), when an access request from the CPU 14 is generated in an area other than the prefetch range (step 62), the access request from the CPU 14 is given priority.

  The access requested from the CPU 14 is often a continuous address due to the well-known locality of the program. In this embodiment, the memory control unit 15 pre-reads from the shared recording device 17 in advance, thereby speeding up data access.

  Even when access to the prefetched data from the CPU 14 is not executed immediately, the prefetched data is written in the main memory 16 as it is, and the data discrimination bit 27 of the corresponding area is effectively updated.

  Next time, when the access from the CPU 14 is the corresponding area, the main memory 16 can be accessed. For this reason, it is possible to increase the speed of the system.

  In the flowchart shown in FIG. 6, the CPU 14, the memory control unit 15, the main memory 16, the data determination bit 27, and the data buffer 32 of the control device 1 b are stored in the CPU 11 when the active control device is the control device 1 a. The memory control unit 12, the main memory 13, the data discrimination bit 21, and the data buffer 26.

  In the above embodiment, the control device may be a server or a control system device of an exchange system. Although the present invention has been described with reference to the above-described embodiment, the present invention is not limited to the above-described embodiment, and various modifications and corrections that can be made by those skilled in the art within the scope of the present invention. Of course.

It is a figure which shows the structure of one Example of this invention. It is a figure which shows the structure of the memory control part of one Example of this invention. It is a figure for demonstrating the read-out operation | movement in one Example of this invention. It is a figure for demonstrating the write-in operation | movement in one Example of this invention. It is a flowchart which shows the process sequence of one Example of this invention. It is a flowchart which shows the process sequence of the other Example of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1a Active system control apparatus 1b Standby system control apparatus 11, 14 CPU
12, 15 Memory controller (controller)
13, 16 Main memory 17 Shared recording device 18 Communication bus 19 Shared bus 21, 27 Data discrimination bit 22, 28 Data discrimination bit of area a 23, 29 Data discrimination bit of area b 24, 30 Data discrimination bit of area c 25, 31 Data discrimination bit for area n 26, 32 Data buffer 50-63 steps

Claims (10)

One of the active system and the other of the standby system, each of which can be freely switched from the active system to the standby system and from the standby system to the active system,
A shared recording device shared by the two control devices;
Including at least
Each of the two control devices
A CPU (Central Processing Unit), a memory, a memory control unit for controlling writing and reading of data,
Have
The memory control unit has flag information indicating validity / invalidity of data for each predetermined memory area with respect to the memory,
The memory control unit of the active control device writes write data from the CPU of the active control device to the memory and the shared recording device of the active control device based on the flag information. Keep in memory,
In response to a data read request from the CPU of the active control device, based on the flag information, data is read from the memory or the shared recording device of the active control device to control the active system Means for supplying to the CPU of the apparatus ;
A communication line for notifying system switching from the active control device to the standby control device;
When switching the standby control device from the standby system to the active system, the memory control unit of the control device that has switched from the standby system to the active system receives a data access request from the CPU of the own device , Determine whether the flag information of the memory area corresponding to the access address is valid,
When the flag information is invalid,
Read the data corresponding to the access address from the shared recording device,
When the access is data writing, the data read from the shared recording device and the write data from the CPU are merged, and the merged data is written to the memory and the shared recording device,
When the access is data read, the read data from the shared recording device is supplied to the CPU and written to the memory to validate the flag information,
On the other hand, if the flag information is valid,
When the access is data writing, data is written to the memory and the shared recording device,
When the access is data read, control is performed to read data from the memory and supply the read data to the CPU .   2. The data duplicating apparatus according to claim 1, wherein in the memory control unit, each flag information provided for each memory area includes a bit for holding a value corresponding to valid / invalid. The memory control unit, the data duplexing system as claimed in claim 1 or 2, wherein the determination of the valid / invalid flag information is provided for each memory region is configured to perform a hardware circuit, it is characterized. The memory control unit includes at least one data buffer for temporarily storing data to be input and / or output with the shared recording device. 4. The data duplication device according to any one of 3 . When the memory control unit reads data from the shared recording device,
2. The data duplicating apparatus according to claim 1, wherein data corresponding to a memory area to be read is read from the shared recording apparatus, and data corresponding to another memory area is pre-read from the shared recording apparatus. The memory control unit includes at least one data buffer for temporarily storing data to be input and / or output with the shared recording device,
When a failure occurs in the active control device, the memory control unit of the active control device monitors the state of the data buffer, and when the processing of the data buffer is completed, the communication line The switching information is transmitted to the standby control device via the switch, and the active system and the standby system are switched, and the control device that has been the standby system is switched to the active system and starts operating. The data duplexing apparatus according to claim 1, wherein: The memory control unit, when the address of the data read request from the CPU of the active control device corresponds to a memory area where the flag information is invalid, after the data read from the shared recording device is completed, The address is increased, and the increased address is within the prefetch range of the memory control unit, and an access request from the CPU of the active control device is generated in an area other than the prefetch range. 6. The data duplicating apparatus according to claim 5 , wherein when there is no data, prefetching of data is executed from the shared recording apparatus. The memory control unit increases the address, and when an access request from the CPU of the active control device is generated for a memory area other than the prefetch range, the memory control unit 8. The data duplexer according to claim 7 , wherein an access request from the CPU is prioritized. The data duplication device according to claim 1 , wherein the memory of the control device is a main memory. When one is the active system, the other is the standby system, and each of the two control devices can be freely switched from the active system to the standby system and from the standby system to the active system,
A shared recording device shared by the two control devices;
Including at least
Each of the two control devices includes a CPU, a memory, and a memory control unit that controls writing and reading of data, and the memory control unit stores data for each predetermined memory area with respect to the memory. A data duplication method by a duplication device having flag information indicating validity / invalidity of
While the active control device is in operation, the memory control unit of the active control device uses the write data from the CPU of the active control device based on the flag information as the active control device. Storing and holding in the memory and the shared recording device,
In response to a data read request from the CPU of the active control device, based on the flag information, data is read from the memory of the active control device or the shared recording device, and the read data is read from the active control device. Supplying to the CPU of the control device;
Only including,
A communication line for notifying system switching from the active control device to the standby control device is provided,
When switching the standby control device from the standby system to the active system, the memory control unit of the control device switched from the standby system to the active system,
Determining whether the flag information of the memory area corresponding to the access address is valid when receiving a data access request from the CPU of the own device;
If the flag information is invalid as a result of the determination,
Reading data corresponding to the access address from the shared recording device;
When the access is data writing, the data read from the shared recording device and the write data from the CPU are merged, and the merged data is written to the memory and the shared recording device;
When the access is data read, the read data from the shared recording device is supplied to the CPU and written to the memory to validate the flag information;
Have
On the other hand, if the flag information is valid as a result of the determination,
When the access is data writing, writing data into the memory and the shared recording device;
When the access is data read, control is performed to read data from the memory and supply the data to the CPU;
A data duplication method characterized by comprising:

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